opcodes/ChangeLog

   1 2019-11-11  Jan Beulich  <jbeulich@suse.com>
   2
   3         * aarch64-opc.c (operand_general_constraint_met_p): Replace
   4         "index" local variable by that of the already existing "num".
   5
   6 2019-11-08  H.J. Lu  <hongjiu.lu@intel.com>
   7
   8         PR gas/25167
   9         * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
  10         * i386-tbl.h: Regenerated.
  11
  12 2019-11-08  Jan Beulich  <jbeulich@suse.com>
  13
  14         * i386-gen.c (operand_type_init): Add Class= to
  15         OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
  16         OPERAND_TYPE_REGBND entry.
  17         (operand_classes): Add RegMask and RegBND entries.
  18         (operand_types): Drop RegMask and RegBND entry.
  19         * i386-opc.h (enum operand_class): Add RegMask and RegBND.
  20         (RegMask, RegBND): Delete.
  21         (union i386_operand_type): Remove regmask and regbnd fields.
  22         * i386-opc.tbl (RegMask, RegBND): Define.
  23         * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
  24         Class=RegBND.
  25         * i386-init.h, i386-tbl.h: Re-generate.
  26
  27 2019-11-08  Jan Beulich  <jbeulich@suse.com>
  28
  29         * i386-gen.c (operand_type_init): Add Class= to
  30         OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
  31         OPERAND_TYPE_REGZMM entries.
  32         (operand_classes): Add RegMMX and RegSIMD entries.
  33         (operand_types): Drop RegMMX and RegSIMD entries.
  34         * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
  35         (RegMMX, RegSIMD): Delete.
  36         (union i386_operand_type): Remove regmmx and regsimd fields.
  37         * i386-opc.tbl (RegMMX): Define.
  38         (RegXMM, RegYMM, RegZMM): Add Class=.
  39         * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
  40         Class=RegSIMD.
  41         * i386-init.h, i386-tbl.h: Re-generate.
  42
  43 2019-11-08  Jan Beulich  <jbeulich@suse.com>
  44
  45         * i386-gen.c (operand_type_init): Add Class= to
  46         OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
  47         entries.
  48         (operand_classes): Add RegCR, RegDR, and RegTR entries.
  49         (operand_types): Drop Control, Debug, and Test entries.
  50         * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
  51         (Control, Debug, Test): Delete.
  52         (union i386_operand_type): Remove control, debug, and test
  53         fields.
  54         * i386-opc.tbl (Control, Debug, Test): Define.
  55         * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
  56         Class=RegDR, and Test by Class=RegTR.
  57         * i386-init.h, i386-tbl.h: Re-generate.
  58
  59 2019-11-08  Jan Beulich  <jbeulich@suse.com>
  60
  61         * i386-gen.c (operand_type_init): Add Class= to
  62         OPERAND_TYPE_SREG entry.
  63         (operand_classes): Add SReg entry.
  64         (operand_types): Drop SReg entry.
  65         * i386-opc.h (enum operand_class): Add SReg.
  66         (SReg): Delete.
  67         (union i386_operand_type): Remove sreg field.
  68         * i386-opc.tbl (SReg): Define.
  69         * i386-reg.tbl: Replace SReg by Class=SReg.
  70         * i386-init.h, i386-tbl.h: Re-generate.
  71
  72 2019-11-08  Jan Beulich  <jbeulich@suse.com>
  73
  74         * i386-gen.c (operand_type_init): Add Class=. New
  75         OPERAND_TYPE_ANYIMM entry.
  76         (operand_classes): New.
  77         (operand_types): Drop Reg entry.
  78         (output_operand_type): New parameter "class". Process it.
  79         (process_i386_operand_type): New local variable "class".
  80         (main): Adjust static assertions.
  81         * i386-opc.h (CLASS_WIDTH): Define.
  82         (enum operand_class): New.
  83         (Reg): Replace by Class. Adjust comment.
  84         (union i386_operand_type): Replace reg by class.
  85         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
  86         Class=.
  87         * i386-reg.tbl: Replace Reg by Class=Reg.
  88         * i386-init.h: Re-generate.
  89
  90 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
  91
  92         * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
  93         (aarch64_opcode_table): Add data gathering hint mnemonic.
  94         * opcodes/aarch64-dis-2.c: Account for new instruction.
  95
  96 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
  97
  98         * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
  99
 100
 101 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 102
 103         * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
 104         aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
 105         aarch64_feature_f64mm): New feature sets.
 106         (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
 107         F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
 108         instructions.
 109         (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
 110         macros.
 111         (QL_MMLA64, OP_SVE_SBB): New qualifiers.
 112         (OP_SVE_QQQ): New qualifier.
 113         (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
 114         F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
 115         the movprfx constraint.
 116         (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
 117         (aarch64_opcode_table): Define new instructions smmla,
 118         ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
 119         uzip{1/2}, trn{1/2}.
 120         * aarch64-opc.c (operand_general_constraint_met_p): Handle
 121         AARCH64_OPND_SVE_ADDR_RI_S4x32.
 122         (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
 123         * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
 124         Account for new instructions.
 125         * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
 126         S4x32 operand.
 127         * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
 128
 129 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 130 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 131
 132         * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
 133         Armv8.6-A.
 134         (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
 135         (neon_opcodes): Add bfloat SIMD instructions.
 136         (print_insn_coprocessor): Add new control character %b to print
 137         condition code without checking cp_num.
 138         (print_insn_neon): Account for BFloat16 instructions that have no
 139         special top-byte handling.
 140
 141 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 142 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 143
 144         * arm-dis.c (print_insn_coprocessor,
 145         print_insn_generic_coprocessor): Create wrapper functions around
 146         the implementation of the print_insn_coprocessor control codes.
 147         (print_insn_coprocessor_1): Original print_insn_coprocessor
 148         function that now takes which array to look at as an argument.
 149         (print_insn_arm): Use both print_insn_coprocessor and
 150         print_insn_generic_coprocessor.
 151         (print_insn_thumb32): As above.
 152
 153 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 154 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 155
 156         * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
 157         in reglane special case.
 158         * aarch64-dis-2.c (aarch64_opcode_lookup_1,
 159         aarch64_find_next_opcode): Account for new instructions.
 160         * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
 161         in reglane special case.
 162         * aarch64-opc.c (struct operand_qualifier_data): Add data for
 163         new AARCH64_OPND_QLF_S_2H qualifier.
 164         * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
 165         QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
 166         (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
 167         sets.
 168         (BFLOAT_SVE, BFLOAT): New feature set macros.
 169         (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
 170         instructions.
 171         (aarch64_opcode_table): Define new instructions bfdot,
 172         bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
 173         bfcvtn2, bfcvt.
 174
 175 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 176 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 177
 178         * aarch64-tbl.h (ARMV8_6): New macro.
 179
 180 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 181
 182         * i386-dis.c (prefix_table): Add mcommit.
 183         (rm_table): Add rdpru.
 184         * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
 185         CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
 186         (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
 187         * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
 188         (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
 189         * i386-opc.tbl (mcommit, rdpru): New.
 190         * i386-init.h, i386-tbl.h: Re-generate.
 191
 192 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 193
 194         * i386-dis.c (OP_Mwait): Drop local variable "names", use
 195         "names32" instead.
 196         (OP_Monitor): Drop local variable "op1_names", re-purpose
 197         "names" for it instead, and replace former "names" uses by
 198         "names32" ones.
 199
 200 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 201
 202         PR/gas 25167
 203         * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
 204         operand-less forms.
 205         * opcodes/i386-tbl.h: Re-generate.
 206
 207 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 208
 209         * i386-dis.c (OP_Mwaitx): Delete.
 210         (prefix_table): Use OP_Mwait for mwaitx entry.
 211         (OP_Mwait): Also handle mwaitx.
 212
 213 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 214
 215         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
 216         PREFIX_0F01_REG_7_MOD_3_RM_3): New.
 217         (prefix_table): Add respective entries.
 218         (rm_table): Link to those entries.
 219
 220 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 221
 222         * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
 223         (REG_0F1C_P_0_MOD_0): ... this.
 224         (REG_0F1E_MOD_3): Rename to ...
 225         (REG_0F1E_P_1_MOD_3): ... this.
 226         (RM_0F01_REG_5): Rename to ...
 227         (RM_0F01_REG_5_MOD_3): ... this.
 228         (RM_0F01_REG_7): Rename to ...
 229         (RM_0F01_REG_7_MOD_3): ... this.
 230         (RM_0F1E_MOD_3_REG_7): Rename to ...
 231         (RM_0F1E_P_1_MOD_3_REG_7): ... this.
 232         (RM_0FAE_REG_6): Rename to ...
 233         (RM_0FAE_REG_6_MOD_3_P_0): ... this.
 234         (RM_0FAE_REG_7): Rename to ...
 235         (RM_0FAE_REG_7_MOD_3): ... this.
 236         (PREFIX_MOD_0_0F01_REG_5): Rename to ...
 237         (PREFIX_0F01_REG_5_MOD_0): ... this.
 238         (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
 239         (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
 240         (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
 241         (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
 242         (PREFIX_0FAE_REG_0): Rename to ...
 243         (PREFIX_0FAE_REG_0_MOD_3): ... this.
 244         (PREFIX_0FAE_REG_1): Rename to ...
 245         (PREFIX_0FAE_REG_1_MOD_3): ... this.
 246         (PREFIX_0FAE_REG_2): Rename to ...
 247         (PREFIX_0FAE_REG_2_MOD_3): ... this.
 248         (PREFIX_0FAE_REG_3): Rename to ...
 249         (PREFIX_0FAE_REG_3_MOD_3): ... this.
 250         (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
 251         (PREFIX_0FAE_REG_4_MOD_0): ... this.
 252         (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
 253         (PREFIX_0FAE_REG_4_MOD_3): ... this.
 254         (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
 255         (PREFIX_0FAE_REG_5_MOD_0): ... this.
 256         (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
 257         (PREFIX_0FAE_REG_5_MOD_3): ... this.
 258         (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
 259         (PREFIX_0FAE_REG_6_MOD_0): ... this.
 260         (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
 261         (PREFIX_0FAE_REG_6_MOD_3): ... this.
 262         (PREFIX_0FAE_REG_7): Rename to ...
 263         (PREFIX_0FAE_REG_7_MOD_0): ... this.
 264         (PREFIX_MOD_0_0FC3): Rename to ...
 265         (PREFIX_0FC3_MOD_0): ... this.
 266         (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
 267         (PREFIX_0FC7_REG_6_MOD_0): ... this.
 268         (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
 269         (PREFIX_0FC7_REG_6_MOD_3): ... this.
 270         (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
 271         (PREFIX_0FC7_REG_7_MOD_3): ... this.
 272         (reg_table, prefix_table, mod_table, rm_table): Adjust
 273         accordingly.
 274
 275 2019-11-04  Nick Clifton  <nickc@redhat.com>
 276
 277         * v850-dis.c (get_v850_sreg_name): New function.  Returns the name
 278         of a v850 system register.  Move the v850_sreg_names array into
 279         this function.
 280         (get_v850_reg_name): Likewise for ordinary register names.
 281         (get_v850_vreg_name): Likewise for vector register names.
 282         (get_v850_cc_name): Likewise for condition codes.
 283         * get_v850_float_cc_name): Likewise for floating point condition
 284         codes.
 285         (get_v850_cacheop_name): Likewise for cache-ops.
 286         (get_v850_prefop_name): Likewise for pref-ops.
 287         (disassemble): Use the new accessor functions.
 288
 289 2019-10-30  Delia Burduv   <delia.burduv@arm.com>
 290
 291         * aarch64-opc.c (print_immediate_offset_address): Don't print the
 292         immediate for the writeback form of ldraa/ldrab if it is 0.
 293         * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
 294         * aarch64-opc-2.c: Regenerated.
 295
 296 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 297
 298         * i386-gen.c (operand_type_shorthands): Delete.
 299         (operand_type_init): Expand previous shorthands.
 300         (set_bitfield_from_shorthand): Rename back to ...
 301         (set_bitfield_from_cpu_flag_init): ... this.  Drop processing
 302         of operand_type_init[].
 303         (set_bitfield): Adjust call to the above function.
 304         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
 305         RegXMM, RegYMM, RegZMM): Define.
 306         * i386-reg.tbl: Expand prior shorthands.
 307
 308 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 309
 310         * i386-gen.c (output_i386_opcode): Change order of fields
 311         emitted to output.
 312         * i386-opc.h (struct insn_template): Move operands field.
 313         Convert extension_opcode field to unsigned short.
 314         * i386-tbl.h: Re-generate.
 315
 316 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 317
 318         * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
 319         of W.
 320         * i386-opc.h (W): Extend comment.
 321         * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
 322         general purpose variants not allowing for byte operands.
 323         * i386-tbl.h: Re-generate.
 324
 325 2019-10-29  Nick Clifton  <nickc@redhat.com>
 326
 327         * tic30-dis.c (print_branch): Correct size of operand array.
 328
 329 2019-10-29  Nick Clifton  <nickc@redhat.com>
 330
 331         * d30v-dis.c (print_insn): Check that operand index is valid
 332         before attempting to access the operands array.
 333
 334 2019-10-29  Nick Clifton  <nickc@redhat.com>
 335
 336         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
 337         locating the bit to be tested.
 338
 339 2019-10-29  Nick Clifton  <nickc@redhat.com>
 340
 341         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
 342         values.
 343         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
 344         (print_insn_s12z):  Check for illegal size values.
 345
 346 2019-10-28  Nick Clifton  <nickc@redhat.com>
 347
 348         * csky-dis.c (csky_chars_to_number): Check for a negative
 349         count. Use an unsigned integer to construct the return value.
 350
 351 2019-10-28  Nick Clifton  <nickc@redhat.com>
 352
 353         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
 354         operand buffer.  Set value to 15 not 13.
 355         (get_register_operand): Use OPERAND_BUFFER_LEN.
 356         (get_indirect_operand): Likewise.
 357         (print_two_operand): Likewise.
 358         (print_three_operand): Likewise.
 359         (print_oar_insn): Likewise.
 360
 361 2019-10-28  Nick Clifton  <nickc@redhat.com>
 362
 363         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
 364         (bit_extract_simple): Likewise.
 365         (bit_copy): Likewise.
 366         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
 367         index_offset array are not accessed.
 368
 369 2019-10-28  Nick Clifton  <nickc@redhat.com>
 370
 371         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
 372         operand.
 373
 374 2019-10-25  Nick Clifton  <nickc@redhat.com>
 375
 376         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
 377         access to opcodes.op array element.
 378
 379 2019-10-23  Nick Clifton  <nickc@redhat.com>
 380
 381         * rx-dis.c (get_register_name): Fix spelling typo in error
 382         message.
 383         (get_condition_name, get_flag_name, get_double_register_name)
 384         (get_double_register_high_name, get_double_register_low_name)
 385         (get_double_control_register_name, get_double_condition_name)
 386         (get_opsize_name, get_size_name): Likewise.
 387
 388 2019-10-22  Nick Clifton  <nickc@redhat.com>
 389
 390         * rx-dis.c (get_size_name): New function.  Provides safe
 391         access to name array.
 392         (get_opsize_name): Likewise.
 393         (print_insn_rx): Use the accessor functions.
 394
 395 2019-10-16  Nick Clifton  <nickc@redhat.com>
 396
 397         * rx-dis.c (get_register_name): New function.  Provides safe
 398         access to name array.
 399         (get_condition_name, get_flag_name, get_double_register_name)
 400         (get_double_register_high_name, get_double_register_low_name)
 401         (get_double_control_register_name, get_double_condition_name):
 402         Likewise.
 403         (print_insn_rx): Use the accessor functions.
 404
 405 2019-10-09  Nick Clifton  <nickc@redhat.com>
 406
 407         PR 25041
 408         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
 409         instructions.
 410
 411 2019-10-07  Jan Beulich  <jbeulich@suse.com>
 412
 413         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
 414         (cmpsd): Likewise. Move EsSeg to other operand.
 415         * opcodes/i386-tbl.h: Re-generate.
 416
 417 2019-09-23  Alan Modra  <amodra@gmail.com>
 418
 419         * m68k-dis.c: Include cpu-m68k.h
 420
 421 2019-09-23  Alan Modra  <amodra@gmail.com>
 422
 423         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
 424         "elf/mips.h" earlier.
 425
 426 2018-09-20  Jan Beulich  <jbeulich@suse.com>
 427
 428         PR gas/25012
 429         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 430         with SReg operand.
 431         * i386-tbl.h: Re-generate.
 432
 433 2019-09-18  Alan Modra  <amodra@gmail.com>
 434
 435         * arc-ext.c: Update throughout for bfd section macro changes.
 436
 437 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 438
 439         * Makefile.in: Re-generate.
 440         * configure: Re-generate.
 441
 442 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 443
 444         * riscv-opc.c (riscv_opcodes): Change subset field
 445         to insn_class field for all instructions.
 446         (riscv_insn_types): Likewise.
 447
 448 2019-09-16  Phil Blundell  <pb@pbcl.net>
 449
 450         * configure: Regenerated.
 451
 452 2019-09-10  Miod Vallat  <miod@online.fr>
 453
 454         PR 24982
 455         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 456
 457 2019-09-09  Phil Blundell  <pb@pbcl.net>
 458
 459         binutils 2.33 branch created.
 460
 461 2019-09-03  Nick Clifton  <nickc@redhat.com>
 462
 463         PR 24961
 464         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 465         greater than zero before indexing via (bufcnt -1).
 466
 467 2019-09-03  Nick Clifton  <nickc@redhat.com>
 468
 469         PR 24958
 470         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 471         (MAX_SPEC_REG_NAME_LEN): Define.
 472         (struct mmix_dis_info): Use defined constants for array lengths.
 473         (get_reg_name): New function.
 474         (get_sprec_reg_name): New function.
 475         (print_insn_mmix): Use new functions.
 476
 477 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 478
 479         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 480         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 481         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 482
 483 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 484
 485         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 486         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 487         (aarch64_sys_reg_supported_p): Update checks for the above.
 488
 489 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 490
 491         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 492         cases MVE_SQRSHRL and MVE_UQRSHLL.
 493         (print_insn_mve): Add case for specifier 'k' to check
 494         specific bit of the instruction.
 495
 496 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 497
 498         PR 24854
 499         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 500         encountering an unknown machine type.
 501         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 502         cases return -1 rather than calling abort.
 503
 504 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 505
 506         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 507         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 508         IgnoreSize.
 509         * i386-tbl.h: Re-generate.
 510
 511 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 512
 513         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 514         instructions.
 515
 516 2019-07-30  Mel Chen <mel.chen@sifive.com>
 517
 518         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 519         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 520
 521         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 522         fscsr.
 523
 524 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 525
 526         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 527         and MPY class instructions.
 528         (parse_option): Add nps400 option.
 529         (print_arc_disassembler_options): Add nps400 info.
 530
 531 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 532
 533         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 534         (bspop): Likewise.
 535         (modapp): Likewise.
 536         * arc-opc.c (RAD_CHK): Add.
 537         * arc-tbl.h: Regenerate.
 538
 539 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 540
 541         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 542         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 543
 544 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 545
 546         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 547         instructions as UNPREDICTABLE.
 548
 549 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 550
 551         * bpf-desc.c: Regenerated.
 552
 553 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 554
 555         * i386-gen.c (static_assert): Define.
 556         (main): Use it.
 557         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 558         (Opcode_Modifier_Num): ... this.
 559         (Mem): Delete.
 560
 561 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 562
 563         * i386-gen.c (operand_types): Move RegMem ...
 564         (opcode_modifiers): ... here.
 565         * i386-opc.h (RegMem): Move to opcode modifer enum.
 566         (union i386_operand_type): Move regmem field ...
 567         (struct i386_opcode_modifier): ... here.
 568         * i386-opc.tbl (RegMem): Define.
 569         (mov, movq): Move RegMem on segment, control, debug, and test
 570         register flavors.
 571         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 572         to non-SSE2AVX flavor.
 573         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 574         Move RegMem on register only flavors. Drop IgnoreSize from
 575         legacy encoding flavors.
 576         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 577         flavors.
 578         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 579         register only flavors.
 580         (vmovd): Move RegMem and drop IgnoreSize on register only
 581         flavor. Change opcode and operand order to store form.
 582         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 583
 584 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 585
 586         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 587         entries.
 588         * i386-opc.h (SReg2, SReg3): Replace by ...
 589         (SReg): ... this.
 590         (union i386_operand_type): Replace sreg fields.
 591         * i386-opc.tbl (mov, ): Use SReg.
 592         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 593         register flavors.
 594         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 595         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 596
 597 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 598
 599         * bpf-desc.c: Regenerate.
 600         * bpf-opc.c: Likewise.
 601         * bpf-opc.h: Likewise.
 602
 603 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 604
 605         * bpf-desc.c: Regenerate.
 606         * bpf-opc.c: Likewise.
 607
 608 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 609
 610         * arm-dis.c (print_insn_coprocessor): Rename index to
 611         index_operand.
 612
 613 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 614
 615         * riscv-opc.c (riscv_insn_types): Add r4 type.
 616
 617         * riscv-opc.c (riscv_insn_types): Add b and j type.
 618
 619         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 620         format for sb type and correct s type.
 621
 622 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 623
 624         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 625         SVE FMOV alias of FCPY.
 626
 627 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 628
 629         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 630         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 631
 632 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 633
 634         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 635         registers in an instruction prefixed by MOVPRFX.
 636
 637 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 638
 639         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 640         sve_size_13 icode to account for variant behaviour of
 641         pmull{t,b}.
 642         * aarch64-dis-2.c: Regenerate.
 643         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 644         sve_size_13 icode to account for variant behaviour of
 645         pmull{t,b}.
 646         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 647         (OP_SVE_VVV_Q_D): Add new qualifier.
 648         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 649         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 650         AES and those not.
 651
 652 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 653
 654         * opcodes/i386-gen.c (operand_type_init): Remove
 655         OPERAND_TYPE_VEC_IMM4 entry.
 656         (operand_types): Remove Vec_Imm4.
 657         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 658         (union i386_operand_type): Remove vec_imm4.
 659         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 660         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 661
 662 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 663
 664         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 665         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 666         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 667         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 668         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 669         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 670         * i386-tbl.h: Re-generate.
 671
 672 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 673
 674         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 675         register operands.
 676         * i386-tbl.h: Re-generate.
 677
 678 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 679
 680         * i386-opc.tbl (C): New.
 681         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 682         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 683         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 684         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 685         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 686         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 687         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 688         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 689         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 690         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 691         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 692         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 693         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 694         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 695         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 696         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 697         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 698         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 699         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 700         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 701         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 702         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 703         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 704         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 705         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 706         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 707         flavors.
 708         * i386-tbl.h: Re-generate.
 709
 710 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 711
 712         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 713         register operands.
 714         * i386-tbl.h: Re-generate.
 715
 716 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 717
 718         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 719         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 720         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 721         * i386-tbl.h: Re-generate.
 722
 723 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 724
 725         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 726         Disp8MemShift from register only templates.
 727         * i386-tbl.h: Re-generate.
 728
 729 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 730
 731         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 732         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 733         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 734         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 735         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 736         EVEX_W_0F11_P_3_M_1): Delete.
 737         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 738         EVEX_W_0F11_P_3): New.
 739         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 740         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 741         MOD_EVEX_0F11_PREFIX_3 table entries.
 742         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 743         PREFIX_EVEX_0F11 table entries.
 744         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 745         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 746         EVEX_W_0F11_P_3_M_{0,1} table entries.
 747
 748 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 749
 750         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 751         Delete.
 752
 753 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 754
 755         PR binutils/24719
 756         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 757         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 758         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 759         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 760         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 761         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 762         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 763         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 764         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 765         PREFIX_EVEX_0F38C6_REG_6 entries.
 766         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 767         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 768         EVEX_W_0F38C7_R_6_P_2 entries.
 769         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 770         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 771         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 772         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 773         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 774         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 775         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 776
 777 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 778
 779         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 780         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 781         VEX_LEN_0F2D_P_3): Delete.
 782         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 783         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 784         (prefix_table): ... here.
 785
 786 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 787
 788         * i386-dis.c (Iq): Delete.
 789         (Id): New.
 790         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 791         TBM insns.
 792         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 793         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 794         (OP_E_memory): Also honor needindex when deciding whether an
 795         address size prefix needs printing.
 796         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 797
 798 2019-06-26  Jim Wilson  <jimw@sifive.com>
 799
 800         PR binutils/24739
 801         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 802         Set info->display_endian to info->endian_code.
 803
 804 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 805
 806         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 807         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 808         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 809         OPERAND_TYPE_ACC64 entries.
 810         * i386-init.h: Re-generate.
 811
 812 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 813
 814         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 815         Delete.
 816         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 817         of dqa_mode.
 818         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 819         entries here.
 820         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 821         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 822
 823 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 824
 825         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 826         variables.
 827
 828 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 829
 830         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 831         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 832         movnti.
 833         * i386-opc.tbl (movnti): Add IgnoreSize.
 834         * i386-tbl.h: Re-generate.
 835
 836 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 837
 838         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 839         * i386-tbl.h: Re-generate.
 840
 841 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 842
 843         * i386-dis-evex.h: Break into ...
 844         * i386-dis-evex-len.h: New file.
 845         * i386-dis-evex-mod.h: Likewise.
 846         * i386-dis-evex-prefix.h: Likewise.
 847         * i386-dis-evex-reg.h: Likewise.
 848         * i386-dis-evex-w.h: Likewise.
 849         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 850         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 851         i386-dis-evex-mod.h.
 852
 853 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 854
 855         PR binutils/24700
 856         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 857         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 858         EVEX_W_0F385B_P_2.
 859         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 860         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 861         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 862         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 863         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 864         EVEX_LEN_0F385B_P_2_W_1.
 865         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 866         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 867         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 868         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 869         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 870         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 871         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 872         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 873         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 874         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 875
 876 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 877
 878         PR binutils/24691
 879         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 880         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 881         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 882         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 883         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 884         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 885         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 886         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 887         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 888         EVEX_LEN_0F3A43_P_2_W_1.
 889         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 890         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 891         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 892         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 893         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 894         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 895         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 896         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 897         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 898         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 899         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 900         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 901
 902 2019-06-14  Nick Clifton  <nickc@redhat.com>
 903
 904         * po/fr.po; Updated French translation.
 905
 906 2019-06-13  Stafford Horne  <shorne@gmail.com>
 907
 908         * or1k-asm.c: Regenerated.
 909         * or1k-desc.c: Regenerated.
 910         * or1k-desc.h: Regenerated.
 911         * or1k-dis.c: Regenerated.
 912         * or1k-ibld.c: Regenerated.
 913         * or1k-opc.c: Regenerated.
 914         * or1k-opc.h: Regenerated.
 915         * or1k-opinst.c: Regenerated.
 916
 917 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 918
 919         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 920
 921 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 922
 923         PR binutils/24633
 924         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 925         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 926         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 927         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 928         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 929         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 930         EVEX_LEN_0F3A1B_P_2_W_1.
 931         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 932         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 933         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 934         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 935         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 936         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 937         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 938         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 939
 940 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 941
 942         PR binutils/24626
 943         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 944         EVEX.vvvv when disassembling VEX and EVEX instructions.
 945         (OP_VEX): Set vex.register_specifier to 0 after readding
 946         vex.register_specifier.
 947         (OP_Vex_2src_1): Likewise.
 948         (OP_Vex_2src_2): Likewise.
 949         (OP_LWP_E): Likewise.
 950         (OP_EX_Vex): Don't check vex.register_specifier.
 951         (OP_XMM_Vex): Likewise.
 952
 953 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 954             Lili Cui  <lili.cui@intel.com>
 955
 956         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 957         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 958         instructions.
 959         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 960         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 961         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 962         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 963         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 964         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 965         * i386-init.h: Regenerated.
 966         * i386-tbl.h: Likewise.
 967
 968 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 969             Lili Cui  <lili.cui@intel.com>
 970
 971         * doc/c-i386.texi: Document enqcmd.
 972         * testsuite/gas/i386/enqcmd-intel.d: New file.
 973         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 974         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 975         * testsuite/gas/i386/enqcmd.d: Likewise.
 976         * testsuite/gas/i386/enqcmd.s: Likewise.
 977         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 978         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 979         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 980         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 981         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 982         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 983         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 984         and x86-64-enqcmd.
 985
 986 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 987
 988         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 989
 990 2019-06-03  Alan Modra  <amodra@gmail.com>
 991
 992         * ppc-dis.c (prefix_opcd_indices): Correct size.
 993
 994 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 995
 996         PR gas/24625
 997         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 998         Disp8ShiftVL.
 999         * i386-tbl.h: Regenerated.
1000
1001 2019-05-24  Alan Modra  <amodra@gmail.com>
1002
1003         * po/POTFILES.in: Regenerate.
1004
1005 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1006             Alan Modra  <amodra@gmail.com>
1007
1008         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1009         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1010         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1011         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1012         XTOP>): Define and add entries.
1013         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1014         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1015         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1016         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1017
1018 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1019             Alan Modra  <amodra@gmail.com>
1020
1021         * ppc-dis.c (ppc_opts): Add "future" entry.
1022         (PREFIX_OPCD_SEGS): Define.
1023         (prefix_opcd_indices): New array.
1024         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1025         (lookup_prefix): New function.
1026         (print_insn_powerpc): Handle 64-bit prefix instructions.
1027         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1028         (PMRR, POWERXX): Define.
1029         (prefix_opcodes): New instruction table.
1030         (prefix_num_opcodes): New constant.
1031
1032 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
1033
1034         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1035         * configure: Regenerated.
1036         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1037         and cpu/bpf.opc.
1038         (HFILES): Add bpf-desc.h and bpf-opc.h.
1039         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1040         bpf-ibld.c and bpf-opc.c.
1041         (BPF_DEPS): Define.
1042         * Makefile.in: Regenerated.
1043         * disassemble.c (ARCH_bpf): Define.
1044         (disassembler): Add case for bfd_arch_bpf.
1045         (disassemble_init_for_target): Likewise.
1046         (enum epbf_isa_attr): Define.
1047         * disassemble.h: extern print_insn_bpf.
1048         * bpf-asm.c: Generated.
1049         * bpf-opc.h: Likewise.
1050         * bpf-opc.c: Likewise.
1051         * bpf-ibld.c: Likewise.
1052         * bpf-dis.c: Likewise.
1053         * bpf-desc.h: Likewise.
1054         * bpf-desc.c: Likewise.
1055
1056 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1057
1058         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1059         and VMSR with the new operands.
1060
1061 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1062
1063         * arm-dis.c (enum mve_instructions): New enum
1064         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1065         and cneg.
1066         (mve_opcodes): New instructions as above.
1067         (is_mve_encoding_conflict): Add cases for csinc, csinv,
1068         csneg and csel.
1069         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1070
1071 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1072
1073         * arm-dis.c (emun mve_instructions): Updated for new instructions.
1074         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1075         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1076         uqshl, urshrl and urshr.
1077         (is_mve_okay_in_it): Add new instructions to TRUE list.
1078         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1079         (print_insn_mve): Updated to accept new %j,
1080         %<bitfield>m and %<bitfield>n patterns.
1081
1082 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1083
1084         * mips-opc.c (mips_builtin_opcodes): Change source register
1085         constraint for DAUI.
1086
1087 2019-05-20  Nick Clifton  <nickc@redhat.com>
1088
1089         * po/fr.po: Updated French translation.
1090
1091 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1092             Michael Collison <michael.collison@arm.com>
1093
1094         * arm-dis.c (thumb32_opcodes): Add new instructions.
1095         (enum mve_instructions): Likewise.
1096         (enum mve_undefined): Add new reasons.
1097         (is_mve_encoding_conflict): Handle new instructions.
1098         (is_mve_undefined): Likewise.
1099         (is_mve_unpredictable): Likewise.
1100         (print_mve_undefined): Likewise.
1101         (print_mve_size): Likewise.
1102
1103 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1104             Michael Collison <michael.collison@arm.com>
1105
1106         * arm-dis.c (thumb32_opcodes): Add new instructions.
1107         (enum mve_instructions): Likewise.
1108         (is_mve_encoding_conflict): Handle new instructions.
1109         (is_mve_undefined): Likewise.
1110         (is_mve_unpredictable): Likewise.
1111         (print_mve_size): Likewise.
1112
1113 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1114             Michael Collison <michael.collison@arm.com>
1115
1116         * arm-dis.c (thumb32_opcodes): Add new instructions.
1117         (enum mve_instructions): Likewise.
1118         (is_mve_encoding_conflict): Likewise.
1119         (is_mve_unpredictable): Likewise.
1120         (print_mve_size): Likewise.
1121
1122 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1123             Michael Collison <michael.collison@arm.com>
1124
1125         * arm-dis.c (thumb32_opcodes): Add new instructions.
1126         (enum mve_instructions): Likewise.
1127         (is_mve_encoding_conflict): Handle new instructions.
1128         (is_mve_undefined): Likewise.
1129         (is_mve_unpredictable): Likewise.
1130         (print_mve_size): Likewise.
1131
1132 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1133             Michael Collison <michael.collison@arm.com>
1134
1135         * arm-dis.c (thumb32_opcodes): Add new instructions.
1136         (enum mve_instructions): Likewise.
1137         (is_mve_encoding_conflict): Handle new instructions.
1138         (is_mve_undefined): Likewise.
1139         (is_mve_unpredictable): Likewise.
1140         (print_mve_size): Likewise.
1141         (print_insn_mve): Likewise.
1142
1143 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1144             Michael Collison <michael.collison@arm.com>
1145
1146         * arm-dis.c (thumb32_opcodes): Add new instructions.
1147         (print_insn_thumb32): Handle new instructions.
1148
1149 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1150             Michael Collison <michael.collison@arm.com>
1151
1152         * arm-dis.c (enum mve_instructions): Add new instructions.
1153         (enum mve_undefined): Add new reasons.
1154         (is_mve_encoding_conflict): Handle new instructions.
1155         (is_mve_undefined): Likewise.
1156         (is_mve_unpredictable): Likewise.
1157         (print_mve_undefined): Likewise.
1158         (print_mve_size): Likewise.
1159         (print_mve_shift_n): Likewise.
1160         (print_insn_mve): Likewise.
1161
1162 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1163             Michael Collison <michael.collison@arm.com>
1164
1165         * arm-dis.c (enum mve_instructions): Add new instructions.
1166         (is_mve_encoding_conflict): Handle new instructions.
1167         (is_mve_unpredictable): Likewise.
1168         (print_mve_rotate): Likewise.
1169         (print_mve_size): Likewise.
1170         (print_insn_mve): Likewise.
1171
1172 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1173             Michael Collison <michael.collison@arm.com>
1174
1175         * arm-dis.c (enum mve_instructions): Add new instructions.
1176         (is_mve_encoding_conflict): Handle new instructions.
1177         (is_mve_unpredictable): Likewise.
1178         (print_mve_size): Likewise.
1179         (print_insn_mve): Likewise.
1180
1181 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1182             Michael Collison <michael.collison@arm.com>
1183
1184         * arm-dis.c (enum mve_instructions): Add new instructions.
1185         (enum mve_undefined): Add new reasons.
1186         (is_mve_encoding_conflict): Handle new instructions.
1187         (is_mve_undefined): Likewise.
1188         (is_mve_unpredictable): Likewise.
1189         (print_mve_undefined): Likewise.
1190         (print_mve_size): Likewise.
1191         (print_insn_mve): Likewise.
1192
1193 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1194             Michael Collison <michael.collison@arm.com>
1195
1196         * arm-dis.c (enum mve_instructions): Add new instructions.
1197         (is_mve_encoding_conflict): Handle new instructions.
1198         (is_mve_undefined): Likewise.
1199         (is_mve_unpredictable): Likewise.
1200         (print_mve_size): Likewise.
1201         (print_insn_mve): Likewise.
1202
1203 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1204             Michael Collison <michael.collison@arm.com>
1205
1206         * arm-dis.c (enum mve_instructions): Add new instructions.
1207         (enum mve_unpredictable): Add new reasons.
1208         (enum mve_undefined): Likewise.
1209         (is_mve_okay_in_it): Handle new isntructions.
1210         (is_mve_encoding_conflict): Likewise.
1211         (is_mve_undefined): Likewise.
1212         (is_mve_unpredictable): Likewise.
1213         (print_mve_vmov_index): Likewise.
1214         (print_simd_imm8): Likewise.
1215         (print_mve_undefined): Likewise.
1216         (print_mve_unpredictable): Likewise.
1217         (print_mve_size): Likewise.
1218         (print_insn_mve): Likewise.
1219
1220 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1221             Michael Collison <michael.collison@arm.com>
1222
1223         * arm-dis.c (enum mve_instructions): Add new instructions.
1224         (enum mve_unpredictable): Add new reasons.
1225         (enum mve_undefined): Likewise.
1226         (is_mve_encoding_conflict): Handle new instructions.
1227         (is_mve_undefined): Likewise.
1228         (is_mve_unpredictable): Likewise.
1229         (print_mve_undefined): Likewise.
1230         (print_mve_unpredictable): Likewise.
1231         (print_mve_rounding_mode): Likewise.
1232         (print_mve_vcvt_size): Likewise.
1233         (print_mve_size): Likewise.
1234         (print_insn_mve): Likewise.
1235
1236 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1237             Michael Collison <michael.collison@arm.com>
1238
1239         * arm-dis.c (enum mve_instructions): Add new instructions.
1240         (enum mve_unpredictable): Add new reasons.
1241         (enum mve_undefined): Likewise.
1242         (is_mve_undefined): Handle new instructions.
1243         (is_mve_unpredictable): Likewise.
1244         (print_mve_undefined): Likewise.
1245         (print_mve_unpredictable): Likewise.
1246         (print_mve_size): Likewise.
1247         (print_insn_mve): Likewise.
1248
1249 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1250             Michael Collison <michael.collison@arm.com>
1251
1252         * arm-dis.c (enum mve_instructions): Add new instructions.
1253         (enum mve_undefined): Add new reasons.
1254         (insns): Add new instructions.
1255         (is_mve_encoding_conflict):
1256         (print_mve_vld_str_addr): New print function.
1257         (is_mve_undefined): Handle new instructions.
1258         (is_mve_unpredictable): Likewise.
1259         (print_mve_undefined): Likewise.
1260         (print_mve_size): Likewise.
1261         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1262         (print_insn_mve):  Handle new operands.
1263
1264 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1265             Michael Collison <michael.collison@arm.com>
1266
1267         * arm-dis.c (enum mve_instructions): Add new instructions.
1268         (enum mve_unpredictable): Add new reasons.
1269         (is_mve_encoding_conflict): Handle new instructions.
1270         (is_mve_unpredictable): Likewise.
1271         (mve_opcodes): Add new instructions.
1272         (print_mve_unpredictable): Handle new reasons.
1273         (print_mve_register_blocks): New print function.
1274         (print_mve_size): Handle new instructions.
1275         (print_insn_mve): Likewise.
1276
1277 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1278             Michael Collison <michael.collison@arm.com>
1279
1280         * arm-dis.c (enum mve_instructions): Add new instructions.
1281         (enum mve_unpredictable): Add new reasons.
1282         (enum mve_undefined): Likewise.
1283         (is_mve_encoding_conflict): Handle new instructions.
1284         (is_mve_undefined): Likewise.
1285         (is_mve_unpredictable): Likewise.
1286         (coprocessor_opcodes): Move NEON VDUP from here...
1287         (neon_opcodes): ... to here.
1288         (mve_opcodes): Add new instructions.
1289         (print_mve_undefined):  Handle new reasons.
1290         (print_mve_unpredictable): Likewise.
1291         (print_mve_size): Handle new instructions.
1292         (print_insn_neon): Handle vdup.
1293         (print_insn_mve): Handle new operands.
1294
1295 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1296             Michael Collison <michael.collison@arm.com>
1297
1298         * arm-dis.c (enum mve_instructions): Add new instructions.
1299         (enum mve_unpredictable): Add new values.
1300         (mve_opcodes): Add new instructions.
1301         (vec_condnames): New array with vector conditions.
1302         (mve_predicatenames): New array with predicate suffixes.
1303         (mve_vec_sizename): New array with vector sizes.
1304         (enum vpt_pred_state): New enum with vector predication states.
1305         (struct vpt_block): New struct type for vpt blocks.
1306         (vpt_block_state): Global struct to keep track of state.
1307         (mve_extract_pred_mask): New helper function.
1308         (num_instructions_vpt_block): Likewise.
1309         (mark_outside_vpt_block): Likewise.
1310         (mark_inside_vpt_block): Likewise.
1311         (invert_next_predicate_state): Likewise.
1312         (update_next_predicate_state): Likewise.
1313         (update_vpt_block_state): Likewise.
1314         (is_vpt_instruction): Likewise.
1315         (is_mve_encoding_conflict): Add entries for new instructions.
1316         (is_mve_unpredictable): Likewise.
1317         (print_mve_unpredictable): Handle new cases.
1318         (print_instruction_predicate): Likewise.
1319         (print_mve_size): New function.
1320         (print_vec_condition): New function.
1321         (print_insn_mve): Handle vpt blocks and new print operands.
1322
1323 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1324
1325         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1326         8, 14 and 15 for Armv8.1-M Mainline.
1327
1328 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1329             Michael Collison <michael.collison@arm.com>
1330
1331         * arm-dis.c (enum mve_instructions): New enum.
1332         (enum mve_unpredictable): Likewise.
1333         (enum mve_undefined): Likewise.
1334         (struct mopcode32): New struct.
1335         (is_mve_okay_in_it): New function.
1336         (is_mve_architecture): Likewise.
1337         (arm_decode_field): Likewise.
1338         (arm_decode_field_multiple): Likewise.
1339         (is_mve_encoding_conflict): Likewise.
1340         (is_mve_undefined): Likewise.
1341         (is_mve_unpredictable): Likewise.
1342         (print_mve_undefined): Likewise.
1343         (print_mve_unpredictable): Likewise.
1344         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1345         (print_insn_mve): New function.
1346         (print_insn_thumb32): Handle MVE architecture.
1347         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1348
1349 2019-05-10  Nick Clifton  <nickc@redhat.com>
1350
1351         PR 24538
1352         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1353         end of the table prematurely.
1354
1355 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1356
1357         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1358         macros for R6.
1359
1360 2019-05-11  Alan Modra  <amodra@gmail.com>
1361
1362         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1363         when -Mraw is in effect.
1364
1365 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1366
1367         * aarch64-dis-2.c: Regenerate.
1368         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1369         (OP_SVE_BBB): New variant set.
1370         (OP_SVE_DDDD): New variant set.
1371         (OP_SVE_HHH): New variant set.
1372         (OP_SVE_HHHU): New variant set.
1373         (OP_SVE_SSS): New variant set.
1374         (OP_SVE_SSSU): New variant set.
1375         (OP_SVE_SHH): New variant set.
1376         (OP_SVE_SBBU): New variant set.
1377         (OP_SVE_DSS): New variant set.
1378         (OP_SVE_DHHU): New variant set.
1379         (OP_SVE_VMV_HSD_BHS): New variant set.
1380         (OP_SVE_VVU_HSD_BHS): New variant set.
1381         (OP_SVE_VVVU_SD_BH): New variant set.
1382         (OP_SVE_VVVU_BHSD): New variant set.
1383         (OP_SVE_VVV_QHD_DBS): New variant set.
1384         (OP_SVE_VVV_HSD_BHS): New variant set.
1385         (OP_SVE_VVV_HSD_BHS2): New variant set.
1386         (OP_SVE_VVV_BHS_HSD): New variant set.
1387         (OP_SVE_VV_BHS_HSD): New variant set.
1388         (OP_SVE_VVV_SD): New variant set.
1389         (OP_SVE_VVU_BHS_HSD): New variant set.
1390         (OP_SVE_VZVV_SD): New variant set.
1391         (OP_SVE_VZVV_BH): New variant set.
1392         (OP_SVE_VZV_SD): New variant set.
1393         (aarch64_opcode_table): Add sve2 instructions.
1394
1395 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1396
1397         * aarch64-asm-2.c: Regenerated.
1398         * aarch64-dis-2.c: Regenerated.
1399         * aarch64-opc-2.c: Regenerated.
1400         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1401         for SVE_SHLIMM_UNPRED_22.
1402         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1403         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1404         operand.
1405
1406 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1407
1408         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1409         sve_size_tsz_bhs iclass encode.
1410         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1411         sve_size_tsz_bhs iclass decode.
1412
1413 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1414
1415         * aarch64-asm-2.c: Regenerated.
1416         * aarch64-dis-2.c: Regenerated.
1417         * aarch64-opc-2.c: Regenerated.
1418         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1419         for SVE_Zm4_11_INDEX.
1420         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1421         (fields): Handle SVE_i2h field.
1422         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1423         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1424
1425 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1426
1427         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1428         sve_shift_tsz_bhsd iclass encode.
1429         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1430         sve_shift_tsz_bhsd iclass decode.
1431
1432 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1433
1434         * aarch64-asm-2.c: Regenerated.
1435         * aarch64-dis-2.c: Regenerated.
1436         * aarch64-opc-2.c: Regenerated.
1437         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1438         (aarch64_encode_variant_using_iclass): Handle
1439         sve_shift_tsz_hsd iclass encode.
1440         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1441         sve_shift_tsz_hsd iclass decode.
1442         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1443         for SVE_SHRIMM_UNPRED_22.
1444         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1445         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1446         operand.
1447
1448 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1449
1450         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1451         sve_size_013 iclass encode.
1452         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1453         sve_size_013 iclass decode.
1454
1455 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1456
1457         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1458         sve_size_bh iclass encode.
1459         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1460         sve_size_bh iclass decode.
1461
1462 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1463
1464         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1465         sve_size_sd2 iclass encode.
1466         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1467         sve_size_sd2 iclass decode.
1468         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1469         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1470
1471 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1472
1473         * aarch64-asm-2.c: Regenerated.
1474         * aarch64-dis-2.c: Regenerated.
1475         * aarch64-opc-2.c: Regenerated.
1476         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1477         for SVE_ADDR_ZX.
1478         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1479         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1480
1481 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1482
1483         * aarch64-asm-2.c: Regenerated.
1484         * aarch64-dis-2.c: Regenerated.
1485         * aarch64-opc-2.c: Regenerated.
1486         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1487         for SVE_Zm3_11_INDEX.
1488         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1489         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1490         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1491         fields.
1492         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1493
1494 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1495
1496         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1497         sve_size_hsd2 iclass encode.
1498         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1499         sve_size_hsd2 iclass decode.
1500         * aarch64-opc.c (fields): Handle SVE_size field.
1501         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1502
1503 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1504
1505         * aarch64-asm-2.c: Regenerated.
1506         * aarch64-dis-2.c: Regenerated.
1507         * aarch64-opc-2.c: Regenerated.
1508         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1509         for SVE_IMM_ROT3.
1510         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1511         (fields): Handle SVE_rot3 field.
1512         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1513         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1514
1515 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1516
1517         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1518         instructions.
1519
1520 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1521
1522         * aarch64-tbl.h
1523         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1524         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1525         aarch64_feature_sve2bitperm): New feature sets.
1526         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1527         for feature set addresses.
1528         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1529         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1530
1531 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1532             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1533
1534         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1535         argument and set ASE_EVA_R6 appropriately.
1536         (set_default_mips_dis_options): Pass ISA to above.
1537         (parse_mips_dis_option): Likewise.
1538         * mips-opc.c (EVAR6): New macro.
1539         (mips_builtin_opcodes): Add llwpe, scwpe.
1540
1541 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1542
1543         * aarch64-asm-2.c: Regenerated.
1544         * aarch64-dis-2.c: Regenerated.
1545         * aarch64-opc-2.c: Regenerated.
1546         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1547         AARCH64_OPND_TME_UIMM16.
1548         (aarch64_print_operand): Likewise.
1549         * aarch64-tbl.h (QL_IMM_NIL): New.
1550         (TME): New.
1551         (_TME_INSN): New.
1552         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1553
1554 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1555
1556         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1557
1558 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1559             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1560
1561         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1562
1563 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1564
1565         * s12z-opc.h: Add extern "C" bracketing to help
1566         users who wish to use this interface in c++ code.
1567
1568 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1569
1570         * s12z-opc.c (bm_decode): Handle bit map operations with the
1571         "reserved0" mode.
1572
1573 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1574
1575         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1576         specifier.  Add entries for VLDR and VSTR of system registers.
1577         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1578         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1579         of %J and %K format specifier.
1580
1581 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1582
1583         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1584         Add new entries for VSCCLRM instruction.
1585         (print_insn_coprocessor): Handle new %C format control code.
1586
1587 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1588
1589         * arm-dis.c (enum isa): New enum.
1590         (struct sopcode32): New structure.
1591         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1592         set isa field of all current entries to ANY.
1593         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1594         Only match an entry if its isa field allows the current mode.
1595
1596 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1597
1598         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1599         CLRM.
1600         (print_insn_thumb32): Add logic to print %n CLRM register list.
1601
1602 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1603
1604         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1605         and %Q patterns.
1606
1607 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1608
1609         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1610         (print_insn_thumb32): Edit the switch case for %Z.
1611
1612 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1613
1614         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1615
1616 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1617
1618         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1619
1620 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1621
1622         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1623
1624 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1625
1626         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1627         Arm register with r13 and r15 unpredictable.
1628         (thumb32_opcodes): New instructions for bfx and bflx.
1629
1630 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1631
1632         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1633
1634 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1635
1636         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1637
1638 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1639
1640         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1641
1642 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1643
1644         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1645
1646 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1647
1648         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1649         "optr". ("operator" is a reserved word in c++).
1650
1651 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1652
1653         * aarch64-opc.c (aarch64_print_operand): Add case for
1654         AARCH64_OPND_Rt_SP.
1655         (verify_constraints): Likewise.
1656         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1657         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1658         to accept Rt|SP as first operand.
1659         (AARCH64_OPERANDS): Add new Rt_SP.
1660         * aarch64-asm-2.c: Regenerated.
1661         * aarch64-dis-2.c: Regenerated.
1662         * aarch64-opc-2.c: Regenerated.
1663
1664 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1665
1666         * aarch64-asm-2.c: Regenerated.
1667         * aarch64-dis-2.c: Likewise.
1668         * aarch64-opc-2.c: Likewise.
1669         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1670
1671 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1672
1673         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1674
1675 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1676
1677         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1678         * i386-init.h: Regenerated.
1679
1680 2019-04-07  Alan Modra  <amodra@gmail.com>
1681
1682         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1683         op_separator to control printing of spaces, comma and parens
1684         rather than need_comma, need_paren and spaces vars.
1685
1686 2019-04-07  Alan Modra  <amodra@gmail.com>
1687
1688         PR 24421
1689         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1690         (print_insn_neon, print_insn_arm): Likewise.
1691
1692 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1693
1694         * i386-dis-evex.h (evex_table): Updated to support BF16
1695         instructions.
1696         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1697         and EVEX_W_0F3872_P_3.
1698         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1699         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1700         * i386-opc.h (enum): Add CpuAVX512_BF16.
1701         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1702         * i386-opc.tbl: Add AVX512 BF16 instructions.
1703         * i386-init.h: Regenerated.
1704         * i386-tbl.h: Likewise.
1705
1706 2019-04-05  Alan Modra  <amodra@gmail.com>
1707
1708         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1709         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1710         to favour printing of "-" branch hint when using the "y" bit.
1711         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1712
1713 2019-04-05  Alan Modra  <amodra@gmail.com>
1714
1715         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1716         opcode until first operand is output.
1717
1718 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1719
1720         PR gas/24349
1721         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1722         (valid_bo_post_v2): Add support for 'at' branch hints.
1723         (insert_bo): Only error on branch on ctr.
1724         (get_bo_hint_mask): New function.
1725         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1726         for inserting 'at' branch hints.
1727         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1728         for extracting 'at' branch hints.
1729         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1730         (BOE): Delete operand.
1731         (BOM, BOP): New operands.
1732         (RM): Update value.
1733         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1734         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1735         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1736         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1737         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1738         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1739         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1740         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1741         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1742         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1743         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1744         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1745         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1746         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1747         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1748         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1749         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1750         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1751         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1752         bttarl+>: New extended mnemonics.
1753
1754 2019-03-28  Alan Modra  <amodra@gmail.com>
1755
1756         PR 24390
1757         * ppc-opc.c (BTF): Define.
1758         (powerpc_opcodes): Use for mtfsb*.
1759         * ppc-dis.c (print_insn_powerpc): Print fields with both
1760         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1761
1762 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1763
1764         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1765         (mapping_symbol_for_insn): Implement new algorithm.
1766         (print_insn): Remove duplicate code.
1767
1768 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1769
1770         * aarch64-dis.c (print_insn_aarch64):
1771         Implement override.
1772
1773 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1774
1775         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1776         order.
1777
1778 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1779
1780         * aarch64-dis.c (last_stop_offset): New.
1781         (print_insn_aarch64): Use stop_offset.
1782
1783 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1784
1785         PR gas/24359
1786         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1787         CPU_ANY_AVX2_FLAGS.
1788         * i386-init.h: Regenerated.
1789
1790 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1791
1792         PR gas/24348
1793         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1794         vmovdqu16, vmovdqu32 and vmovdqu64.
1795         * i386-tbl.h: Regenerated.
1796
1797 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1798
1799         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1800         from vstrszb, vstrszh, and vstrszf.
1801
1802 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1803
1804         * s390-opc.txt: Add instruction descriptions.
1805
1806 2019-02-08  Jim Wilson  <jimw@sifive.com>
1807
1808         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1809         <bne>: Likewise.
1810
1811 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1812
1813         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1814
1815 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1816
1817         PR binutils/23212
1818         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1819         * aarch64-opc.c (verify_elem_sd): New.
1820         (fields): Add FLD_sz entr.
1821         * aarch64-tbl.h (_SIMD_INSN): New.
1822         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1823         fmulx scalar and vector by element isns.
1824
1825 2019-02-07  Nick Clifton  <nickc@redhat.com>
1826
1827         * po/sv.po: Updated Swedish translation.
1828
1829 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1830
1831         * s390-mkopc.c (main): Accept arch13 as cpu string.
1832         * s390-opc.c: Add new instruction formats and instruction opcode
1833         masks.
1834         * s390-opc.txt: Add new arch13 instructions.
1835
1836 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1837
1838         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1839         (aarch64_opcode): Change encoding for stg, stzg
1840         st2g and st2zg.
1841         * aarch64-asm-2.c: Regenerated.
1842         * aarch64-dis-2.c: Regenerated.
1843         * aarch64-opc-2.c: Regenerated.
1844
1845 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1846
1847         * aarch64-asm-2.c: Regenerated.
1848         * aarch64-dis-2.c: Likewise.
1849         * aarch64-opc-2.c: Likewise.
1850         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1851
1852 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1853             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1854
1855         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1856         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1857         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1858         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1859         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1860         case for ldstgv_indexed.
1861         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1862         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1863         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1864         * aarch64-asm-2.c: Regenerated.
1865         * aarch64-dis-2.c: Regenerated.
1866         * aarch64-opc-2.c: Regenerated.
1867
1868 2019-01-23  Nick Clifton  <nickc@redhat.com>
1869
1870         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1871
1872 2019-01-21  Nick Clifton  <nickc@redhat.com>
1873
1874         * po/de.po: Updated German translation.
1875         * po/uk.po: Updated Ukranian translation.
1876
1877 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1878         * mips-dis.c (mips_arch_choices): Fix typo in
1879         gs464, gs464e and gs264e descriptors.
1880
1881 2019-01-19  Nick Clifton  <nickc@redhat.com>
1882
1883         * configure: Regenerate.
1884         * po/opcodes.pot: Regenerate.
1885
1886 2018-06-24  Nick Clifton  <nickc@redhat.com>
1887
1888         2.32 branch created.
1889
1890 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1891
1892         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1893         if it is null.
1894         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1895         zero.
1896
1897 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1898
1899         * configure: Regenerate.
1900
1901 2019-01-07  Alan Modra  <amodra@gmail.com>
1902
1903         * configure: Regenerate.
1904         * po/POTFILES.in: Regenerate.
1905
1906 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1907
1908         * s12z-opc.c: New file.
1909         * s12z-opc.h: New file.
1910         * s12z-dis.c: Removed all code not directly related to display
1911         of instructions.  Used the interface provided by the new files
1912         instead.
1913         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1914         * Makefile.in: Regenerate.
1915         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1916         * configure: Regenerate.
1917
1918 2019-01-01  Alan Modra  <amodra@gmail.com>
1919
1920         Update year range in copyright notice of all files.
1921
1922 For older changes see ChangeLog-2018
1923 \f
1924 Copyright (C) 2019 Free Software Foundation, Inc.
1925
1926 Copying and distribution of this file, with or without modification,
1927 are permitted in any medium without royalty provided the copyright
1928 notice and this notice are preserved.
1929
1930 Local Variables:
1931 mode: change-log
1932 left-margin: 8
1933 fill-column: 74
1934 version-control: never
1935 End: