1 2020-05-11 Alan Modra <amodra@gmail.com>
3 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
5 2020-05-11 Alan Modra <amodra@gmail.com>
7 * ppc-dis.c (ppc_opts): Add "power10" entry.
8 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
9 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
11 2020-05-11 Nick Clifton <nickc@redhat.com>
13 * po/fr.po: Updated French translation.
15 2020-04-30 Alex Coplan <alex.coplan@arm.com>
17 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
18 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
19 (operand_general_constraint_met_p): validate
20 AARCH64_OPND_UNDEFINED.
21 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
23 * aarch64-asm-2.c: Regenerated.
24 * aarch64-dis-2.c: Regenerated.
25 * aarch64-opc-2.c: Regenerated.
27 2020-04-29 Nick Clifton <nickc@redhat.com>
30 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
33 2020-04-29 Nick Clifton <nickc@redhat.com>
35 * po/sv.po: Updated Swedish translation.
37 2020-04-29 Nick Clifton <nickc@redhat.com>
40 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
41 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
42 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
45 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
48 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
49 cmpi only on m68020up and cpu32.
51 2020-04-20 Sudakshina Das <sudi.das@arm.com>
53 * aarch64-asm.c (aarch64_ins_none): New.
54 * aarch64-asm.h (ins_none): New declaration.
55 * aarch64-dis.c (aarch64_ext_none): New.
56 * aarch64-dis.h (ext_none): New declaration.
57 * aarch64-opc.c (aarch64_print_operand): Update case for
58 AARCH64_OPND_BARRIER_PSB.
59 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
60 (AARCH64_OPERANDS): Update inserter/extracter for
61 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
62 * aarch64-asm-2.c: Regenerated.
63 * aarch64-dis-2.c: Regenerated.
64 * aarch64-opc-2.c: Regenerated.
66 2020-04-20 Sudakshina Das <sudi.das@arm.com>
68 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
69 (aarch64_feature_ras, RAS): Likewise.
70 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
71 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
72 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
73 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
74 * aarch64-asm-2.c: Regenerated.
75 * aarch64-dis-2.c: Regenerated.
76 * aarch64-opc-2.c: Regenerated.
78 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
80 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
81 (print_insn_neon): Support disassembly of conditional
84 2020-02-16 David Faust <david.faust@oracle.com>
86 * bpf-desc.c: Regenerate.
87 * bpf-desc.h: Likewise.
88 * bpf-opc.c: Regenerate.
89 * bpf-opc.h: Likewise.
91 2020-04-07 Lili Cui <lili.cui@intel.com>
93 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
94 (prefix_table): New instructions (see prefixes above).
96 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
97 CPU_ANY_TSXLDTRK_FLAGS.
98 (cpu_flags): Add CpuTSXLDTRK.
99 * i386-opc.h (enum): Add CpuTSXLDTRK.
100 (i386_cpu_flags): Add cputsxldtrk.
101 * i386-opc.tbl: Add XSUSPLDTRK insns.
102 * i386-init.h: Regenerate.
103 * i386-tbl.h: Likewise.
105 2020-04-02 Lili Cui <lili.cui@intel.com>
107 * i386-dis.c (prefix_table): New instructions serialize.
108 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
109 CPU_ANY_SERIALIZE_FLAGS.
110 (cpu_flags): Add CpuSERIALIZE.
111 * i386-opc.h (enum): Add CpuSERIALIZE.
112 (i386_cpu_flags): Add cpuserialize.
113 * i386-opc.tbl: Add SERIALIZE insns.
114 * i386-init.h: Regenerate.
115 * i386-tbl.h: Likewise.
117 2020-03-26 Alan Modra <amodra@gmail.com>
119 * disassemble.h (opcodes_assert): Declare.
120 (OPCODES_ASSERT): Define.
121 * disassemble.c: Don't include assert.h. Include opintl.h.
122 (opcodes_assert): New function.
123 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
124 (bfd_h8_disassemble): Reduce size of data array. Correctly
125 calculate maxlen. Omit insn decoding when insn length exceeds
126 maxlen. Exit from nibble loop when looking for E, before
127 accessing next data byte. Move processing of E outside loop.
128 Replace tests of maxlen in loop with assertions.
130 2020-03-26 Alan Modra <amodra@gmail.com>
132 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
134 2020-03-25 Alan Modra <amodra@gmail.com>
136 * z80-dis.c (suffix): Init mybuf.
138 2020-03-22 Alan Modra <amodra@gmail.com>
140 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
141 successflly read from section.
143 2020-03-22 Alan Modra <amodra@gmail.com>
145 * arc-dis.c (find_format): Use ISO C string concatenation rather
146 than line continuation within a string. Don't access needs_limm
147 before testing opcode != NULL.
149 2020-03-22 Alan Modra <amodra@gmail.com>
151 * ns32k-dis.c (print_insn_arg): Update comment.
152 (print_insn_ns32k): Reduce size of index_offset array, and
153 initialize, passing -1 to print_insn_arg for args that are not
154 an index. Don't exit arg loop early. Abort on bad arg number.
156 2020-03-22 Alan Modra <amodra@gmail.com>
158 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
159 * s12z-opc.c: Formatting.
160 (operands_f): Return an int.
161 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
162 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
163 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
164 (exg_sex_discrim): Likewise.
165 (create_immediate_operand, create_bitfield_operand),
166 (create_register_operand_with_size, create_register_all_operand),
167 (create_register_all16_operand, create_simple_memory_operand),
168 (create_memory_operand, create_memory_auto_operand): Don't
169 segfault on malloc failure.
170 (z_ext24_decode): Return an int status, negative on fail, zero
172 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
173 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
174 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
175 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
176 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
177 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
178 (loop_primitive_decode, shift_decode, psh_pul_decode),
179 (bit_field_decode): Similarly.
180 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
181 to return value, update callers.
182 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
183 Don't segfault on NULL operand.
184 (decode_operation): Return OP_INVALID on first fail.
185 (decode_s12z): Check all reads, returning -1 on fail.
187 2020-03-20 Alan Modra <amodra@gmail.com>
189 * metag-dis.c (print_insn_metag): Don't ignore status from
192 2020-03-20 Alan Modra <amodra@gmail.com>
194 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
195 Initialize parts of buffer not written when handling a possible
196 2-byte insn at end of section. Don't attempt decoding of such
197 an insn by the 4-byte machinery.
199 2020-03-20 Alan Modra <amodra@gmail.com>
201 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
202 partially filled buffer. Prevent lookup of 4-byte insns when
203 only VLE 2-byte insns are possible due to section size. Print
204 ".word" rather than ".long" for 2-byte leftovers.
206 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
209 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
211 2020-03-13 Jan Beulich <jbeulich@suse.com>
213 * i386-dis.c (X86_64_0D): Rename to ...
214 (X86_64_0E): ... this.
216 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
218 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
219 * Makefile.in: Regenerated.
221 2020-03-09 Jan Beulich <jbeulich@suse.com>
223 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
225 * i386-tbl.h: Re-generate.
227 2020-03-09 Jan Beulich <jbeulich@suse.com>
229 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
230 vprot*, vpsha*, and vpshl*.
231 * i386-tbl.h: Re-generate.
233 2020-03-09 Jan Beulich <jbeulich@suse.com>
235 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
236 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
237 * i386-tbl.h: Re-generate.
239 2020-03-09 Jan Beulich <jbeulich@suse.com>
241 * i386-gen.c (set_bitfield): Ignore zero-length field names.
242 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
243 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
244 * i386-tbl.h: Re-generate.
246 2020-03-09 Jan Beulich <jbeulich@suse.com>
248 * i386-gen.c (struct template_arg, struct template_instance,
249 struct template_param, struct template, templates,
250 parse_template, expand_templates): New.
251 (process_i386_opcodes): Various local variables moved to
252 expand_templates. Call parse_template and expand_templates.
253 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
254 * i386-tbl.h: Re-generate.
256 2020-03-06 Jan Beulich <jbeulich@suse.com>
258 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
259 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
260 register and memory source templates. Replace VexW= by VexW*
262 * i386-tbl.h: Re-generate.
264 2020-03-06 Jan Beulich <jbeulich@suse.com>
266 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
267 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
268 * i386-tbl.h: Re-generate.
270 2020-03-06 Jan Beulich <jbeulich@suse.com>
272 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
273 * i386-tbl.h: Re-generate.
275 2020-03-06 Jan Beulich <jbeulich@suse.com>
277 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
278 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
279 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
280 VexW0 on SSE2AVX variants.
281 (vmovq): Drop NoRex64 from XMM/XMM variants.
282 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
283 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
284 applicable use VexW0.
285 * i386-tbl.h: Re-generate.
287 2020-03-06 Jan Beulich <jbeulich@suse.com>
289 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
290 * i386-opc.h (Rex64): Delete.
291 (struct i386_opcode_modifier): Remove rex64 field.
292 * i386-opc.tbl (crc32): Drop Rex64.
293 Replace Rex64 with Size64 everywhere else.
294 * i386-tbl.h: Re-generate.
296 2020-03-06 Jan Beulich <jbeulich@suse.com>
298 * i386-dis.c (OP_E_memory): Exclude recording of used address
299 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
300 addressed memory operands for MPX insns.
302 2020-03-06 Jan Beulich <jbeulich@suse.com>
304 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
305 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
306 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
307 (ptwrite): Split into non-64-bit and 64-bit forms.
308 * i386-tbl.h: Re-generate.
310 2020-03-06 Jan Beulich <jbeulich@suse.com>
312 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
314 * i386-tbl.h: Re-generate.
316 2020-03-04 Jan Beulich <jbeulich@suse.com>
318 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
319 (prefix_table): Move vmmcall here. Add vmgexit.
320 (rm_table): Replace vmmcall entry by prefix_table[] escape.
321 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
322 (cpu_flags): Add CpuSEV_ES entry.
323 * i386-opc.h (CpuSEV_ES): New.
324 (union i386_cpu_flags): Add cpusev_es field.
325 * i386-opc.tbl (vmgexit): New.
326 * i386-init.h, i386-tbl.h: Re-generate.
328 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
330 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
332 * i386-opc.h (IGNORESIZE): New.
333 (DEFAULTSIZE): Likewise.
334 (IgnoreSize): Removed.
335 (DefaultSize): Likewise.
337 (i386_opcode_modifier): Replace ignoresize/defaultsize with
339 * i386-opc.tbl (IgnoreSize): New.
340 (DefaultSize): Likewise.
341 * i386-tbl.h: Regenerated.
343 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
346 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
349 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
352 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
353 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
354 * i386-tbl.h: Regenerated.
356 2020-02-26 Alan Modra <amodra@gmail.com>
358 * aarch64-asm.c: Indent labels correctly.
359 * aarch64-dis.c: Likewise.
360 * aarch64-gen.c: Likewise.
361 * aarch64-opc.c: Likewise.
362 * alpha-dis.c: Likewise.
363 * i386-dis.c: Likewise.
364 * nds32-asm.c: Likewise.
365 * nfp-dis.c: Likewise.
366 * visium-dis.c: Likewise.
368 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
370 * arc-regs.h (int_vector_base): Make it available for all ARC
373 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
375 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
378 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
380 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
381 c.mv/c.li if rs1 is zero.
383 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
385 * i386-gen.c (cpu_flag_init): Replace CpuABM with
386 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
388 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
389 * i386-opc.h (CpuABM): Removed.
391 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
392 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
393 popcnt. Remove CpuABM from lzcnt.
394 * i386-init.h: Regenerated.
395 * i386-tbl.h: Likewise.
397 2020-02-17 Jan Beulich <jbeulich@suse.com>
399 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
400 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
401 VexW1 instead of open-coding them.
402 * i386-tbl.h: Re-generate.
404 2020-02-17 Jan Beulich <jbeulich@suse.com>
406 * i386-opc.tbl (AddrPrefixOpReg): Define.
407 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
408 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
409 templates. Drop NoRex64.
410 * i386-tbl.h: Re-generate.
412 2020-02-17 Jan Beulich <jbeulich@suse.com>
415 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
416 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
417 into Intel syntax instance (with Unpsecified) and AT&T one
419 (vcvtneps2bf16): Likewise, along with folding the two so far
421 * i386-tbl.h: Re-generate.
423 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
425 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
428 2020-02-17 Alan Modra <amodra@gmail.com>
430 * i386-gen.c (cpu_flag_init): Correct last change.
432 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
434 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
437 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
439 * i386-opc.tbl (movsx): Remove Intel syntax comments.
442 2020-02-14 Jan Beulich <jbeulich@suse.com>
445 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
446 destination for Cpu64-only variant.
447 (movzx): Fold patterns.
448 * i386-tbl.h: Re-generate.
450 2020-02-13 Jan Beulich <jbeulich@suse.com>
452 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
453 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
454 CPU_ANY_SSE4_FLAGS entry.
455 * i386-init.h: Re-generate.
457 2020-02-12 Jan Beulich <jbeulich@suse.com>
459 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
460 with Unspecified, making the present one AT&T syntax only.
461 * i386-tbl.h: Re-generate.
463 2020-02-12 Jan Beulich <jbeulich@suse.com>
465 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
466 * i386-tbl.h: Re-generate.
468 2020-02-12 Jan Beulich <jbeulich@suse.com>
471 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
472 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
473 Amd64 and Intel64 templates.
474 (call, jmp): Likewise for far indirect variants. Dro
476 * i386-tbl.h: Re-generate.
478 2020-02-11 Jan Beulich <jbeulich@suse.com>
480 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
481 * i386-opc.h (ShortForm): Delete.
482 (struct i386_opcode_modifier): Remove shortform field.
483 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
484 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
485 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
486 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
488 * i386-tbl.h: Re-generate.
490 2020-02-11 Jan Beulich <jbeulich@suse.com>
492 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
493 fucompi): Drop ShortForm from operand-less templates.
494 * i386-tbl.h: Re-generate.
496 2020-02-11 Alan Modra <amodra@gmail.com>
498 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
499 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
500 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
501 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
502 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
504 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
506 * arm-dis.c (print_insn_cde): Define 'V' parse character.
507 (cde_opcodes): Add VCX* instructions.
509 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
510 Matthew Malcomson <matthew.malcomson@arm.com>
512 * arm-dis.c (struct cdeopcode32): New.
513 (CDE_OPCODE): New macro.
514 (cde_opcodes): New disassembly table.
515 (regnames): New option to table.
516 (cde_coprocs): New global variable.
517 (print_insn_cde): New
518 (print_insn_thumb32): Use print_insn_cde.
519 (parse_arm_disassembler_options): Parse coprocN args.
521 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
524 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
526 * i386-opc.h (AMD64): Removed.
530 (INTEL64ONLY): Likewise.
531 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
532 * i386-opc.tbl (Amd64): New.
534 (Intel64Only): Likewise.
535 Replace AMD64 with Amd64. Update sysenter/sysenter with
536 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
537 * i386-tbl.h: Regenerated.
539 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
542 * z80-dis.c: Add support for GBZ80 opcodes.
544 2020-02-04 Alan Modra <amodra@gmail.com>
546 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
548 2020-02-03 Alan Modra <amodra@gmail.com>
550 * m32c-ibld.c: Regenerate.
552 2020-02-01 Alan Modra <amodra@gmail.com>
554 * frv-ibld.c: Regenerate.
556 2020-01-31 Jan Beulich <jbeulich@suse.com>
558 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
559 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
560 (OP_E_memory): Replace xmm_mdq_mode case label by
561 vex_scalar_w_dq_mode one.
562 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
564 2020-01-31 Jan Beulich <jbeulich@suse.com>
566 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
567 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
568 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
569 (intel_operand_size): Drop vex_w_dq_mode case label.
571 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
573 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
574 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
576 2020-01-30 Alan Modra <amodra@gmail.com>
578 * m32c-ibld.c: Regenerate.
580 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
582 * bpf-opc.c: Regenerate.
584 2020-01-30 Jan Beulich <jbeulich@suse.com>
586 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
587 (dis386): Use them to replace C2/C3 table entries.
588 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
589 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
590 ones. Use Size64 instead of DefaultSize on Intel64 ones.
591 * i386-tbl.h: Re-generate.
593 2020-01-30 Jan Beulich <jbeulich@suse.com>
595 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
597 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
599 * i386-tbl.h: Re-generate.
601 2020-01-30 Alan Modra <amodra@gmail.com>
603 * tic4x-dis.c (tic4x_dp): Make unsigned.
605 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
606 Jan Beulich <jbeulich@suse.com>
609 * i386-dis.c (MOVSXD_Fixup): New function.
610 (movsxd_mode): New enum.
611 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
612 (intel_operand_size): Handle movsxd_mode.
613 (OP_E_register): Likewise.
615 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
616 register on movsxd. Add movsxd with 16-bit destination register
617 for AMD64 and Intel64 ISAs.
618 * i386-tbl.h: Regenerated.
620 2020-01-27 Tamar Christina <tamar.christina@arm.com>
623 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
624 * aarch64-asm-2.c: Regenerate
625 * aarch64-dis-2.c: Likewise.
626 * aarch64-opc-2.c: Likewise.
628 2020-01-21 Jan Beulich <jbeulich@suse.com>
630 * i386-opc.tbl (sysret): Drop DefaultSize.
631 * i386-tbl.h: Re-generate.
633 2020-01-21 Jan Beulich <jbeulich@suse.com>
635 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
637 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
638 * i386-tbl.h: Re-generate.
640 2020-01-20 Nick Clifton <nickc@redhat.com>
642 * po/de.po: Updated German translation.
643 * po/pt_BR.po: Updated Brazilian Portuguese translation.
644 * po/uk.po: Updated Ukranian translation.
646 2020-01-20 Alan Modra <amodra@gmail.com>
648 * hppa-dis.c (fput_const): Remove useless cast.
650 2020-01-20 Alan Modra <amodra@gmail.com>
652 * arm-dis.c (print_insn_arm): Wrap 'T' value.
654 2020-01-18 Nick Clifton <nickc@redhat.com>
656 * configure: Regenerate.
657 * po/opcodes.pot: Regenerate.
659 2020-01-18 Nick Clifton <nickc@redhat.com>
661 Binutils 2.34 branch created.
663 2020-01-17 Christian Biesinger <cbiesinger@google.com>
665 * opintl.h: Fix spelling error (seperate).
667 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
669 * i386-opc.tbl: Add {vex} pseudo prefix.
670 * i386-tbl.h: Regenerated.
672 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
675 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
676 (neon_opcodes): Likewise.
677 (select_arm_features): Make sure we enable MVE bits when selecting
678 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
681 2020-01-16 Jan Beulich <jbeulich@suse.com>
683 * i386-opc.tbl: Drop stale comment from XOP section.
685 2020-01-16 Jan Beulich <jbeulich@suse.com>
687 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
688 (extractps): Add VexWIG to SSE2AVX forms.
689 * i386-tbl.h: Re-generate.
691 2020-01-16 Jan Beulich <jbeulich@suse.com>
693 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
694 Size64 from and use VexW1 on SSE2AVX forms.
695 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
696 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
697 * i386-tbl.h: Re-generate.
699 2020-01-15 Alan Modra <amodra@gmail.com>
701 * tic4x-dis.c (tic4x_version): Make unsigned long.
702 (optab, optab_special, registernames): New file scope vars.
703 (tic4x_print_register): Set up registernames rather than
704 malloc'd registertable.
705 (tic4x_disassemble): Delete optable and optable_special. Use
706 optab and optab_special instead. Throw away old optab,
707 optab_special and registernames when info->mach changes.
709 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
712 * z80-dis.c (suffix): Use .db instruction to generate double
715 2020-01-14 Alan Modra <amodra@gmail.com>
717 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
718 values to unsigned before shifting.
720 2020-01-13 Thomas Troeger <tstroege@gmx.de>
722 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
724 (print_insn_thumb16, print_insn_thumb32): Likewise.
725 (print_insn): Initialize the insn info.
726 * i386-dis.c (print_insn): Initialize the insn info fields, and
729 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
731 * arc-opc.c (C_NE): Make it required.
733 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
735 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
736 reserved register name.
738 2020-01-13 Alan Modra <amodra@gmail.com>
740 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
741 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
743 2020-01-13 Alan Modra <amodra@gmail.com>
745 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
746 result of wasm_read_leb128 in a uint64_t and check that bits
747 are not lost when copying to other locals. Use uint32_t for
748 most locals. Use PRId64 when printing int64_t.
750 2020-01-13 Alan Modra <amodra@gmail.com>
752 * score-dis.c: Formatting.
753 * score7-dis.c: Formatting.
755 2020-01-13 Alan Modra <amodra@gmail.com>
757 * score-dis.c (print_insn_score48): Use unsigned variables for
758 unsigned values. Don't left shift negative values.
759 (print_insn_score32): Likewise.
760 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
762 2020-01-13 Alan Modra <amodra@gmail.com>
764 * tic4x-dis.c (tic4x_print_register): Remove dead code.
766 2020-01-13 Alan Modra <amodra@gmail.com>
768 * fr30-ibld.c: Regenerate.
770 2020-01-13 Alan Modra <amodra@gmail.com>
772 * xgate-dis.c (print_insn): Don't left shift signed value.
773 (ripBits): Formatting, use 1u.
775 2020-01-10 Alan Modra <amodra@gmail.com>
777 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
778 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
780 2020-01-10 Alan Modra <amodra@gmail.com>
782 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
783 and XRREG value earlier to avoid a shift with negative exponent.
784 * m10200-dis.c (disassemble): Similarly.
786 2020-01-09 Nick Clifton <nickc@redhat.com>
789 * z80-dis.c (ld_ii_ii): Use correct cast.
791 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
794 * z80-dis.c (ld_ii_ii): Use character constant when checking
797 2020-01-09 Jan Beulich <jbeulich@suse.com>
799 * i386-dis.c (SEP_Fixup): New.
801 (dis386_twobyte): Use it for sysenter/sysexit.
802 (enum x86_64_isa): Change amd64 enumerator to value 1.
803 (OP_J): Compare isa64 against intel64 instead of amd64.
804 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
806 * i386-tbl.h: Re-generate.
808 2020-01-08 Alan Modra <amodra@gmail.com>
810 * z8k-dis.c: Include libiberty.h
811 (instr_data_s): Make max_fetched unsigned.
812 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
813 Don't exceed byte_info bounds.
814 (output_instr): Make num_bytes unsigned.
815 (unpack_instr): Likewise for nibl_count and loop.
816 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
818 * z8k-opc.h: Regenerate.
820 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
822 * arc-tbl.h (llock): Use 'LLOCK' as class.
824 (scond): Use 'SCOND' as class.
826 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
829 2020-01-06 Alan Modra <amodra@gmail.com>
831 * m32c-ibld.c: Regenerate.
833 2020-01-06 Alan Modra <amodra@gmail.com>
836 * z80-dis.c (suffix): Don't use a local struct buffer copy.
837 Peek at next byte to prevent recursion on repeated prefix bytes.
838 Ensure uninitialised "mybuf" is not accessed.
839 (print_insn_z80): Don't zero n_fetch and n_used here,..
840 (print_insn_z80_buf): ..do it here instead.
842 2020-01-04 Alan Modra <amodra@gmail.com>
844 * m32r-ibld.c: Regenerate.
846 2020-01-04 Alan Modra <amodra@gmail.com>
848 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
850 2020-01-04 Alan Modra <amodra@gmail.com>
852 * crx-dis.c (match_opcode): Avoid shift left of signed value.
854 2020-01-04 Alan Modra <amodra@gmail.com>
856 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
858 2020-01-03 Jan Beulich <jbeulich@suse.com>
860 * aarch64-tbl.h (aarch64_opcode_table): Use
861 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
863 2020-01-03 Jan Beulich <jbeulich@suse.com>
865 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
866 forms of SUDOT and USDOT.
868 2020-01-03 Jan Beulich <jbeulich@suse.com>
870 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
872 * opcodes/aarch64-dis-2.c: Re-generate.
874 2020-01-03 Jan Beulich <jbeulich@suse.com>
876 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
878 * opcodes/aarch64-dis-2.c: Re-generate.
880 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
882 * z80-dis.c: Add support for eZ80 and Z80 instructions.
884 2020-01-01 Alan Modra <amodra@gmail.com>
886 Update year range in copyright notice of all files.
888 For older changes see ChangeLog-2019
890 Copyright (C) 2020 Free Software Foundation, Inc.
892 Copying and distribution of this file, with or without modification,
893 are permitted in any medium without royalty provided the copyright
894 notice and this notice are preserved.
900 version-control: never