opcodes/ChangeLog

   1 2015-04-23  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
   4         * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
   5         vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
   6         (vfpclasspd, vfpclassps): Add %XZ.
   7
   8 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
   9
  10         * i386-dis.c (PREFIX_UD_SHIFT): Removed.
  11         (PREFIX_UD_REPZ): Likewise.
  12         (PREFIX_UD_REPNZ): Likewise.
  13         (PREFIX_UD_DATA): Likewise.
  14         (PREFIX_UD_ADDR): Likewise.
  15         (PREFIX_UD_LOCK): Likewise.
  16
  17 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
  18
  19         * i386-dis.c (prefix_requirement): Removed.
  20         (print_insn): Don't set prefix_requirement.  Check
  21         dp->prefix_requirement instead of prefix_requirement.
  22
  23 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
  24
  25         PR binutils/17898
  26         * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
  27         (PREFIX_MOD_0_0FC7_REG_6): This.
  28         (PREFIX_MOD_3_0FC7_REG_6): New.
  29         (PREFIX_MOD_3_0FC7_REG_7): Likewise.
  30         (prefix_table): Replace PREFIX_0FC7_REG_6 with
  31         PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
  32         PREFIX_MOD_3_0FC7_REG_7.
  33         (mod_table): Replace PREFIX_0FC7_REG_6 with
  34         PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
  35         PREFIX_MOD_3_0FC7_REG_7.
  36
  37 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
  38
  39         * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
  40         (PREFIX_MANDATORY_REPNZ): Likewise.
  41         (PREFIX_MANDATORY_DATA): Likewise.
  42         (PREFIX_MANDATORY_ADDR): Likewise.
  43         (PREFIX_MANDATORY_LOCK): Likewise.
  44         (PREFIX_MANDATORY): Likewise.
  45         (PREFIX_UD_SHIFT): Set to 8
  46         (PREFIX_UD_REPZ): Updated.
  47         (PREFIX_UD_REPNZ): Likewise.
  48         (PREFIX_UD_DATA): Likewise.
  49         (PREFIX_UD_ADDR): Likewise.
  50         (PREFIX_UD_LOCK): Likewise.
  51         (PREFIX_IGNORED_SHIFT): New.
  52         (PREFIX_IGNORED_REPZ): Likewise.
  53         (PREFIX_IGNORED_REPNZ): Likewise.
  54         (PREFIX_IGNORED_DATA): Likewise.
  55         (PREFIX_IGNORED_ADDR): Likewise.
  56         (PREFIX_IGNORED_LOCK): Likewise.
  57         (PREFIX_OPCODE): Likewise.
  58         (PREFIX_IGNORED): Likewise.
  59         (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
  60         (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
  61         (three_byte_table): Likewise.
  62         (mod_table): Likewise.
  63         (mandatory_prefix): Renamed to ...
  64         (prefix_requirement): This.
  65         (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
  66         Update PREFIX_90 entry.
  67         (get_valid_dis386): Check prefix_requirement to see if a prefix
  68         should be ignored.
  69         (print_insn): Replace mandatory_prefix with prefix_requirement.
  70
  71 2015-04-15  Renlin Li  <renlin.li@arm.com>
  72
  73         * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
  74         use it for ssat and ssat16.
  75         (print_insn_thumb32): Add handle case for 'D' control code.
  76
  77 2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
  78             H.J. Lu  <hongjiu.lu@intel.com>
  79
  80         * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
  81         * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
  82         PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
  83         PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
  84         PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
  85         (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
  86         Fill prefix_requirement field.
  87         (struct dis386): Add prefix_requirement field.
  88         (dis386): Fill prefix_requirement field.
  89         (dis386_twobyte): Ditto.
  90         (twobyte_has_mandatory_prefix_: Remove.
  91         (reg_table): Fill prefix_requirement field.
  92         (prefix_table): Ditto.
  93         (x86_64_table): Ditto.
  94         (three_byte_table): Ditto.
  95         (xop_table): Ditto.
  96         (vex_table): Ditto.
  97         (vex_len_table): Ditto.
  98         (vex_w_table): Ditto.
  99         (mod_table): Ditto.
 100         (bad_opcode): Ditto.
 101         (print_insn): Use prefix_requirement.
 102         (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
 103         FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
 104         (float_reg): Ditto.
 105
 106 2015-03-30  Mike Frysinger  <vapier@gentoo.org>
 107
 108         * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
 109
 110 2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 111
 112         * Makefile.in: Regenerated.
 113
 114 2015-03-25  Anton Blanchard  <anton@samba.org>
 115
 116         * ppc-dis.c (disassemble_init_powerpc): Only initialise
 117         powerpc_opcd_indices and vle_opcd_indices once.
 118
 119 2015-03-25  Anton Blanchard  <anton@samba.org>
 120
 121         * ppc-opc.c (powerpc_opcodes): Add slbfee.
 122
 123 2015-03-24  Terry Guo  <terry.guo@arm.com>
 124
 125         * arm-dis.c (opcode32): Updated to use new arm feature struct.
 126         (opcode16): Likewise.
 127         (coprocessor_opcodes): Replace bit with feature struct.
 128         (neon_opcodes): Likewise.
 129         (arm_opcodes): Likewise.
 130         (thumb_opcodes): Likewise.
 131         (thumb32_opcodes): Likewise.
 132         (print_insn_coprocessor): Likewise.
 133         (print_insn_arm): Likewise.
 134         (select_arm_features): Follow new feature struct.
 135
 136 2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
 137
 138         * i386-dis.c (rm_table): Add clzero.
 139         * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
 140         Add CPU_CLZERO_FLAGS.
 141         (cpu_flags): Add CpuCLZERO.
 142         * i386-opc.h: Add CpuCLZERO.
 143         * i386-opc.tbl: Add clzero.
 144         * i386-init.h: Re-generated.
 145         * i386-tbl.h: Re-generated.
 146
 147 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 148
 149         * mips-opc.c (decode_mips_operand): Fix constraint issues
 150         with u and y operands.
 151
 152 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 153
 154         * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
 155
 156 2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 157
 158         * s390-opc.c: Add new IBM z13 instructions.
 159         * s390-opc.txt: Likewise.
 160
 161 2015-03-10  Renlin Li  <renlin.li@arm.com>
 162
 163         * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
 164         stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
 165         related alias.
 166         * aarch64-asm-2.c: Regenerate.
 167         * aarch64-dis-2.c: Likewise.
 168         * aarch64-opc-2.c: Likewise.
 169
 170 2015-03-03  Jiong Wang  <jiong.wang@arm.com>
 171
 172         * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
 173
 174 2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>
 175
 176         * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
 177         arch_sh_up.
 178         (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
 179         arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
 180
 181 2015-02-23  Vinay  <Vinay.G@kpit.com>
 182
 183         * rl78-decode.opc (MOV): Added space between two operands for
 184         'mov' instruction in index addressing mode.
 185         * rl78-decode.c: Regenerate.
 186
 187 2015-02-19  Pedro Alves  <palves@redhat.com>
 188
 189         * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
 190
 191 2015-02-10  Pedro Alves  <palves@redhat.com>
 192             Tom Tromey  <tromey@redhat.com>
 193
 194         * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
 195         microblaze_and, microblaze_xor.
 196         * microblaze-opc.h (opcodes): Adjust.
 197
 198 2015-01-28  James Bowman  <james.bowman@ftdichip.com>
 199
 200         * Makefile.am: Add FT32 files.
 201         * configure.ac: Handle FT32.
 202         * disassemble.c (disassembler): Call print_insn_ft32.
 203         * ft32-dis.c: New file.
 204         * ft32-opc.c: New file.
 205         * Makefile.in: Regenerate.
 206         * configure: Regenerate.
 207         * po/POTFILES.in: Regenerate.
 208
 209 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
 210
 211         * nds32-asm.c (keyword_sr): Add new system registers.
 212
 213 2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 214
 215         * s390-dis.c (s390_extract_operand): Support vector register
 216         operands.
 217         (s390_print_insn_with_opcode): Support new operands types and add
 218         new handling of optional operands.
 219         * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
 220         and include opcode/s390.h instead.
 221         (struct op_struct): New field `flags'.
 222         (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
 223         (dumpTable): Dump flags.
 224         (main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
 225         string.
 226         * s390-opc.c: Add new operands types, instruction formats, and
 227         instruction masks.
 228         (s390_opformats): Add new formats for .insn.
 229         * s390-opc.txt: Add new instructions.
 230
 231 2015-01-01  Alan Modra  <amodra@gmail.com>
 232
 233         Update year range in copyright notice of all files.
 234
 235 For older changes see ChangeLog-2014
 236 \f
 237 Copyright (C) 2015 Free Software Foundation, Inc.
 238
 239 Copying and distribution of this file, with or without modification,
 240 are permitted in any medium without royalty provided the copyright
 241 notice and this notice are preserved.
 242
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 244 mode: change-log
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