opcodes/ChangeLog

   1 2019-12-11  Alan Modra  <amodra@gmail.com>
   2
   3         * arc-dis.c (BITS): Don't truncate high bits with shifts.
   4         * nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts.
   5         * tic54x-dis.c (print_instruction): Likewise.
   6         * tilegx-opc.c (parse_insn_tilegx): Likewise.
   7         * tilepro-opc.c (parse_insn_tilepro): Likewise.
   8         * visium-dis.c (disassem_class0): Likewise.
   9         * pdp11-dis.c (sign_extend): Likewise.
  10         (SIGN_BITS): Delete.
  11         * epiphany-ibld.c: Regenerate.
  12         * lm32-ibld.c: Regenerate.
  13         * m32c-ibld.c: Regenerate.
  14
  15 2019-12-11  Alan Modra  <amodra@gmail.com>
  16
  17         * ns32k-dis.c (sign_extend): Correct last patch.
  18
  19 2019-12-11  Alan Modra  <amodra@gmail.com>
  20
  21         * vax-dis.c (NEXTLONG): Avoid signed overflow.
  22
  23 2019-12-11  Alan Modra  <amodra@gmail.com>
  24
  25         * v850-dis.c (get_operand_value): Use unsigned arithmetic.  Don't
  26         sign extend using shifts.
  27
  28 2019-12-11  Alan Modra  <amodra@gmail.com>
  29
  30         * tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
  31
  32 2019-12-11  Alan Modra  <amodra@gmail.com>
  33
  34         * tic4x-dis.c (tic4x_print_register): Formatting.  Don't segfault
  35         on NULL registertable entry.
  36         (tic4x_hash_opcode): Use unsigned arithmetic.
  37
  38 2019-12-11  Alan Modra  <amodra@gmail.com>
  39
  40         * s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
  41
  42 2019-12-11  Alan Modra  <amodra@gmail.com>
  43
  44         * ns32k-dis.c (bit_extract): Use unsigned arithmetic.
  45         (bit_extract_simple, sign_extend): Likewise.
  46
  47 2019-12-11  Alan Modra  <amodra@gmail.com>
  48
  49         * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
  50
  51 2019-12-11  Alan Modra  <amodra@gmail.com>
  52
  53         * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
  54
  55 2019-12-11  Alan Modra  <amodra@gmail.com>
  56
  57         * m68k-dis.c (COERCE32): Cast value first.
  58         (NEXTLONG, NEXTULONG): Avoid signed overflow.
  59
  60 2019-12-11  Alan Modra  <amodra@gmail.com>
  61
  62         * h8300-dis.c (extract_immediate): Avoid signed overflow.
  63         (bfd_h8_disassemble): Likewise.
  64
  65 2019-12-11  Alan Modra  <amodra@gmail.com>
  66
  67         * d30v-dis.c (print_insn): Make opind unsigned.  Don't access
  68         past end of operands array.
  69
  70 2019-12-11  Alan Modra  <amodra@gmail.com>
  71
  72         * csky-dis.c (csky_chars_to_number): Rewrite.  Avoid signed
  73         overflow when collecting bytes of a number.
  74
  75 2019-12-11  Alan Modra  <amodra@gmail.com>
  76
  77         * cris-dis.c (print_with_operands): Avoid signed integer
  78         overflow when collecting bytes of a 32-bit integer.
  79
  80 2019-12-11  Alan Modra  <amodra@gmail.com>
  81
  82         * cr16-dis.c (EXTRACT, SBM): Rewrite.
  83         (cr16_match_opcode): Delete duplicate bcond test.
  84
  85 2019-12-11  Alan Modra  <amodra@gmail.com>
  86
  87         * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
  88         (SIGNBIT): New.
  89         (MASKBITS, SIGNEXTEND): Rewrite.
  90         (fmtconst): Don't use ? expression now that SIGNEXTEND uses
  91         unsigned arithmetic, instead assign result of SIGNEXTEND back
  92         to x.
  93         (fmtconst_val): Use 1u in shift expression.
  94
  95 2019-12-11  Alan Modra  <amodra@gmail.com>
  96
  97         * arc-dis.c (find_format_from_table): Use ull constant when
  98         shifting by up to 32.
  99
 100 2019-12-11  Alan Modra  <amodra@gmail.com>
 101
 102         PR 25270
 103         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
 104         false when field is zero for sve_size_tsz_bhs.
 105
 106 2019-12-11  Alan Modra  <amodra@gmail.com>
 107
 108         * epiphany-ibld.c: Regenerate.
 109
 110 2019-12-10  Alan Modra  <amodra@gmail.com>
 111
 112         PR 24960
 113         * disassemble.c (disassemble_free_target): New function.
 114
 115 2019-12-10  Alan Modra  <amodra@gmail.com>
 116
 117         * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
 118         * disassemble.c (disassemble_init_for_target): Likewise.
 119         * bpf-dis.c: Regenerate.
 120         * epiphany-dis.c: Regenerate.
 121         * fr30-dis.c: Regenerate.
 122         * frv-dis.c: Regenerate.
 123         * ip2k-dis.c: Regenerate.
 124         * iq2000-dis.c: Regenerate.
 125         * lm32-dis.c: Regenerate.
 126         * m32c-dis.c: Regenerate.
 127         * m32r-dis.c: Regenerate.
 128         * mep-dis.c: Regenerate.
 129         * mt-dis.c: Regenerate.
 130         * or1k-dis.c: Regenerate.
 131         * xc16x-dis.c: Regenerate.
 132         * xstormy16-dis.c: Regenerate.
 133
 134 2019-12-10  Alan Modra  <amodra@gmail.com>
 135
 136         * ppc-dis.c (private): Delete variable.
 137         (get_powerpc_dialect): Don't segfault on NULL info->private_data.
 138         (powerpc_init_dialect): Don't use global private.
 139
 140 2019-12-10  Alan Modra  <amodra@gmail.com>
 141
 142         * s12z-opc.c: Formatting.
 143
 144 2019-12-08  Alan Modra  <amodra@gmail.com>
 145
 146         * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
 147         registers.
 148
 149 2019-12-05  Jan Beulich  <jbeulich@suse.com>
 150
 151         * aarch64-tbl.h (aarch64_feature_crypto,
 152         aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
 153         CRYPTO_V8_2_INSN): Delete.
 154
 155 2019-12-05  Alan Modra  <amodra@gmail.com>
 156
 157         PR 25249
 158         * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
 159         (struct string_buf): New.
 160         (strbuf): New function.
 161         (get_field): Use strbuf rather than strdup of local temp.
 162         (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
 163         (get_field_rfsl, get_field_imm15): Likewise.
 164         (get_field_rd, get_field_r1, get_field_r2): Update macros.
 165         (get_field_special): Likewise.  Don't strcpy spr.  Formatting.
 166         (print_insn_microblaze): Formatting.  Init and pass string_buf to
 167         get_field functions.
 168
 169 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 170
 171         * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
 172         * i386-tbl.h: Re-generate.
 173
 174 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 175
 176         * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
 177
 178 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 179
 180         * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
 181         forms.
 182         (xbegin): Drop DefaultSize.
 183         * i386-tbl.h: Re-generate.
 184
 185 2019-11-22  Mihail Ionescu  <mihail.ionescu@arm.com>
 186
 187         * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
 188         Change the coproc CRC conditions to use the extension
 189         feature set, second word, base on ARM_EXT2_CRC.
 190
 191 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 192
 193         * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
 194         * i386-tbl.h: Re-generate.
 195
 196 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 197
 198         * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
 199         JumpInterSegment, and JumpAbsolute entries.
 200         * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
 201         JUMP_ABSOLUTE): Define.
 202         (struct i386_opcode_modifier): Extend jump field to 3 bits.
 203         Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
 204         fields.
 205         * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
 206         JumpInterSegment): Define.
 207         * i386-tbl.h: Re-generate.
 208
 209 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 210
 211         * i386-gen.c (operand_type_init): Remove
 212         OPERAND_TYPE_JUMPABSOLUTE entry.
 213         (opcode_modifiers): Add JumpAbsolute entry.
 214         (operand_types): Remove JumpAbsolute entry.
 215         * i386-opc.h (JumpAbsolute): Move between enums.
 216         (struct i386_opcode_modifier): Add jumpabsolute field.
 217         (union i386_operand_type): Remove jumpabsolute field.
 218         * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
 219         * i386-init.h, i386-tbl.h: Re-generate.
 220
 221 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 222
 223         * i386-gen.c (opcode_modifiers): Add AnySize entry.
 224         (operand_types): Remove AnySize entry.
 225         * i386-opc.h (AnySize): Move between enums.
 226         (struct i386_opcode_modifier): Add anysize field.
 227         (OTUnused): Un-comment.
 228         (union i386_operand_type): Remove anysize field.
 229         * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
 230         prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
 231         bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
 232         AnySize.
 233         * i386-tbl.h: Re-generate.
 234
 235 2019-11-12  Nelson Chu  <nelson.chu@sifive.com>
 236
 237         * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
 238         INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
 239         use the floating point register (FPR).
 240
 241 2019-11-12  Mihail Ionescu  <mihail.ionescu@arm.com>
 242
 243         * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
 244         cmode 1101.
 245         (is_mve_encoding_conflict): Update cmode conflict checks for
 246         MVE_VMVN_IMM.
 247
 248 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 249
 250         * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
 251         entry.
 252         (operand_types): Remove EsSeg entry.
 253         (main): Replace stale use of OTMax.
 254         * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
 255         (struct i386_opcode_modifier): Expand isstring field to 2 bits.
 256         (EsSeg): Delete.
 257         (OTUnused): Comment out.
 258         (union i386_operand_type): Remove esseg field.
 259         * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
 260         (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
 261         (ins, movs, smov, movsd): Add IsStringEsOpOp1.
 262         (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
 263         * i386-init.h, i386-tbl.h: Re-generate.
 264
 265 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 266
 267         * i386-gen.c (operand_instances): Add RegB entry.
 268         * i386-opc.h (enum operand_instance): Add RegB.
 269         * i386-opc.tbl (RegC, RegD, RegB): Define.
 270         (Acc, ShiftCount, InOutPortReg): Adjust definitions.
 271         (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
 272         monitorx, mwaitx): Drop ImmExt and convert encodings
 273         accordingly.
 274         * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
 275         (edx, rdx): Add Instance=RegD.
 276         (ebx, rbx): Add Instance=RegB.
 277         * i386-tbl.h: Re-generate.
 278
 279 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 280
 281         * i386-gen.c (operand_type_init): Adjust
 282         OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
 283         OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
 284         OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
 285         (operand_instances): New.
 286         (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
 287         (output_operand_type): New parameter "instance". Process it.
 288         (process_i386_operand_type): New local variable "instance".
 289         (main): Adjust static assertions.
 290         * i386-opc.h (INSTANCE_WIDTH): Define.
 291         (enum operand_instance): New.
 292         (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
 293         (union i386_operand_type): Replace acc, inoutportreg, and
 294         shiftcount by instance.
 295         * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
 296         * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
 297         Add Instance=.
 298         * i386-init.h, i386-tbl.h: Re-generate.
 299
 300 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 301
 302         * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
 303         smaxp/sminp entries' "tied_operand" field to 2.
 304
 305 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 306
 307         * aarch64-opc.c (operand_general_constraint_met_p): Replace
 308         "index" local variable by that of the already existing "num".
 309
 310 2019-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 311
 312         PR gas/25167
 313         * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
 314         * i386-tbl.h: Regenerated.
 315
 316 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 317
 318         * i386-gen.c (operand_type_init): Add Class= to
 319         OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
 320         OPERAND_TYPE_REGBND entry.
 321         (operand_classes): Add RegMask and RegBND entries.
 322         (operand_types): Drop RegMask and RegBND entry.
 323         * i386-opc.h (enum operand_class): Add RegMask and RegBND.
 324         (RegMask, RegBND): Delete.
 325         (union i386_operand_type): Remove regmask and regbnd fields.
 326         * i386-opc.tbl (RegMask, RegBND): Define.
 327         * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
 328         Class=RegBND.
 329         * i386-init.h, i386-tbl.h: Re-generate.
 330
 331 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 332
 333         * i386-gen.c (operand_type_init): Add Class= to
 334         OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
 335         OPERAND_TYPE_REGZMM entries.
 336         (operand_classes): Add RegMMX and RegSIMD entries.
 337         (operand_types): Drop RegMMX and RegSIMD entries.
 338         * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
 339         (RegMMX, RegSIMD): Delete.
 340         (union i386_operand_type): Remove regmmx and regsimd fields.
 341         * i386-opc.tbl (RegMMX): Define.
 342         (RegXMM, RegYMM, RegZMM): Add Class=.
 343         * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
 344         Class=RegSIMD.
 345         * i386-init.h, i386-tbl.h: Re-generate.
 346
 347 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 348
 349         * i386-gen.c (operand_type_init): Add Class= to
 350         OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
 351         entries.
 352         (operand_classes): Add RegCR, RegDR, and RegTR entries.
 353         (operand_types): Drop Control, Debug, and Test entries.
 354         * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
 355         (Control, Debug, Test): Delete.
 356         (union i386_operand_type): Remove control, debug, and test
 357         fields.
 358         * i386-opc.tbl (Control, Debug, Test): Define.
 359         * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
 360         Class=RegDR, and Test by Class=RegTR.
 361         * i386-init.h, i386-tbl.h: Re-generate.
 362
 363 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 364
 365         * i386-gen.c (operand_type_init): Add Class= to
 366         OPERAND_TYPE_SREG entry.
 367         (operand_classes): Add SReg entry.
 368         (operand_types): Drop SReg entry.
 369         * i386-opc.h (enum operand_class): Add SReg.
 370         (SReg): Delete.
 371         (union i386_operand_type): Remove sreg field.
 372         * i386-opc.tbl (SReg): Define.
 373         * i386-reg.tbl: Replace SReg by Class=SReg.
 374         * i386-init.h, i386-tbl.h: Re-generate.
 375
 376 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 377
 378         * i386-gen.c (operand_type_init): Add Class=. New
 379         OPERAND_TYPE_ANYIMM entry.
 380         (operand_classes): New.
 381         (operand_types): Drop Reg entry.
 382         (output_operand_type): New parameter "class". Process it.
 383         (process_i386_operand_type): New local variable "class".
 384         (main): Adjust static assertions.
 385         * i386-opc.h (CLASS_WIDTH): Define.
 386         (enum operand_class): New.
 387         (Reg): Replace by Class. Adjust comment.
 388         (union i386_operand_type): Replace reg by class.
 389         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
 390         Class=.
 391         * i386-reg.tbl: Replace Reg by Class=Reg.
 392         * i386-init.h: Re-generate.
 393
 394 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 395
 396         * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
 397         (aarch64_opcode_table): Add data gathering hint mnemonic.
 398         * opcodes/aarch64-dis-2.c: Account for new instruction.
 399
 400 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 401
 402         * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
 403
 404
 405 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 406
 407         * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
 408         aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
 409         aarch64_feature_f64mm): New feature sets.
 410         (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
 411         F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
 412         instructions.
 413         (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
 414         macros.
 415         (QL_MMLA64, OP_SVE_SBB): New qualifiers.
 416         (OP_SVE_QQQ): New qualifier.
 417         (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
 418         F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
 419         the movprfx constraint.
 420         (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
 421         (aarch64_opcode_table): Define new instructions smmla,
 422         ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
 423         uzip{1/2}, trn{1/2}.
 424         * aarch64-opc.c (operand_general_constraint_met_p): Handle
 425         AARCH64_OPND_SVE_ADDR_RI_S4x32.
 426         (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
 427         * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
 428         Account for new instructions.
 429         * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
 430         S4x32 operand.
 431         * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
 432
 433 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 434 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 435
 436         * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
 437         Armv8.6-A.
 438         (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
 439         (neon_opcodes): Add bfloat SIMD instructions.
 440         (print_insn_coprocessor): Add new control character %b to print
 441         condition code without checking cp_num.
 442         (print_insn_neon): Account for BFloat16 instructions that have no
 443         special top-byte handling.
 444
 445 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 446 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 447
 448         * arm-dis.c (print_insn_coprocessor,
 449         print_insn_generic_coprocessor): Create wrapper functions around
 450         the implementation of the print_insn_coprocessor control codes.
 451         (print_insn_coprocessor_1): Original print_insn_coprocessor
 452         function that now takes which array to look at as an argument.
 453         (print_insn_arm): Use both print_insn_coprocessor and
 454         print_insn_generic_coprocessor.
 455         (print_insn_thumb32): As above.
 456
 457 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 458 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 459
 460         * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
 461         in reglane special case.
 462         * aarch64-dis-2.c (aarch64_opcode_lookup_1,
 463         aarch64_find_next_opcode): Account for new instructions.
 464         * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
 465         in reglane special case.
 466         * aarch64-opc.c (struct operand_qualifier_data): Add data for
 467         new AARCH64_OPND_QLF_S_2H qualifier.
 468         * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
 469         QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
 470         (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
 471         sets.
 472         (BFLOAT_SVE, BFLOAT): New feature set macros.
 473         (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
 474         instructions.
 475         (aarch64_opcode_table): Define new instructions bfdot,
 476         bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
 477         bfcvtn2, bfcvt.
 478
 479 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 480 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 481
 482         * aarch64-tbl.h (ARMV8_6): New macro.
 483
 484 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 485
 486         * i386-dis.c (prefix_table): Add mcommit.
 487         (rm_table): Add rdpru.
 488         * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
 489         CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
 490         (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
 491         * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
 492         (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
 493         * i386-opc.tbl (mcommit, rdpru): New.
 494         * i386-init.h, i386-tbl.h: Re-generate.
 495
 496 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 497
 498         * i386-dis.c (OP_Mwait): Drop local variable "names", use
 499         "names32" instead.
 500         (OP_Monitor): Drop local variable "op1_names", re-purpose
 501         "names" for it instead, and replace former "names" uses by
 502         "names32" ones.
 503
 504 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 505
 506         PR/gas 25167
 507         * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
 508         operand-less forms.
 509         * opcodes/i386-tbl.h: Re-generate.
 510
 511 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 512
 513         * i386-dis.c (OP_Mwaitx): Delete.
 514         (prefix_table): Use OP_Mwait for mwaitx entry.
 515         (OP_Mwait): Also handle mwaitx.
 516
 517 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 518
 519         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
 520         PREFIX_0F01_REG_7_MOD_3_RM_3): New.
 521         (prefix_table): Add respective entries.
 522         (rm_table): Link to those entries.
 523
 524 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 525
 526         * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
 527         (REG_0F1C_P_0_MOD_0): ... this.
 528         (REG_0F1E_MOD_3): Rename to ...
 529         (REG_0F1E_P_1_MOD_3): ... this.
 530         (RM_0F01_REG_5): Rename to ...
 531         (RM_0F01_REG_5_MOD_3): ... this.
 532         (RM_0F01_REG_7): Rename to ...
 533         (RM_0F01_REG_7_MOD_3): ... this.
 534         (RM_0F1E_MOD_3_REG_7): Rename to ...
 535         (RM_0F1E_P_1_MOD_3_REG_7): ... this.
 536         (RM_0FAE_REG_6): Rename to ...
 537         (RM_0FAE_REG_6_MOD_3_P_0): ... this.
 538         (RM_0FAE_REG_7): Rename to ...
 539         (RM_0FAE_REG_7_MOD_3): ... this.
 540         (PREFIX_MOD_0_0F01_REG_5): Rename to ...
 541         (PREFIX_0F01_REG_5_MOD_0): ... this.
 542         (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
 543         (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
 544         (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
 545         (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
 546         (PREFIX_0FAE_REG_0): Rename to ...
 547         (PREFIX_0FAE_REG_0_MOD_3): ... this.
 548         (PREFIX_0FAE_REG_1): Rename to ...
 549         (PREFIX_0FAE_REG_1_MOD_3): ... this.
 550         (PREFIX_0FAE_REG_2): Rename to ...
 551         (PREFIX_0FAE_REG_2_MOD_3): ... this.
 552         (PREFIX_0FAE_REG_3): Rename to ...
 553         (PREFIX_0FAE_REG_3_MOD_3): ... this.
 554         (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
 555         (PREFIX_0FAE_REG_4_MOD_0): ... this.
 556         (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
 557         (PREFIX_0FAE_REG_4_MOD_3): ... this.
 558         (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
 559         (PREFIX_0FAE_REG_5_MOD_0): ... this.
 560         (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
 561         (PREFIX_0FAE_REG_5_MOD_3): ... this.
 562         (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
 563         (PREFIX_0FAE_REG_6_MOD_0): ... this.
 564         (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
 565         (PREFIX_0FAE_REG_6_MOD_3): ... this.
 566         (PREFIX_0FAE_REG_7): Rename to ...
 567         (PREFIX_0FAE_REG_7_MOD_0): ... this.
 568         (PREFIX_MOD_0_0FC3): Rename to ...
 569         (PREFIX_0FC3_MOD_0): ... this.
 570         (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
 571         (PREFIX_0FC7_REG_6_MOD_0): ... this.
 572         (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
 573         (PREFIX_0FC7_REG_6_MOD_3): ... this.
 574         (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
 575         (PREFIX_0FC7_REG_7_MOD_3): ... this.
 576         (reg_table, prefix_table, mod_table, rm_table): Adjust
 577         accordingly.
 578
 579 2019-11-04  Nick Clifton  <nickc@redhat.com>
 580
 581         * v850-dis.c (get_v850_sreg_name): New function.  Returns the name
 582         of a v850 system register.  Move the v850_sreg_names array into
 583         this function.
 584         (get_v850_reg_name): Likewise for ordinary register names.
 585         (get_v850_vreg_name): Likewise for vector register names.
 586         (get_v850_cc_name): Likewise for condition codes.
 587         * get_v850_float_cc_name): Likewise for floating point condition
 588         codes.
 589         (get_v850_cacheop_name): Likewise for cache-ops.
 590         (get_v850_prefop_name): Likewise for pref-ops.
 591         (disassemble): Use the new accessor functions.
 592
 593 2019-10-30  Delia Burduv   <delia.burduv@arm.com>
 594
 595         * aarch64-opc.c (print_immediate_offset_address): Don't print the
 596         immediate for the writeback form of ldraa/ldrab if it is 0.
 597         * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
 598         * aarch64-opc-2.c: Regenerated.
 599
 600 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 601
 602         * i386-gen.c (operand_type_shorthands): Delete.
 603         (operand_type_init): Expand previous shorthands.
 604         (set_bitfield_from_shorthand): Rename back to ...
 605         (set_bitfield_from_cpu_flag_init): ... this.  Drop processing
 606         of operand_type_init[].
 607         (set_bitfield): Adjust call to the above function.
 608         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
 609         RegXMM, RegYMM, RegZMM): Define.
 610         * i386-reg.tbl: Expand prior shorthands.
 611
 612 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 613
 614         * i386-gen.c (output_i386_opcode): Change order of fields
 615         emitted to output.
 616         * i386-opc.h (struct insn_template): Move operands field.
 617         Convert extension_opcode field to unsigned short.
 618         * i386-tbl.h: Re-generate.
 619
 620 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 621
 622         * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
 623         of W.
 624         * i386-opc.h (W): Extend comment.
 625         * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
 626         general purpose variants not allowing for byte operands.
 627         * i386-tbl.h: Re-generate.
 628
 629 2019-10-29  Nick Clifton  <nickc@redhat.com>
 630
 631         * tic30-dis.c (print_branch): Correct size of operand array.
 632
 633 2019-10-29  Nick Clifton  <nickc@redhat.com>
 634
 635         * d30v-dis.c (print_insn): Check that operand index is valid
 636         before attempting to access the operands array.
 637
 638 2019-10-29  Nick Clifton  <nickc@redhat.com>
 639
 640         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
 641         locating the bit to be tested.
 642
 643 2019-10-29  Nick Clifton  <nickc@redhat.com>
 644
 645         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
 646         values.
 647         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
 648         (print_insn_s12z):  Check for illegal size values.
 649
 650 2019-10-28  Nick Clifton  <nickc@redhat.com>
 651
 652         * csky-dis.c (csky_chars_to_number): Check for a negative
 653         count. Use an unsigned integer to construct the return value.
 654
 655 2019-10-28  Nick Clifton  <nickc@redhat.com>
 656
 657         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
 658         operand buffer.  Set value to 15 not 13.
 659         (get_register_operand): Use OPERAND_BUFFER_LEN.
 660         (get_indirect_operand): Likewise.
 661         (print_two_operand): Likewise.
 662         (print_three_operand): Likewise.
 663         (print_oar_insn): Likewise.
 664
 665 2019-10-28  Nick Clifton  <nickc@redhat.com>
 666
 667         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
 668         (bit_extract_simple): Likewise.
 669         (bit_copy): Likewise.
 670         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
 671         index_offset array are not accessed.
 672
 673 2019-10-28  Nick Clifton  <nickc@redhat.com>
 674
 675         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
 676         operand.
 677
 678 2019-10-25  Nick Clifton  <nickc@redhat.com>
 679
 680         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
 681         access to opcodes.op array element.
 682
 683 2019-10-23  Nick Clifton  <nickc@redhat.com>
 684
 685         * rx-dis.c (get_register_name): Fix spelling typo in error
 686         message.
 687         (get_condition_name, get_flag_name, get_double_register_name)
 688         (get_double_register_high_name, get_double_register_low_name)
 689         (get_double_control_register_name, get_double_condition_name)
 690         (get_opsize_name, get_size_name): Likewise.
 691
 692 2019-10-22  Nick Clifton  <nickc@redhat.com>
 693
 694         * rx-dis.c (get_size_name): New function.  Provides safe
 695         access to name array.
 696         (get_opsize_name): Likewise.
 697         (print_insn_rx): Use the accessor functions.
 698
 699 2019-10-16  Nick Clifton  <nickc@redhat.com>
 700
 701         * rx-dis.c (get_register_name): New function.  Provides safe
 702         access to name array.
 703         (get_condition_name, get_flag_name, get_double_register_name)
 704         (get_double_register_high_name, get_double_register_low_name)
 705         (get_double_control_register_name, get_double_condition_name):
 706         Likewise.
 707         (print_insn_rx): Use the accessor functions.
 708
 709 2019-10-09  Nick Clifton  <nickc@redhat.com>
 710
 711         PR 25041
 712         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
 713         instructions.
 714
 715 2019-10-07  Jan Beulich  <jbeulich@suse.com>
 716
 717         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
 718         (cmpsd): Likewise. Move EsSeg to other operand.
 719         * opcodes/i386-tbl.h: Re-generate.
 720
 721 2019-09-23  Alan Modra  <amodra@gmail.com>
 722
 723         * m68k-dis.c: Include cpu-m68k.h
 724
 725 2019-09-23  Alan Modra  <amodra@gmail.com>
 726
 727         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
 728         "elf/mips.h" earlier.
 729
 730 2018-09-20  Jan Beulich  <jbeulich@suse.com>
 731
 732         PR gas/25012
 733         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 734         with SReg operand.
 735         * i386-tbl.h: Re-generate.
 736
 737 2019-09-18  Alan Modra  <amodra@gmail.com>
 738
 739         * arc-ext.c: Update throughout for bfd section macro changes.
 740
 741 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 742
 743         * Makefile.in: Re-generate.
 744         * configure: Re-generate.
 745
 746 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 747
 748         * riscv-opc.c (riscv_opcodes): Change subset field
 749         to insn_class field for all instructions.
 750         (riscv_insn_types): Likewise.
 751
 752 2019-09-16  Phil Blundell  <pb@pbcl.net>
 753
 754         * configure: Regenerated.
 755
 756 2019-09-10  Miod Vallat  <miod@online.fr>
 757
 758         PR 24982
 759         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 760
 761 2019-09-09  Phil Blundell  <pb@pbcl.net>
 762
 763         binutils 2.33 branch created.
 764
 765 2019-09-03  Nick Clifton  <nickc@redhat.com>
 766
 767         PR 24961
 768         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 769         greater than zero before indexing via (bufcnt -1).
 770
 771 2019-09-03  Nick Clifton  <nickc@redhat.com>
 772
 773         PR 24958
 774         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 775         (MAX_SPEC_REG_NAME_LEN): Define.
 776         (struct mmix_dis_info): Use defined constants for array lengths.
 777         (get_reg_name): New function.
 778         (get_sprec_reg_name): New function.
 779         (print_insn_mmix): Use new functions.
 780
 781 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 782
 783         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 784         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 785         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 786
 787 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 788
 789         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 790         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 791         (aarch64_sys_reg_supported_p): Update checks for the above.
 792
 793 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 794
 795         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 796         cases MVE_SQRSHRL and MVE_UQRSHLL.
 797         (print_insn_mve): Add case for specifier 'k' to check
 798         specific bit of the instruction.
 799
 800 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 801
 802         PR 24854
 803         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 804         encountering an unknown machine type.
 805         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 806         cases return -1 rather than calling abort.
 807
 808 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 809
 810         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 811         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 812         IgnoreSize.
 813         * i386-tbl.h: Re-generate.
 814
 815 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 816
 817         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 818         instructions.
 819
 820 2019-07-30  Mel Chen <mel.chen@sifive.com>
 821
 822         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 823         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 824
 825         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 826         fscsr.
 827
 828 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 829
 830         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 831         and MPY class instructions.
 832         (parse_option): Add nps400 option.
 833         (print_arc_disassembler_options): Add nps400 info.
 834
 835 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 836
 837         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 838         (bspop): Likewise.
 839         (modapp): Likewise.
 840         * arc-opc.c (RAD_CHK): Add.
 841         * arc-tbl.h: Regenerate.
 842
 843 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 844
 845         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 846         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 847
 848 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 849
 850         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 851         instructions as UNPREDICTABLE.
 852
 853 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 854
 855         * bpf-desc.c: Regenerated.
 856
 857 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 858
 859         * i386-gen.c (static_assert): Define.
 860         (main): Use it.
 861         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 862         (Opcode_Modifier_Num): ... this.
 863         (Mem): Delete.
 864
 865 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 866
 867         * i386-gen.c (operand_types): Move RegMem ...
 868         (opcode_modifiers): ... here.
 869         * i386-opc.h (RegMem): Move to opcode modifer enum.
 870         (union i386_operand_type): Move regmem field ...
 871         (struct i386_opcode_modifier): ... here.
 872         * i386-opc.tbl (RegMem): Define.
 873         (mov, movq): Move RegMem on segment, control, debug, and test
 874         register flavors.
 875         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 876         to non-SSE2AVX flavor.
 877         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 878         Move RegMem on register only flavors. Drop IgnoreSize from
 879         legacy encoding flavors.
 880         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 881         flavors.
 882         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 883         register only flavors.
 884         (vmovd): Move RegMem and drop IgnoreSize on register only
 885         flavor. Change opcode and operand order to store form.
 886         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 887
 888 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 889
 890         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 891         entries.
 892         * i386-opc.h (SReg2, SReg3): Replace by ...
 893         (SReg): ... this.
 894         (union i386_operand_type): Replace sreg fields.
 895         * i386-opc.tbl (mov, ): Use SReg.
 896         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 897         register flavors.
 898         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 899         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 900
 901 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 902
 903         * bpf-desc.c: Regenerate.
 904         * bpf-opc.c: Likewise.
 905         * bpf-opc.h: Likewise.
 906
 907 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 908
 909         * bpf-desc.c: Regenerate.
 910         * bpf-opc.c: Likewise.
 911
 912 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 913
 914         * arm-dis.c (print_insn_coprocessor): Rename index to
 915         index_operand.
 916
 917 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 918
 919         * riscv-opc.c (riscv_insn_types): Add r4 type.
 920
 921         * riscv-opc.c (riscv_insn_types): Add b and j type.
 922
 923         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 924         format for sb type and correct s type.
 925
 926 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 927
 928         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 929         SVE FMOV alias of FCPY.
 930
 931 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 932
 933         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 934         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 935
 936 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 937
 938         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 939         registers in an instruction prefixed by MOVPRFX.
 940
 941 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 942
 943         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 944         sve_size_13 icode to account for variant behaviour of
 945         pmull{t,b}.
 946         * aarch64-dis-2.c: Regenerate.
 947         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 948         sve_size_13 icode to account for variant behaviour of
 949         pmull{t,b}.
 950         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 951         (OP_SVE_VVV_Q_D): Add new qualifier.
 952         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 953         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 954         AES and those not.
 955
 956 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 957
 958         * opcodes/i386-gen.c (operand_type_init): Remove
 959         OPERAND_TYPE_VEC_IMM4 entry.
 960         (operand_types): Remove Vec_Imm4.
 961         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 962         (union i386_operand_type): Remove vec_imm4.
 963         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 964         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 965
 966 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 967
 968         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 969         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 970         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 971         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 972         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 973         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 974         * i386-tbl.h: Re-generate.
 975
 976 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 977
 978         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 979         register operands.
 980         * i386-tbl.h: Re-generate.
 981
 982 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 983
 984         * i386-opc.tbl (C): New.
 985         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 986         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 987         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 988         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 989         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 990         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 991         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 992         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 993         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 994         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 995         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 996         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 997         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 998         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 999         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
1000         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
1001         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
1002         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
1003         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
1004         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
1005         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
1006         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
1007         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
1008         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
1009         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
1010         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
1011         flavors.
1012         * i386-tbl.h: Re-generate.
1013
1014 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1015
1016         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1017         register operands.
1018         * i386-tbl.h: Re-generate.
1019
1020 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1021
1022         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
1023         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
1024         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
1025         * i386-tbl.h: Re-generate.
1026
1027 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1028
1029         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
1030         Disp8MemShift from register only templates.
1031         * i386-tbl.h: Re-generate.
1032
1033 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1034
1035         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
1036         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
1037         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
1038         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
1039         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
1040         EVEX_W_0F11_P_3_M_1): Delete.
1041         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
1042         EVEX_W_0F11_P_3): New.
1043         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
1044         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
1045         MOD_EVEX_0F11_PREFIX_3 table entries.
1046         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
1047         PREFIX_EVEX_0F11 table entries.
1048         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
1049         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1050         EVEX_W_0F11_P_3_M_{0,1} table entries.
1051
1052 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1053
1054         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1055         Delete.
1056
1057 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
1058
1059         PR binutils/24719
1060         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1061         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1062         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1063         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1064         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1065         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1066         EVEX_LEN_0F38C7_R_6_P_2_W_1.
1067         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1068         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1069         PREFIX_EVEX_0F38C6_REG_6 entries.
1070         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1071         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1072         EVEX_W_0F38C7_R_6_P_2 entries.
1073         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1074         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1075         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1076         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1077         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1078         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1079         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1080
1081 2019-06-27  Jan Beulich  <jbeulich@suse.com>
1082
1083         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1084         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1085         VEX_LEN_0F2D_P_3): Delete.
1086         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1087         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1088         (prefix_table): ... here.
1089
1090 2019-06-27  Jan Beulich  <jbeulich@suse.com>
1091
1092         * i386-dis.c (Iq): Delete.
1093         (Id): New.
1094         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1095         TBM insns.
1096         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1097         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1098         (OP_E_memory): Also honor needindex when deciding whether an
1099         address size prefix needs printing.
1100         (OP_I): Remove handling of q_mode. Add handling of d_mode.
1101
1102 2019-06-26  Jim Wilson  <jimw@sifive.com>
1103
1104         PR binutils/24739
1105         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1106         Set info->display_endian to info->endian_code.
1107
1108 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1109
1110         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1111         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1112         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1113         OPERAND_TYPE_ACC64 entries.
1114         * i386-init.h: Re-generate.
1115
1116 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1117
1118         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1119         Delete.
1120         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1121         of dqa_mode.
1122         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1123         entries here.
1124         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1125         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1126
1127 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1128
1129         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1130         variables.
1131
1132 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1133
1134         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1135         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1136         movnti.
1137         * i386-opc.tbl (movnti): Add IgnoreSize.
1138         * i386-tbl.h: Re-generate.
1139
1140 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1141
1142         * i386-opc.tbl (and): Mark Imm8S form for optimization.
1143         * i386-tbl.h: Re-generate.
1144
1145 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
1146
1147         * i386-dis-evex.h: Break into ...
1148         * i386-dis-evex-len.h: New file.
1149         * i386-dis-evex-mod.h: Likewise.
1150         * i386-dis-evex-prefix.h: Likewise.
1151         * i386-dis-evex-reg.h: Likewise.
1152         * i386-dis-evex-w.h: Likewise.
1153         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1154         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1155         i386-dis-evex-mod.h.
1156
1157 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
1158
1159         PR binutils/24700
1160         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1161         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1162         EVEX_W_0F385B_P_2.
1163         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1164         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1165         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1166         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1167         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1168         EVEX_LEN_0F385B_P_2_W_1.
1169         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1170         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1171         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1172         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1173         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1174         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1175         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1176         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1177         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1178         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1179
1180 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
1181
1182         PR binutils/24691
1183         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1184         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1185         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1186         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1187         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1188         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1189         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1190         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1191         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1192         EVEX_LEN_0F3A43_P_2_W_1.
1193         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1194         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1195         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1196         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1197         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1198         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1199         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1200         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1201         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1202         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1203         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1204         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1205
1206 2019-06-14  Nick Clifton  <nickc@redhat.com>
1207
1208         * po/fr.po; Updated French translation.
1209
1210 2019-06-13  Stafford Horne  <shorne@gmail.com>
1211
1212         * or1k-asm.c: Regenerated.
1213         * or1k-desc.c: Regenerated.
1214         * or1k-desc.h: Regenerated.
1215         * or1k-dis.c: Regenerated.
1216         * or1k-ibld.c: Regenerated.
1217         * or1k-opc.c: Regenerated.
1218         * or1k-opc.h: Regenerated.
1219         * or1k-opinst.c: Regenerated.
1220
1221 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
1222
1223         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1224
1225 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
1226
1227         PR binutils/24633
1228         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1229         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1230         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1231         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1232         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1233         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1234         EVEX_LEN_0F3A1B_P_2_W_1.
1235         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1236         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1237         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1238         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1239         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1240         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1241         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1242         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1243
1244 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
1245
1246         PR binutils/24626
1247         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1248         EVEX.vvvv when disassembling VEX and EVEX instructions.
1249         (OP_VEX): Set vex.register_specifier to 0 after readding
1250         vex.register_specifier.
1251         (OP_Vex_2src_1): Likewise.
1252         (OP_Vex_2src_2): Likewise.
1253         (OP_LWP_E): Likewise.
1254         (OP_EX_Vex): Don't check vex.register_specifier.
1255         (OP_XMM_Vex): Likewise.
1256
1257 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1258             Lili Cui  <lili.cui@intel.com>
1259
1260         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1261         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1262         instructions.
1263         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1264         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1265         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1266         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1267         (i386_cpu_flags): Add cpuavx512_vp2intersect.
1268         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1269         * i386-init.h: Regenerated.
1270         * i386-tbl.h: Likewise.
1271
1272 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
1273             Lili Cui  <lili.cui@intel.com>
1274
1275         * doc/c-i386.texi: Document enqcmd.
1276         * testsuite/gas/i386/enqcmd-intel.d: New file.
1277         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1278         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1279         * testsuite/gas/i386/enqcmd.d: Likewise.
1280         * testsuite/gas/i386/enqcmd.s: Likewise.
1281         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1282         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1283         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1284         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1285         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1286         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1287         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1288         and x86-64-enqcmd.
1289
1290 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
1291
1292         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1293
1294 2019-06-03  Alan Modra  <amodra@gmail.com>
1295
1296         * ppc-dis.c (prefix_opcd_indices): Correct size.
1297
1298 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
1299
1300         PR gas/24625
1301         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1302         Disp8ShiftVL.
1303         * i386-tbl.h: Regenerated.
1304
1305 2019-05-24  Alan Modra  <amodra@gmail.com>
1306
1307         * po/POTFILES.in: Regenerate.
1308
1309 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1310             Alan Modra  <amodra@gmail.com>
1311
1312         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1313         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1314         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1315         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1316         XTOP>): Define and add entries.
1317         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1318         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1319         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1320         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1321
1322 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1323             Alan Modra  <amodra@gmail.com>
1324
1325         * ppc-dis.c (ppc_opts): Add "future" entry.
1326         (PREFIX_OPCD_SEGS): Define.
1327         (prefix_opcd_indices): New array.
1328         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1329         (lookup_prefix): New function.
1330         (print_insn_powerpc): Handle 64-bit prefix instructions.
1331         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1332         (PMRR, POWERXX): Define.
1333         (prefix_opcodes): New instruction table.
1334         (prefix_num_opcodes): New constant.
1335
1336 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
1337
1338         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1339         * configure: Regenerated.
1340         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1341         and cpu/bpf.opc.
1342         (HFILES): Add bpf-desc.h and bpf-opc.h.
1343         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1344         bpf-ibld.c and bpf-opc.c.
1345         (BPF_DEPS): Define.
1346         * Makefile.in: Regenerated.
1347         * disassemble.c (ARCH_bpf): Define.
1348         (disassembler): Add case for bfd_arch_bpf.
1349         (disassemble_init_for_target): Likewise.
1350         (enum epbf_isa_attr): Define.
1351         * disassemble.h: extern print_insn_bpf.
1352         * bpf-asm.c: Generated.
1353         * bpf-opc.h: Likewise.
1354         * bpf-opc.c: Likewise.
1355         * bpf-ibld.c: Likewise.
1356         * bpf-dis.c: Likewise.
1357         * bpf-desc.h: Likewise.
1358         * bpf-desc.c: Likewise.
1359
1360 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1361
1362         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1363         and VMSR with the new operands.
1364
1365 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1366
1367         * arm-dis.c (enum mve_instructions): New enum
1368         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1369         and cneg.
1370         (mve_opcodes): New instructions as above.
1371         (is_mve_encoding_conflict): Add cases for csinc, csinv,
1372         csneg and csel.
1373         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1374
1375 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1376
1377         * arm-dis.c (emun mve_instructions): Updated for new instructions.
1378         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1379         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1380         uqshl, urshrl and urshr.
1381         (is_mve_okay_in_it): Add new instructions to TRUE list.
1382         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1383         (print_insn_mve): Updated to accept new %j,
1384         %<bitfield>m and %<bitfield>n patterns.
1385
1386 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1387
1388         * mips-opc.c (mips_builtin_opcodes): Change source register
1389         constraint for DAUI.
1390
1391 2019-05-20  Nick Clifton  <nickc@redhat.com>
1392
1393         * po/fr.po: Updated French translation.
1394
1395 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1396             Michael Collison <michael.collison@arm.com>
1397
1398         * arm-dis.c (thumb32_opcodes): Add new instructions.
1399         (enum mve_instructions): Likewise.
1400         (enum mve_undefined): Add new reasons.
1401         (is_mve_encoding_conflict): Handle new instructions.
1402         (is_mve_undefined): Likewise.
1403         (is_mve_unpredictable): Likewise.
1404         (print_mve_undefined): Likewise.
1405         (print_mve_size): Likewise.
1406
1407 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1408             Michael Collison <michael.collison@arm.com>
1409
1410         * arm-dis.c (thumb32_opcodes): Add new instructions.
1411         (enum mve_instructions): Likewise.
1412         (is_mve_encoding_conflict): Handle new instructions.
1413         (is_mve_undefined): Likewise.
1414         (is_mve_unpredictable): Likewise.
1415         (print_mve_size): Likewise.
1416
1417 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1418             Michael Collison <michael.collison@arm.com>
1419
1420         * arm-dis.c (thumb32_opcodes): Add new instructions.
1421         (enum mve_instructions): Likewise.
1422         (is_mve_encoding_conflict): Likewise.
1423         (is_mve_unpredictable): Likewise.
1424         (print_mve_size): Likewise.
1425
1426 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1427             Michael Collison <michael.collison@arm.com>
1428
1429         * arm-dis.c (thumb32_opcodes): Add new instructions.
1430         (enum mve_instructions): Likewise.
1431         (is_mve_encoding_conflict): Handle new instructions.
1432         (is_mve_undefined): Likewise.
1433         (is_mve_unpredictable): Likewise.
1434         (print_mve_size): Likewise.
1435
1436 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1437             Michael Collison <michael.collison@arm.com>
1438
1439         * arm-dis.c (thumb32_opcodes): Add new instructions.
1440         (enum mve_instructions): Likewise.
1441         (is_mve_encoding_conflict): Handle new instructions.
1442         (is_mve_undefined): Likewise.
1443         (is_mve_unpredictable): Likewise.
1444         (print_mve_size): Likewise.
1445         (print_insn_mve): Likewise.
1446
1447 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1448             Michael Collison <michael.collison@arm.com>
1449
1450         * arm-dis.c (thumb32_opcodes): Add new instructions.
1451         (print_insn_thumb32): Handle new instructions.
1452
1453 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1454             Michael Collison <michael.collison@arm.com>
1455
1456         * arm-dis.c (enum mve_instructions): Add new instructions.
1457         (enum mve_undefined): Add new reasons.
1458         (is_mve_encoding_conflict): Handle new instructions.
1459         (is_mve_undefined): Likewise.
1460         (is_mve_unpredictable): Likewise.
1461         (print_mve_undefined): Likewise.
1462         (print_mve_size): Likewise.
1463         (print_mve_shift_n): Likewise.
1464         (print_insn_mve): Likewise.
1465
1466 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1467             Michael Collison <michael.collison@arm.com>
1468
1469         * arm-dis.c (enum mve_instructions): Add new instructions.
1470         (is_mve_encoding_conflict): Handle new instructions.
1471         (is_mve_unpredictable): Likewise.
1472         (print_mve_rotate): Likewise.
1473         (print_mve_size): Likewise.
1474         (print_insn_mve): Likewise.
1475
1476 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1477             Michael Collison <michael.collison@arm.com>
1478
1479         * arm-dis.c (enum mve_instructions): Add new instructions.
1480         (is_mve_encoding_conflict): Handle new instructions.
1481         (is_mve_unpredictable): Likewise.
1482         (print_mve_size): Likewise.
1483         (print_insn_mve): Likewise.
1484
1485 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1486             Michael Collison <michael.collison@arm.com>
1487
1488         * arm-dis.c (enum mve_instructions): Add new instructions.
1489         (enum mve_undefined): Add new reasons.
1490         (is_mve_encoding_conflict): Handle new instructions.
1491         (is_mve_undefined): Likewise.
1492         (is_mve_unpredictable): Likewise.
1493         (print_mve_undefined): Likewise.
1494         (print_mve_size): Likewise.
1495         (print_insn_mve): Likewise.
1496
1497 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1498             Michael Collison <michael.collison@arm.com>
1499
1500         * arm-dis.c (enum mve_instructions): Add new instructions.
1501         (is_mve_encoding_conflict): Handle new instructions.
1502         (is_mve_undefined): Likewise.
1503         (is_mve_unpredictable): Likewise.
1504         (print_mve_size): Likewise.
1505         (print_insn_mve): Likewise.
1506
1507 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1508             Michael Collison <michael.collison@arm.com>
1509
1510         * arm-dis.c (enum mve_instructions): Add new instructions.
1511         (enum mve_unpredictable): Add new reasons.
1512         (enum mve_undefined): Likewise.
1513         (is_mve_okay_in_it): Handle new isntructions.
1514         (is_mve_encoding_conflict): Likewise.
1515         (is_mve_undefined): Likewise.
1516         (is_mve_unpredictable): Likewise.
1517         (print_mve_vmov_index): Likewise.
1518         (print_simd_imm8): Likewise.
1519         (print_mve_undefined): Likewise.
1520         (print_mve_unpredictable): Likewise.
1521         (print_mve_size): Likewise.
1522         (print_insn_mve): Likewise.
1523
1524 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1525             Michael Collison <michael.collison@arm.com>
1526
1527         * arm-dis.c (enum mve_instructions): Add new instructions.
1528         (enum mve_unpredictable): Add new reasons.
1529         (enum mve_undefined): Likewise.
1530         (is_mve_encoding_conflict): Handle new instructions.
1531         (is_mve_undefined): Likewise.
1532         (is_mve_unpredictable): Likewise.
1533         (print_mve_undefined): Likewise.
1534         (print_mve_unpredictable): Likewise.
1535         (print_mve_rounding_mode): Likewise.
1536         (print_mve_vcvt_size): Likewise.
1537         (print_mve_size): Likewise.
1538         (print_insn_mve): Likewise.
1539
1540 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1541             Michael Collison <michael.collison@arm.com>
1542
1543         * arm-dis.c (enum mve_instructions): Add new instructions.
1544         (enum mve_unpredictable): Add new reasons.
1545         (enum mve_undefined): Likewise.
1546         (is_mve_undefined): Handle new instructions.
1547         (is_mve_unpredictable): Likewise.
1548         (print_mve_undefined): Likewise.
1549         (print_mve_unpredictable): Likewise.
1550         (print_mve_size): Likewise.
1551         (print_insn_mve): Likewise.
1552
1553 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1554             Michael Collison <michael.collison@arm.com>
1555
1556         * arm-dis.c (enum mve_instructions): Add new instructions.
1557         (enum mve_undefined): Add new reasons.
1558         (insns): Add new instructions.
1559         (is_mve_encoding_conflict):
1560         (print_mve_vld_str_addr): New print function.
1561         (is_mve_undefined): Handle new instructions.
1562         (is_mve_unpredictable): Likewise.
1563         (print_mve_undefined): Likewise.
1564         (print_mve_size): Likewise.
1565         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1566         (print_insn_mve):  Handle new operands.
1567
1568 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1569             Michael Collison <michael.collison@arm.com>
1570
1571         * arm-dis.c (enum mve_instructions): Add new instructions.
1572         (enum mve_unpredictable): Add new reasons.
1573         (is_mve_encoding_conflict): Handle new instructions.
1574         (is_mve_unpredictable): Likewise.
1575         (mve_opcodes): Add new instructions.
1576         (print_mve_unpredictable): Handle new reasons.
1577         (print_mve_register_blocks): New print function.
1578         (print_mve_size): Handle new instructions.
1579         (print_insn_mve): Likewise.
1580
1581 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1582             Michael Collison <michael.collison@arm.com>
1583
1584         * arm-dis.c (enum mve_instructions): Add new instructions.
1585         (enum mve_unpredictable): Add new reasons.
1586         (enum mve_undefined): Likewise.
1587         (is_mve_encoding_conflict): Handle new instructions.
1588         (is_mve_undefined): Likewise.
1589         (is_mve_unpredictable): Likewise.
1590         (coprocessor_opcodes): Move NEON VDUP from here...
1591         (neon_opcodes): ... to here.
1592         (mve_opcodes): Add new instructions.
1593         (print_mve_undefined):  Handle new reasons.
1594         (print_mve_unpredictable): Likewise.
1595         (print_mve_size): Handle new instructions.
1596         (print_insn_neon): Handle vdup.
1597         (print_insn_mve): Handle new operands.
1598
1599 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1600             Michael Collison <michael.collison@arm.com>
1601
1602         * arm-dis.c (enum mve_instructions): Add new instructions.
1603         (enum mve_unpredictable): Add new values.
1604         (mve_opcodes): Add new instructions.
1605         (vec_condnames): New array with vector conditions.
1606         (mve_predicatenames): New array with predicate suffixes.
1607         (mve_vec_sizename): New array with vector sizes.
1608         (enum vpt_pred_state): New enum with vector predication states.
1609         (struct vpt_block): New struct type for vpt blocks.
1610         (vpt_block_state): Global struct to keep track of state.
1611         (mve_extract_pred_mask): New helper function.
1612         (num_instructions_vpt_block): Likewise.
1613         (mark_outside_vpt_block): Likewise.
1614         (mark_inside_vpt_block): Likewise.
1615         (invert_next_predicate_state): Likewise.
1616         (update_next_predicate_state): Likewise.
1617         (update_vpt_block_state): Likewise.
1618         (is_vpt_instruction): Likewise.
1619         (is_mve_encoding_conflict): Add entries for new instructions.
1620         (is_mve_unpredictable): Likewise.
1621         (print_mve_unpredictable): Handle new cases.
1622         (print_instruction_predicate): Likewise.
1623         (print_mve_size): New function.
1624         (print_vec_condition): New function.
1625         (print_insn_mve): Handle vpt blocks and new print operands.
1626
1627 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1628
1629         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1630         8, 14 and 15 for Armv8.1-M Mainline.
1631
1632 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1633             Michael Collison <michael.collison@arm.com>
1634
1635         * arm-dis.c (enum mve_instructions): New enum.
1636         (enum mve_unpredictable): Likewise.
1637         (enum mve_undefined): Likewise.
1638         (struct mopcode32): New struct.
1639         (is_mve_okay_in_it): New function.
1640         (is_mve_architecture): Likewise.
1641         (arm_decode_field): Likewise.
1642         (arm_decode_field_multiple): Likewise.
1643         (is_mve_encoding_conflict): Likewise.
1644         (is_mve_undefined): Likewise.
1645         (is_mve_unpredictable): Likewise.
1646         (print_mve_undefined): Likewise.
1647         (print_mve_unpredictable): Likewise.
1648         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1649         (print_insn_mve): New function.
1650         (print_insn_thumb32): Handle MVE architecture.
1651         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1652
1653 2019-05-10  Nick Clifton  <nickc@redhat.com>
1654
1655         PR 24538
1656         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1657         end of the table prematurely.
1658
1659 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1660
1661         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1662         macros for R6.
1663
1664 2019-05-11  Alan Modra  <amodra@gmail.com>
1665
1666         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1667         when -Mraw is in effect.
1668
1669 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1670
1671         * aarch64-dis-2.c: Regenerate.
1672         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1673         (OP_SVE_BBB): New variant set.
1674         (OP_SVE_DDDD): New variant set.
1675         (OP_SVE_HHH): New variant set.
1676         (OP_SVE_HHHU): New variant set.
1677         (OP_SVE_SSS): New variant set.
1678         (OP_SVE_SSSU): New variant set.
1679         (OP_SVE_SHH): New variant set.
1680         (OP_SVE_SBBU): New variant set.
1681         (OP_SVE_DSS): New variant set.
1682         (OP_SVE_DHHU): New variant set.
1683         (OP_SVE_VMV_HSD_BHS): New variant set.
1684         (OP_SVE_VVU_HSD_BHS): New variant set.
1685         (OP_SVE_VVVU_SD_BH): New variant set.
1686         (OP_SVE_VVVU_BHSD): New variant set.
1687         (OP_SVE_VVV_QHD_DBS): New variant set.
1688         (OP_SVE_VVV_HSD_BHS): New variant set.
1689         (OP_SVE_VVV_HSD_BHS2): New variant set.
1690         (OP_SVE_VVV_BHS_HSD): New variant set.
1691         (OP_SVE_VV_BHS_HSD): New variant set.
1692         (OP_SVE_VVV_SD): New variant set.
1693         (OP_SVE_VVU_BHS_HSD): New variant set.
1694         (OP_SVE_VZVV_SD): New variant set.
1695         (OP_SVE_VZVV_BH): New variant set.
1696         (OP_SVE_VZV_SD): New variant set.
1697         (aarch64_opcode_table): Add sve2 instructions.
1698
1699 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1700
1701         * aarch64-asm-2.c: Regenerated.
1702         * aarch64-dis-2.c: Regenerated.
1703         * aarch64-opc-2.c: Regenerated.
1704         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1705         for SVE_SHLIMM_UNPRED_22.
1706         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1707         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1708         operand.
1709
1710 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1711
1712         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1713         sve_size_tsz_bhs iclass encode.
1714         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1715         sve_size_tsz_bhs iclass decode.
1716
1717 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1718
1719         * aarch64-asm-2.c: Regenerated.
1720         * aarch64-dis-2.c: Regenerated.
1721         * aarch64-opc-2.c: Regenerated.
1722         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1723         for SVE_Zm4_11_INDEX.
1724         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1725         (fields): Handle SVE_i2h field.
1726         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1727         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1728
1729 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1730
1731         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1732         sve_shift_tsz_bhsd iclass encode.
1733         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1734         sve_shift_tsz_bhsd iclass decode.
1735
1736 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1737
1738         * aarch64-asm-2.c: Regenerated.
1739         * aarch64-dis-2.c: Regenerated.
1740         * aarch64-opc-2.c: Regenerated.
1741         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1742         (aarch64_encode_variant_using_iclass): Handle
1743         sve_shift_tsz_hsd iclass encode.
1744         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1745         sve_shift_tsz_hsd iclass decode.
1746         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1747         for SVE_SHRIMM_UNPRED_22.
1748         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1749         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1750         operand.
1751
1752 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1753
1754         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1755         sve_size_013 iclass encode.
1756         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1757         sve_size_013 iclass decode.
1758
1759 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1760
1761         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1762         sve_size_bh iclass encode.
1763         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1764         sve_size_bh iclass decode.
1765
1766 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1767
1768         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1769         sve_size_sd2 iclass encode.
1770         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1771         sve_size_sd2 iclass decode.
1772         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1773         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1774
1775 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1776
1777         * aarch64-asm-2.c: Regenerated.
1778         * aarch64-dis-2.c: Regenerated.
1779         * aarch64-opc-2.c: Regenerated.
1780         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1781         for SVE_ADDR_ZX.
1782         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1783         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1784
1785 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1786
1787         * aarch64-asm-2.c: Regenerated.
1788         * aarch64-dis-2.c: Regenerated.
1789         * aarch64-opc-2.c: Regenerated.
1790         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1791         for SVE_Zm3_11_INDEX.
1792         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1793         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1794         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1795         fields.
1796         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1797
1798 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1799
1800         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1801         sve_size_hsd2 iclass encode.
1802         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1803         sve_size_hsd2 iclass decode.
1804         * aarch64-opc.c (fields): Handle SVE_size field.
1805         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1806
1807 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1808
1809         * aarch64-asm-2.c: Regenerated.
1810         * aarch64-dis-2.c: Regenerated.
1811         * aarch64-opc-2.c: Regenerated.
1812         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1813         for SVE_IMM_ROT3.
1814         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1815         (fields): Handle SVE_rot3 field.
1816         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1817         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1818
1819 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1820
1821         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1822         instructions.
1823
1824 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1825
1826         * aarch64-tbl.h
1827         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1828         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1829         aarch64_feature_sve2bitperm): New feature sets.
1830         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1831         for feature set addresses.
1832         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1833         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1834
1835 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1836             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1837
1838         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1839         argument and set ASE_EVA_R6 appropriately.
1840         (set_default_mips_dis_options): Pass ISA to above.
1841         (parse_mips_dis_option): Likewise.
1842         * mips-opc.c (EVAR6): New macro.
1843         (mips_builtin_opcodes): Add llwpe, scwpe.
1844
1845 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1846
1847         * aarch64-asm-2.c: Regenerated.
1848         * aarch64-dis-2.c: Regenerated.
1849         * aarch64-opc-2.c: Regenerated.
1850         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1851         AARCH64_OPND_TME_UIMM16.
1852         (aarch64_print_operand): Likewise.
1853         * aarch64-tbl.h (QL_IMM_NIL): New.
1854         (TME): New.
1855         (_TME_INSN): New.
1856         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1857
1858 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1859
1860         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1861
1862 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1863             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1864
1865         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1866
1867 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1868
1869         * s12z-opc.h: Add extern "C" bracketing to help
1870         users who wish to use this interface in c++ code.
1871
1872 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1873
1874         * s12z-opc.c (bm_decode): Handle bit map operations with the
1875         "reserved0" mode.
1876
1877 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1878
1879         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1880         specifier.  Add entries for VLDR and VSTR of system registers.
1881         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1882         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1883         of %J and %K format specifier.
1884
1885 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1886
1887         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1888         Add new entries for VSCCLRM instruction.
1889         (print_insn_coprocessor): Handle new %C format control code.
1890
1891 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1892
1893         * arm-dis.c (enum isa): New enum.
1894         (struct sopcode32): New structure.
1895         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1896         set isa field of all current entries to ANY.
1897         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1898         Only match an entry if its isa field allows the current mode.
1899
1900 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1901
1902         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1903         CLRM.
1904         (print_insn_thumb32): Add logic to print %n CLRM register list.
1905
1906 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1907
1908         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1909         and %Q patterns.
1910
1911 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1912
1913         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1914         (print_insn_thumb32): Edit the switch case for %Z.
1915
1916 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1917
1918         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1919
1920 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1921
1922         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1923
1924 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1925
1926         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1927
1928 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1929
1930         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1931         Arm register with r13 and r15 unpredictable.
1932         (thumb32_opcodes): New instructions for bfx and bflx.
1933
1934 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1935
1936         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1937
1938 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1939
1940         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1941
1942 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1943
1944         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1945
1946 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1947
1948         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1949
1950 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1951
1952         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1953         "optr". ("operator" is a reserved word in c++).
1954
1955 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1956
1957         * aarch64-opc.c (aarch64_print_operand): Add case for
1958         AARCH64_OPND_Rt_SP.
1959         (verify_constraints): Likewise.
1960         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1961         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1962         to accept Rt|SP as first operand.
1963         (AARCH64_OPERANDS): Add new Rt_SP.
1964         * aarch64-asm-2.c: Regenerated.
1965         * aarch64-dis-2.c: Regenerated.
1966         * aarch64-opc-2.c: Regenerated.
1967
1968 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1969
1970         * aarch64-asm-2.c: Regenerated.
1971         * aarch64-dis-2.c: Likewise.
1972         * aarch64-opc-2.c: Likewise.
1973         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1974
1975 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1976
1977         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1978
1979 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1980
1981         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1982         * i386-init.h: Regenerated.
1983
1984 2019-04-07  Alan Modra  <amodra@gmail.com>
1985
1986         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1987         op_separator to control printing of spaces, comma and parens
1988         rather than need_comma, need_paren and spaces vars.
1989
1990 2019-04-07  Alan Modra  <amodra@gmail.com>
1991
1992         PR 24421
1993         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1994         (print_insn_neon, print_insn_arm): Likewise.
1995
1996 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1997
1998         * i386-dis-evex.h (evex_table): Updated to support BF16
1999         instructions.
2000         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
2001         and EVEX_W_0F3872_P_3.
2002         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
2003         (cpu_flags): Add bitfield for CpuAVX512_BF16.
2004         * i386-opc.h (enum): Add CpuAVX512_BF16.
2005         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
2006         * i386-opc.tbl: Add AVX512 BF16 instructions.
2007         * i386-init.h: Regenerated.
2008         * i386-tbl.h: Likewise.
2009
2010 2019-04-05  Alan Modra  <amodra@gmail.com>
2011
2012         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
2013         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
2014         to favour printing of "-" branch hint when using the "y" bit.
2015         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
2016
2017 2019-04-05  Alan Modra  <amodra@gmail.com>
2018
2019         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
2020         opcode until first operand is output.
2021
2022 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
2023
2024         PR gas/24349
2025         * ppc-opc.c (valid_bo_pre_v2): Add comments.
2026         (valid_bo_post_v2): Add support for 'at' branch hints.
2027         (insert_bo): Only error on branch on ctr.
2028         (get_bo_hint_mask): New function.
2029         (insert_boe): Add new 'branch_taken' formal argument.  Add support
2030         for inserting 'at' branch hints.
2031         (extract_boe): Add new 'branch_taken' formal argument.  Add support
2032         for extracting 'at' branch hints.
2033         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
2034         (BOE): Delete operand.
2035         (BOM, BOP): New operands.
2036         (RM): Update value.
2037         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
2038         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
2039         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
2040         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
2041         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
2042         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
2043         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
2044         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
2045         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
2046         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
2047         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
2048         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
2049         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2050         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2051         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2052         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2053         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2054         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2055         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2056         bttarl+>: New extended mnemonics.
2057
2058 2019-03-28  Alan Modra  <amodra@gmail.com>
2059
2060         PR 24390
2061         * ppc-opc.c (BTF): Define.
2062         (powerpc_opcodes): Use for mtfsb*.
2063         * ppc-dis.c (print_insn_powerpc): Print fields with both
2064         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2065
2066 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2067
2068         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2069         (mapping_symbol_for_insn): Implement new algorithm.
2070         (print_insn): Remove duplicate code.
2071
2072 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2073
2074         * aarch64-dis.c (print_insn_aarch64):
2075         Implement override.
2076
2077 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2078
2079         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2080         order.
2081
2082 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2083
2084         * aarch64-dis.c (last_stop_offset): New.
2085         (print_insn_aarch64): Use stop_offset.
2086
2087 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
2088
2089         PR gas/24359
2090         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2091         CPU_ANY_AVX2_FLAGS.
2092         * i386-init.h: Regenerated.
2093
2094 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
2095
2096         PR gas/24348
2097         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2098         vmovdqu16, vmovdqu32 and vmovdqu64.
2099         * i386-tbl.h: Regenerated.
2100
2101 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2102
2103         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
2104         from vstrszb, vstrszh, and vstrszf.
2105
2106 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2107
2108         * s390-opc.txt: Add instruction descriptions.
2109
2110 2019-02-08  Jim Wilson  <jimw@sifive.com>
2111
2112         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2113         <bne>: Likewise.
2114
2115 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2116
2117         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2118
2119 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2120
2121         PR binutils/23212
2122         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2123         * aarch64-opc.c (verify_elem_sd): New.
2124         (fields): Add FLD_sz entr.
2125         * aarch64-tbl.h (_SIMD_INSN): New.
2126         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2127         fmulx scalar and vector by element isns.
2128
2129 2019-02-07  Nick Clifton  <nickc@redhat.com>
2130
2131         * po/sv.po: Updated Swedish translation.
2132
2133 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
2134
2135         * s390-mkopc.c (main): Accept arch13 as cpu string.
2136         * s390-opc.c: Add new instruction formats and instruction opcode
2137         masks.
2138         * s390-opc.txt: Add new arch13 instructions.
2139
2140 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2141
2142         * aarch64-tbl.h (QL_LDST_AT): Update macro.
2143         (aarch64_opcode): Change encoding for stg, stzg
2144         st2g and st2zg.
2145         * aarch64-asm-2.c: Regenerated.
2146         * aarch64-dis-2.c: Regenerated.
2147         * aarch64-opc-2.c: Regenerated.
2148
2149 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2150
2151         * aarch64-asm-2.c: Regenerated.
2152         * aarch64-dis-2.c: Likewise.
2153         * aarch64-opc-2.c: Likewise.
2154         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2155
2156 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2157             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
2158
2159         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2160         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2161         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2162         * aarch64-dis.h (ext_addr_simple_2): Likewise.
2163         * aarch64-opc.c (operand_general_constraint_met_p): Remove
2164         case for ldstgv_indexed.
2165         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2166         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2167         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2168         * aarch64-asm-2.c: Regenerated.
2169         * aarch64-dis-2.c: Regenerated.
2170         * aarch64-opc-2.c: Regenerated.
2171
2172 2019-01-23  Nick Clifton  <nickc@redhat.com>
2173
2174         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2175
2176 2019-01-21  Nick Clifton  <nickc@redhat.com>
2177
2178         * po/de.po: Updated German translation.
2179         * po/uk.po: Updated Ukranian translation.
2180
2181 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
2182         * mips-dis.c (mips_arch_choices): Fix typo in
2183         gs464, gs464e and gs264e descriptors.
2184
2185 2019-01-19  Nick Clifton  <nickc@redhat.com>
2186
2187         * configure: Regenerate.
2188         * po/opcodes.pot: Regenerate.
2189
2190 2018-06-24  Nick Clifton  <nickc@redhat.com>
2191
2192         2.32 branch created.
2193
2194 2019-01-09  John Darrington <john@darrington.wattle.id.au>
2195
2196         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
2197         if it is null.
2198         -dis.c (opr_emit_disassembly): Do not omit an index if it is
2199         zero.
2200
2201 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
2202
2203         * configure: Regenerate.
2204
2205 2019-01-07  Alan Modra  <amodra@gmail.com>
2206
2207         * configure: Regenerate.
2208         * po/POTFILES.in: Regenerate.
2209
2210 2019-01-03  John Darrington <john@darrington.wattle.id.au>
2211
2212         * s12z-opc.c: New file.
2213         * s12z-opc.h: New file.
2214         * s12z-dis.c: Removed all code not directly related to display
2215         of instructions.  Used the interface provided by the new files
2216         instead.
2217         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
2218         * Makefile.in: Regenerate.
2219         * configure.ac (bfd_s12z_arch): Correct the dependencies.
2220         * configure: Regenerate.
2221
2222 2019-01-01  Alan Modra  <amodra@gmail.com>
2223
2224         Update year range in copyright notice of all files.
2225
2226 For older changes see ChangeLog-2018
2227 \f
2228 Copyright (C) 2019 Free Software Foundation, Inc.
2229
2230 Copying and distribution of this file, with or without modification,
2231 are permitted in any medium without royalty provided the copyright
2232 notice and this notice are preserved.
2233
2234 Local Variables:
2235 mode: change-log
2236 left-margin: 8
2237 fill-column: 74
2238 version-control: never
2239 End: