opcodes/ChangeLog

   1 2019-12-11  Alan Modra  <amodra@gmail.com>
   2
   3         * v850-dis.c (get_operand_value): Use unsigned arithmetic.  Don't
   4         sign extend using shifts.
   5
   6 2019-12-11  Alan Modra  <amodra@gmail.com>
   7
   8         * tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
   9
  10 2019-12-11  Alan Modra  <amodra@gmail.com>
  11
  12         * tic4x-dis.c (tic4x_print_register): Formatting.  Don't segfault
  13         on NULL registertable entry.
  14         (tic4x_hash_opcode): Use unsigned arithmetic.
  15
  16 2019-12-11  Alan Modra  <amodra@gmail.com>
  17
  18         * s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
  19
  20 2019-12-11  Alan Modra  <amodra@gmail.com>
  21
  22         * ns32k-dis.c (bit_extract): Use unsigned arithmetic.
  23         (bit_extract_simple, sign_extend): Likewise.
  24
  25 2019-12-11  Alan Modra  <amodra@gmail.com>
  26
  27         * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
  28
  29 2019-12-11  Alan Modra  <amodra@gmail.com>
  30
  31         * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
  32
  33 2019-12-11  Alan Modra  <amodra@gmail.com>
  34
  35         * m68k-dis.c (COERCE32): Cast value first.
  36         (NEXTLONG, NEXTULONG): Avoid signed overflow.
  37
  38 2019-12-11  Alan Modra  <amodra@gmail.com>
  39
  40         * h8300-dis.c (extract_immediate): Avoid signed overflow.
  41         (bfd_h8_disassemble): Likewise.
  42
  43 2019-12-11  Alan Modra  <amodra@gmail.com>
  44
  45         * d30v-dis.c (print_insn): Make opind unsigned.  Don't access
  46         past end of operands array.
  47
  48 2019-12-11  Alan Modra  <amodra@gmail.com>
  49
  50         * csky-dis.c (csky_chars_to_number): Rewrite.  Avoid signed
  51         overflow when collecting bytes of a number.
  52
  53 2019-12-11  Alan Modra  <amodra@gmail.com>
  54
  55         * cris-dis.c (print_with_operands): Avoid signed integer
  56         overflow when collecting bytes of a 32-bit integer.
  57
  58 2019-12-11  Alan Modra  <amodra@gmail.com>
  59
  60         * cr16-dis.c (EXTRACT, SBM): Rewrite.
  61         (cr16_match_opcode): Delete duplicate bcond test.
  62
  63 2019-12-11  Alan Modra  <amodra@gmail.com>
  64
  65         * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
  66         (SIGNBIT): New.
  67         (MASKBITS, SIGNEXTEND): Rewrite.
  68         (fmtconst): Don't use ? expression now that SIGNEXTEND uses
  69         unsigned arithmetic, instead assign result of SIGNEXTEND back
  70         to x.
  71         (fmtconst_val): Use 1u in shift expression.
  72
  73 2019-12-11  Alan Modra  <amodra@gmail.com>
  74
  75         * arc-dis.c (find_format_from_table): Use ull constant when
  76         shifting by up to 32.
  77
  78 2019-12-11  Alan Modra  <amodra@gmail.com>
  79
  80         PR 25270
  81         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
  82         false when field is zero for sve_size_tsz_bhs.
  83
  84 2019-12-11  Alan Modra  <amodra@gmail.com>
  85
  86         * epiphany-ibld.c: Regenerate.
  87
  88 2019-12-10  Alan Modra  <amodra@gmail.com>
  89
  90         PR 24960
  91         * disassemble.c (disassemble_free_target): New function.
  92
  93 2019-12-10  Alan Modra  <amodra@gmail.com>
  94
  95         * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
  96         * disassemble.c (disassemble_init_for_target): Likewise.
  97         * bpf-dis.c: Regenerate.
  98         * epiphany-dis.c: Regenerate.
  99         * fr30-dis.c: Regenerate.
 100         * frv-dis.c: Regenerate.
 101         * ip2k-dis.c: Regenerate.
 102         * iq2000-dis.c: Regenerate.
 103         * lm32-dis.c: Regenerate.
 104         * m32c-dis.c: Regenerate.
 105         * m32r-dis.c: Regenerate.
 106         * mep-dis.c: Regenerate.
 107         * mt-dis.c: Regenerate.
 108         * or1k-dis.c: Regenerate.
 109         * xc16x-dis.c: Regenerate.
 110         * xstormy16-dis.c: Regenerate.
 111
 112 2019-12-10  Alan Modra  <amodra@gmail.com>
 113
 114         * ppc-dis.c (private): Delete variable.
 115         (get_powerpc_dialect): Don't segfault on NULL info->private_data.
 116         (powerpc_init_dialect): Don't use global private.
 117
 118 2019-12-10  Alan Modra  <amodra@gmail.com>
 119
 120         * s12z-opc.c: Formatting.
 121
 122 2019-12-08  Alan Modra  <amodra@gmail.com>
 123
 124         * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
 125         registers.
 126
 127 2019-12-05  Jan Beulich  <jbeulich@suse.com>
 128
 129         * aarch64-tbl.h (aarch64_feature_crypto,
 130         aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
 131         CRYPTO_V8_2_INSN): Delete.
 132
 133 2019-12-05  Alan Modra  <amodra@gmail.com>
 134
 135         PR 25249
 136         * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
 137         (struct string_buf): New.
 138         (strbuf): New function.
 139         (get_field): Use strbuf rather than strdup of local temp.
 140         (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
 141         (get_field_rfsl, get_field_imm15): Likewise.
 142         (get_field_rd, get_field_r1, get_field_r2): Update macros.
 143         (get_field_special): Likewise.  Don't strcpy spr.  Formatting.
 144         (print_insn_microblaze): Formatting.  Init and pass string_buf to
 145         get_field functions.
 146
 147 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 148
 149         * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
 150         * i386-tbl.h: Re-generate.
 151
 152 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 153
 154         * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
 155
 156 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 157
 158         * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
 159         forms.
 160         (xbegin): Drop DefaultSize.
 161         * i386-tbl.h: Re-generate.
 162
 163 2019-11-22  Mihail Ionescu  <mihail.ionescu@arm.com>
 164
 165         * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
 166         Change the coproc CRC conditions to use the extension
 167         feature set, second word, base on ARM_EXT2_CRC.
 168
 169 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 170
 171         * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
 172         * i386-tbl.h: Re-generate.
 173
 174 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 175
 176         * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
 177         JumpInterSegment, and JumpAbsolute entries.
 178         * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
 179         JUMP_ABSOLUTE): Define.
 180         (struct i386_opcode_modifier): Extend jump field to 3 bits.
 181         Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
 182         fields.
 183         * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
 184         JumpInterSegment): Define.
 185         * i386-tbl.h: Re-generate.
 186
 187 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 188
 189         * i386-gen.c (operand_type_init): Remove
 190         OPERAND_TYPE_JUMPABSOLUTE entry.
 191         (opcode_modifiers): Add JumpAbsolute entry.
 192         (operand_types): Remove JumpAbsolute entry.
 193         * i386-opc.h (JumpAbsolute): Move between enums.
 194         (struct i386_opcode_modifier): Add jumpabsolute field.
 195         (union i386_operand_type): Remove jumpabsolute field.
 196         * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
 197         * i386-init.h, i386-tbl.h: Re-generate.
 198
 199 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 200
 201         * i386-gen.c (opcode_modifiers): Add AnySize entry.
 202         (operand_types): Remove AnySize entry.
 203         * i386-opc.h (AnySize): Move between enums.
 204         (struct i386_opcode_modifier): Add anysize field.
 205         (OTUnused): Un-comment.
 206         (union i386_operand_type): Remove anysize field.
 207         * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
 208         prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
 209         bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
 210         AnySize.
 211         * i386-tbl.h: Re-generate.
 212
 213 2019-11-12  Nelson Chu  <nelson.chu@sifive.com>
 214
 215         * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
 216         INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
 217         use the floating point register (FPR).
 218
 219 2019-11-12  Mihail Ionescu  <mihail.ionescu@arm.com>
 220
 221         * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
 222         cmode 1101.
 223         (is_mve_encoding_conflict): Update cmode conflict checks for
 224         MVE_VMVN_IMM.
 225
 226 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 227
 228         * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
 229         entry.
 230         (operand_types): Remove EsSeg entry.
 231         (main): Replace stale use of OTMax.
 232         * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
 233         (struct i386_opcode_modifier): Expand isstring field to 2 bits.
 234         (EsSeg): Delete.
 235         (OTUnused): Comment out.
 236         (union i386_operand_type): Remove esseg field.
 237         * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
 238         (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
 239         (ins, movs, smov, movsd): Add IsStringEsOpOp1.
 240         (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
 241         * i386-init.h, i386-tbl.h: Re-generate.
 242
 243 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 244
 245         * i386-gen.c (operand_instances): Add RegB entry.
 246         * i386-opc.h (enum operand_instance): Add RegB.
 247         * i386-opc.tbl (RegC, RegD, RegB): Define.
 248         (Acc, ShiftCount, InOutPortReg): Adjust definitions.
 249         (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
 250         monitorx, mwaitx): Drop ImmExt and convert encodings
 251         accordingly.
 252         * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
 253         (edx, rdx): Add Instance=RegD.
 254         (ebx, rbx): Add Instance=RegB.
 255         * i386-tbl.h: Re-generate.
 256
 257 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 258
 259         * i386-gen.c (operand_type_init): Adjust
 260         OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
 261         OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
 262         OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
 263         (operand_instances): New.
 264         (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
 265         (output_operand_type): New parameter "instance". Process it.
 266         (process_i386_operand_type): New local variable "instance".
 267         (main): Adjust static assertions.
 268         * i386-opc.h (INSTANCE_WIDTH): Define.
 269         (enum operand_instance): New.
 270         (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
 271         (union i386_operand_type): Replace acc, inoutportreg, and
 272         shiftcount by instance.
 273         * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
 274         * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
 275         Add Instance=.
 276         * i386-init.h, i386-tbl.h: Re-generate.
 277
 278 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 279
 280         * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
 281         smaxp/sminp entries' "tied_operand" field to 2.
 282
 283 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 284
 285         * aarch64-opc.c (operand_general_constraint_met_p): Replace
 286         "index" local variable by that of the already existing "num".
 287
 288 2019-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 289
 290         PR gas/25167
 291         * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
 292         * i386-tbl.h: Regenerated.
 293
 294 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 295
 296         * i386-gen.c (operand_type_init): Add Class= to
 297         OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
 298         OPERAND_TYPE_REGBND entry.
 299         (operand_classes): Add RegMask and RegBND entries.
 300         (operand_types): Drop RegMask and RegBND entry.
 301         * i386-opc.h (enum operand_class): Add RegMask and RegBND.
 302         (RegMask, RegBND): Delete.
 303         (union i386_operand_type): Remove regmask and regbnd fields.
 304         * i386-opc.tbl (RegMask, RegBND): Define.
 305         * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
 306         Class=RegBND.
 307         * i386-init.h, i386-tbl.h: Re-generate.
 308
 309 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 310
 311         * i386-gen.c (operand_type_init): Add Class= to
 312         OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
 313         OPERAND_TYPE_REGZMM entries.
 314         (operand_classes): Add RegMMX and RegSIMD entries.
 315         (operand_types): Drop RegMMX and RegSIMD entries.
 316         * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
 317         (RegMMX, RegSIMD): Delete.
 318         (union i386_operand_type): Remove regmmx and regsimd fields.
 319         * i386-opc.tbl (RegMMX): Define.
 320         (RegXMM, RegYMM, RegZMM): Add Class=.
 321         * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
 322         Class=RegSIMD.
 323         * i386-init.h, i386-tbl.h: Re-generate.
 324
 325 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 326
 327         * i386-gen.c (operand_type_init): Add Class= to
 328         OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
 329         entries.
 330         (operand_classes): Add RegCR, RegDR, and RegTR entries.
 331         (operand_types): Drop Control, Debug, and Test entries.
 332         * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
 333         (Control, Debug, Test): Delete.
 334         (union i386_operand_type): Remove control, debug, and test
 335         fields.
 336         * i386-opc.tbl (Control, Debug, Test): Define.
 337         * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
 338         Class=RegDR, and Test by Class=RegTR.
 339         * i386-init.h, i386-tbl.h: Re-generate.
 340
 341 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 342
 343         * i386-gen.c (operand_type_init): Add Class= to
 344         OPERAND_TYPE_SREG entry.
 345         (operand_classes): Add SReg entry.
 346         (operand_types): Drop SReg entry.
 347         * i386-opc.h (enum operand_class): Add SReg.
 348         (SReg): Delete.
 349         (union i386_operand_type): Remove sreg field.
 350         * i386-opc.tbl (SReg): Define.
 351         * i386-reg.tbl: Replace SReg by Class=SReg.
 352         * i386-init.h, i386-tbl.h: Re-generate.
 353
 354 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 355
 356         * i386-gen.c (operand_type_init): Add Class=. New
 357         OPERAND_TYPE_ANYIMM entry.
 358         (operand_classes): New.
 359         (operand_types): Drop Reg entry.
 360         (output_operand_type): New parameter "class". Process it.
 361         (process_i386_operand_type): New local variable "class".
 362         (main): Adjust static assertions.
 363         * i386-opc.h (CLASS_WIDTH): Define.
 364         (enum operand_class): New.
 365         (Reg): Replace by Class. Adjust comment.
 366         (union i386_operand_type): Replace reg by class.
 367         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
 368         Class=.
 369         * i386-reg.tbl: Replace Reg by Class=Reg.
 370         * i386-init.h: Re-generate.
 371
 372 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 373
 374         * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
 375         (aarch64_opcode_table): Add data gathering hint mnemonic.
 376         * opcodes/aarch64-dis-2.c: Account for new instruction.
 377
 378 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 379
 380         * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
 381
 382
 383 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 384
 385         * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
 386         aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
 387         aarch64_feature_f64mm): New feature sets.
 388         (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
 389         F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
 390         instructions.
 391         (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
 392         macros.
 393         (QL_MMLA64, OP_SVE_SBB): New qualifiers.
 394         (OP_SVE_QQQ): New qualifier.
 395         (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
 396         F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
 397         the movprfx constraint.
 398         (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
 399         (aarch64_opcode_table): Define new instructions smmla,
 400         ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
 401         uzip{1/2}, trn{1/2}.
 402         * aarch64-opc.c (operand_general_constraint_met_p): Handle
 403         AARCH64_OPND_SVE_ADDR_RI_S4x32.
 404         (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
 405         * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
 406         Account for new instructions.
 407         * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
 408         S4x32 operand.
 409         * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
 410
 411 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 412 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 413
 414         * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
 415         Armv8.6-A.
 416         (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
 417         (neon_opcodes): Add bfloat SIMD instructions.
 418         (print_insn_coprocessor): Add new control character %b to print
 419         condition code without checking cp_num.
 420         (print_insn_neon): Account for BFloat16 instructions that have no
 421         special top-byte handling.
 422
 423 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 424 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 425
 426         * arm-dis.c (print_insn_coprocessor,
 427         print_insn_generic_coprocessor): Create wrapper functions around
 428         the implementation of the print_insn_coprocessor control codes.
 429         (print_insn_coprocessor_1): Original print_insn_coprocessor
 430         function that now takes which array to look at as an argument.
 431         (print_insn_arm): Use both print_insn_coprocessor and
 432         print_insn_generic_coprocessor.
 433         (print_insn_thumb32): As above.
 434
 435 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 436 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 437
 438         * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
 439         in reglane special case.
 440         * aarch64-dis-2.c (aarch64_opcode_lookup_1,
 441         aarch64_find_next_opcode): Account for new instructions.
 442         * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
 443         in reglane special case.
 444         * aarch64-opc.c (struct operand_qualifier_data): Add data for
 445         new AARCH64_OPND_QLF_S_2H qualifier.
 446         * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
 447         QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
 448         (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
 449         sets.
 450         (BFLOAT_SVE, BFLOAT): New feature set macros.
 451         (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
 452         instructions.
 453         (aarch64_opcode_table): Define new instructions bfdot,
 454         bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
 455         bfcvtn2, bfcvt.
 456
 457 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 458 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 459
 460         * aarch64-tbl.h (ARMV8_6): New macro.
 461
 462 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 463
 464         * i386-dis.c (prefix_table): Add mcommit.
 465         (rm_table): Add rdpru.
 466         * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
 467         CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
 468         (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
 469         * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
 470         (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
 471         * i386-opc.tbl (mcommit, rdpru): New.
 472         * i386-init.h, i386-tbl.h: Re-generate.
 473
 474 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 475
 476         * i386-dis.c (OP_Mwait): Drop local variable "names", use
 477         "names32" instead.
 478         (OP_Monitor): Drop local variable "op1_names", re-purpose
 479         "names" for it instead, and replace former "names" uses by
 480         "names32" ones.
 481
 482 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 483
 484         PR/gas 25167
 485         * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
 486         operand-less forms.
 487         * opcodes/i386-tbl.h: Re-generate.
 488
 489 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 490
 491         * i386-dis.c (OP_Mwaitx): Delete.
 492         (prefix_table): Use OP_Mwait for mwaitx entry.
 493         (OP_Mwait): Also handle mwaitx.
 494
 495 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 496
 497         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
 498         PREFIX_0F01_REG_7_MOD_3_RM_3): New.
 499         (prefix_table): Add respective entries.
 500         (rm_table): Link to those entries.
 501
 502 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 503
 504         * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
 505         (REG_0F1C_P_0_MOD_0): ... this.
 506         (REG_0F1E_MOD_3): Rename to ...
 507         (REG_0F1E_P_1_MOD_3): ... this.
 508         (RM_0F01_REG_5): Rename to ...
 509         (RM_0F01_REG_5_MOD_3): ... this.
 510         (RM_0F01_REG_7): Rename to ...
 511         (RM_0F01_REG_7_MOD_3): ... this.
 512         (RM_0F1E_MOD_3_REG_7): Rename to ...
 513         (RM_0F1E_P_1_MOD_3_REG_7): ... this.
 514         (RM_0FAE_REG_6): Rename to ...
 515         (RM_0FAE_REG_6_MOD_3_P_0): ... this.
 516         (RM_0FAE_REG_7): Rename to ...
 517         (RM_0FAE_REG_7_MOD_3): ... this.
 518         (PREFIX_MOD_0_0F01_REG_5): Rename to ...
 519         (PREFIX_0F01_REG_5_MOD_0): ... this.
 520         (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
 521         (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
 522         (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
 523         (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
 524         (PREFIX_0FAE_REG_0): Rename to ...
 525         (PREFIX_0FAE_REG_0_MOD_3): ... this.
 526         (PREFIX_0FAE_REG_1): Rename to ...
 527         (PREFIX_0FAE_REG_1_MOD_3): ... this.
 528         (PREFIX_0FAE_REG_2): Rename to ...
 529         (PREFIX_0FAE_REG_2_MOD_3): ... this.
 530         (PREFIX_0FAE_REG_3): Rename to ...
 531         (PREFIX_0FAE_REG_3_MOD_3): ... this.
 532         (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
 533         (PREFIX_0FAE_REG_4_MOD_0): ... this.
 534         (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
 535         (PREFIX_0FAE_REG_4_MOD_3): ... this.
 536         (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
 537         (PREFIX_0FAE_REG_5_MOD_0): ... this.
 538         (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
 539         (PREFIX_0FAE_REG_5_MOD_3): ... this.
 540         (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
 541         (PREFIX_0FAE_REG_6_MOD_0): ... this.
 542         (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
 543         (PREFIX_0FAE_REG_6_MOD_3): ... this.
 544         (PREFIX_0FAE_REG_7): Rename to ...
 545         (PREFIX_0FAE_REG_7_MOD_0): ... this.
 546         (PREFIX_MOD_0_0FC3): Rename to ...
 547         (PREFIX_0FC3_MOD_0): ... this.
 548         (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
 549         (PREFIX_0FC7_REG_6_MOD_0): ... this.
 550         (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
 551         (PREFIX_0FC7_REG_6_MOD_3): ... this.
 552         (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
 553         (PREFIX_0FC7_REG_7_MOD_3): ... this.
 554         (reg_table, prefix_table, mod_table, rm_table): Adjust
 555         accordingly.
 556
 557 2019-11-04  Nick Clifton  <nickc@redhat.com>
 558
 559         * v850-dis.c (get_v850_sreg_name): New function.  Returns the name
 560         of a v850 system register.  Move the v850_sreg_names array into
 561         this function.
 562         (get_v850_reg_name): Likewise for ordinary register names.
 563         (get_v850_vreg_name): Likewise for vector register names.
 564         (get_v850_cc_name): Likewise for condition codes.
 565         * get_v850_float_cc_name): Likewise for floating point condition
 566         codes.
 567         (get_v850_cacheop_name): Likewise for cache-ops.
 568         (get_v850_prefop_name): Likewise for pref-ops.
 569         (disassemble): Use the new accessor functions.
 570
 571 2019-10-30  Delia Burduv   <delia.burduv@arm.com>
 572
 573         * aarch64-opc.c (print_immediate_offset_address): Don't print the
 574         immediate for the writeback form of ldraa/ldrab if it is 0.
 575         * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
 576         * aarch64-opc-2.c: Regenerated.
 577
 578 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 579
 580         * i386-gen.c (operand_type_shorthands): Delete.
 581         (operand_type_init): Expand previous shorthands.
 582         (set_bitfield_from_shorthand): Rename back to ...
 583         (set_bitfield_from_cpu_flag_init): ... this.  Drop processing
 584         of operand_type_init[].
 585         (set_bitfield): Adjust call to the above function.
 586         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
 587         RegXMM, RegYMM, RegZMM): Define.
 588         * i386-reg.tbl: Expand prior shorthands.
 589
 590 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 591
 592         * i386-gen.c (output_i386_opcode): Change order of fields
 593         emitted to output.
 594         * i386-opc.h (struct insn_template): Move operands field.
 595         Convert extension_opcode field to unsigned short.
 596         * i386-tbl.h: Re-generate.
 597
 598 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 599
 600         * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
 601         of W.
 602         * i386-opc.h (W): Extend comment.
 603         * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
 604         general purpose variants not allowing for byte operands.
 605         * i386-tbl.h: Re-generate.
 606
 607 2019-10-29  Nick Clifton  <nickc@redhat.com>
 608
 609         * tic30-dis.c (print_branch): Correct size of operand array.
 610
 611 2019-10-29  Nick Clifton  <nickc@redhat.com>
 612
 613         * d30v-dis.c (print_insn): Check that operand index is valid
 614         before attempting to access the operands array.
 615
 616 2019-10-29  Nick Clifton  <nickc@redhat.com>
 617
 618         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
 619         locating the bit to be tested.
 620
 621 2019-10-29  Nick Clifton  <nickc@redhat.com>
 622
 623         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
 624         values.
 625         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
 626         (print_insn_s12z):  Check for illegal size values.
 627
 628 2019-10-28  Nick Clifton  <nickc@redhat.com>
 629
 630         * csky-dis.c (csky_chars_to_number): Check for a negative
 631         count. Use an unsigned integer to construct the return value.
 632
 633 2019-10-28  Nick Clifton  <nickc@redhat.com>
 634
 635         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
 636         operand buffer.  Set value to 15 not 13.
 637         (get_register_operand): Use OPERAND_BUFFER_LEN.
 638         (get_indirect_operand): Likewise.
 639         (print_two_operand): Likewise.
 640         (print_three_operand): Likewise.
 641         (print_oar_insn): Likewise.
 642
 643 2019-10-28  Nick Clifton  <nickc@redhat.com>
 644
 645         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
 646         (bit_extract_simple): Likewise.
 647         (bit_copy): Likewise.
 648         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
 649         index_offset array are not accessed.
 650
 651 2019-10-28  Nick Clifton  <nickc@redhat.com>
 652
 653         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
 654         operand.
 655
 656 2019-10-25  Nick Clifton  <nickc@redhat.com>
 657
 658         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
 659         access to opcodes.op array element.
 660
 661 2019-10-23  Nick Clifton  <nickc@redhat.com>
 662
 663         * rx-dis.c (get_register_name): Fix spelling typo in error
 664         message.
 665         (get_condition_name, get_flag_name, get_double_register_name)
 666         (get_double_register_high_name, get_double_register_low_name)
 667         (get_double_control_register_name, get_double_condition_name)
 668         (get_opsize_name, get_size_name): Likewise.
 669
 670 2019-10-22  Nick Clifton  <nickc@redhat.com>
 671
 672         * rx-dis.c (get_size_name): New function.  Provides safe
 673         access to name array.
 674         (get_opsize_name): Likewise.
 675         (print_insn_rx): Use the accessor functions.
 676
 677 2019-10-16  Nick Clifton  <nickc@redhat.com>
 678
 679         * rx-dis.c (get_register_name): New function.  Provides safe
 680         access to name array.
 681         (get_condition_name, get_flag_name, get_double_register_name)
 682         (get_double_register_high_name, get_double_register_low_name)
 683         (get_double_control_register_name, get_double_condition_name):
 684         Likewise.
 685         (print_insn_rx): Use the accessor functions.
 686
 687 2019-10-09  Nick Clifton  <nickc@redhat.com>
 688
 689         PR 25041
 690         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
 691         instructions.
 692
 693 2019-10-07  Jan Beulich  <jbeulich@suse.com>
 694
 695         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
 696         (cmpsd): Likewise. Move EsSeg to other operand.
 697         * opcodes/i386-tbl.h: Re-generate.
 698
 699 2019-09-23  Alan Modra  <amodra@gmail.com>
 700
 701         * m68k-dis.c: Include cpu-m68k.h
 702
 703 2019-09-23  Alan Modra  <amodra@gmail.com>
 704
 705         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
 706         "elf/mips.h" earlier.
 707
 708 2018-09-20  Jan Beulich  <jbeulich@suse.com>
 709
 710         PR gas/25012
 711         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 712         with SReg operand.
 713         * i386-tbl.h: Re-generate.
 714
 715 2019-09-18  Alan Modra  <amodra@gmail.com>
 716
 717         * arc-ext.c: Update throughout for bfd section macro changes.
 718
 719 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 720
 721         * Makefile.in: Re-generate.
 722         * configure: Re-generate.
 723
 724 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 725
 726         * riscv-opc.c (riscv_opcodes): Change subset field
 727         to insn_class field for all instructions.
 728         (riscv_insn_types): Likewise.
 729
 730 2019-09-16  Phil Blundell  <pb@pbcl.net>
 731
 732         * configure: Regenerated.
 733
 734 2019-09-10  Miod Vallat  <miod@online.fr>
 735
 736         PR 24982
 737         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 738
 739 2019-09-09  Phil Blundell  <pb@pbcl.net>
 740
 741         binutils 2.33 branch created.
 742
 743 2019-09-03  Nick Clifton  <nickc@redhat.com>
 744
 745         PR 24961
 746         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 747         greater than zero before indexing via (bufcnt -1).
 748
 749 2019-09-03  Nick Clifton  <nickc@redhat.com>
 750
 751         PR 24958
 752         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 753         (MAX_SPEC_REG_NAME_LEN): Define.
 754         (struct mmix_dis_info): Use defined constants for array lengths.
 755         (get_reg_name): New function.
 756         (get_sprec_reg_name): New function.
 757         (print_insn_mmix): Use new functions.
 758
 759 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 760
 761         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 762         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 763         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 764
 765 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 766
 767         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 768         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 769         (aarch64_sys_reg_supported_p): Update checks for the above.
 770
 771 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 772
 773         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 774         cases MVE_SQRSHRL and MVE_UQRSHLL.
 775         (print_insn_mve): Add case for specifier 'k' to check
 776         specific bit of the instruction.
 777
 778 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 779
 780         PR 24854
 781         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 782         encountering an unknown machine type.
 783         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 784         cases return -1 rather than calling abort.
 785
 786 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 787
 788         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 789         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 790         IgnoreSize.
 791         * i386-tbl.h: Re-generate.
 792
 793 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 794
 795         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 796         instructions.
 797
 798 2019-07-30  Mel Chen <mel.chen@sifive.com>
 799
 800         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 801         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 802
 803         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 804         fscsr.
 805
 806 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 807
 808         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 809         and MPY class instructions.
 810         (parse_option): Add nps400 option.
 811         (print_arc_disassembler_options): Add nps400 info.
 812
 813 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 814
 815         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 816         (bspop): Likewise.
 817         (modapp): Likewise.
 818         * arc-opc.c (RAD_CHK): Add.
 819         * arc-tbl.h: Regenerate.
 820
 821 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 822
 823         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 824         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 825
 826 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 827
 828         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 829         instructions as UNPREDICTABLE.
 830
 831 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 832
 833         * bpf-desc.c: Regenerated.
 834
 835 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 836
 837         * i386-gen.c (static_assert): Define.
 838         (main): Use it.
 839         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 840         (Opcode_Modifier_Num): ... this.
 841         (Mem): Delete.
 842
 843 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 844
 845         * i386-gen.c (operand_types): Move RegMem ...
 846         (opcode_modifiers): ... here.
 847         * i386-opc.h (RegMem): Move to opcode modifer enum.
 848         (union i386_operand_type): Move regmem field ...
 849         (struct i386_opcode_modifier): ... here.
 850         * i386-opc.tbl (RegMem): Define.
 851         (mov, movq): Move RegMem on segment, control, debug, and test
 852         register flavors.
 853         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 854         to non-SSE2AVX flavor.
 855         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 856         Move RegMem on register only flavors. Drop IgnoreSize from
 857         legacy encoding flavors.
 858         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 859         flavors.
 860         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 861         register only flavors.
 862         (vmovd): Move RegMem and drop IgnoreSize on register only
 863         flavor. Change opcode and operand order to store form.
 864         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 865
 866 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 867
 868         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 869         entries.
 870         * i386-opc.h (SReg2, SReg3): Replace by ...
 871         (SReg): ... this.
 872         (union i386_operand_type): Replace sreg fields.
 873         * i386-opc.tbl (mov, ): Use SReg.
 874         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 875         register flavors.
 876         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 877         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 878
 879 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 880
 881         * bpf-desc.c: Regenerate.
 882         * bpf-opc.c: Likewise.
 883         * bpf-opc.h: Likewise.
 884
 885 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 886
 887         * bpf-desc.c: Regenerate.
 888         * bpf-opc.c: Likewise.
 889
 890 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 891
 892         * arm-dis.c (print_insn_coprocessor): Rename index to
 893         index_operand.
 894
 895 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 896
 897         * riscv-opc.c (riscv_insn_types): Add r4 type.
 898
 899         * riscv-opc.c (riscv_insn_types): Add b and j type.
 900
 901         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 902         format for sb type and correct s type.
 903
 904 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 905
 906         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 907         SVE FMOV alias of FCPY.
 908
 909 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 910
 911         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 912         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 913
 914 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 915
 916         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 917         registers in an instruction prefixed by MOVPRFX.
 918
 919 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 920
 921         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 922         sve_size_13 icode to account for variant behaviour of
 923         pmull{t,b}.
 924         * aarch64-dis-2.c: Regenerate.
 925         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 926         sve_size_13 icode to account for variant behaviour of
 927         pmull{t,b}.
 928         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 929         (OP_SVE_VVV_Q_D): Add new qualifier.
 930         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 931         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 932         AES and those not.
 933
 934 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 935
 936         * opcodes/i386-gen.c (operand_type_init): Remove
 937         OPERAND_TYPE_VEC_IMM4 entry.
 938         (operand_types): Remove Vec_Imm4.
 939         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 940         (union i386_operand_type): Remove vec_imm4.
 941         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 942         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 943
 944 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 945
 946         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 947         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 948         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 949         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 950         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 951         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 952         * i386-tbl.h: Re-generate.
 953
 954 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 955
 956         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 957         register operands.
 958         * i386-tbl.h: Re-generate.
 959
 960 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 961
 962         * i386-opc.tbl (C): New.
 963         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 964         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 965         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 966         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 967         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 968         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 969         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 970         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 971         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 972         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 973         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 974         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 975         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 976         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 977         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 978         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 979         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 980         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 981         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 982         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 983         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 984         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 985         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 986         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 987         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 988         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 989         flavors.
 990         * i386-tbl.h: Re-generate.
 991
 992 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 993
 994         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 995         register operands.
 996         * i386-tbl.h: Re-generate.
 997
 998 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 999
1000         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
1001         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
1002         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
1003         * i386-tbl.h: Re-generate.
1004
1005 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1006
1007         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
1008         Disp8MemShift from register only templates.
1009         * i386-tbl.h: Re-generate.
1010
1011 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1012
1013         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
1014         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
1015         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
1016         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
1017         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
1018         EVEX_W_0F11_P_3_M_1): Delete.
1019         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
1020         EVEX_W_0F11_P_3): New.
1021         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
1022         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
1023         MOD_EVEX_0F11_PREFIX_3 table entries.
1024         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
1025         PREFIX_EVEX_0F11 table entries.
1026         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
1027         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1028         EVEX_W_0F11_P_3_M_{0,1} table entries.
1029
1030 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1031
1032         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1033         Delete.
1034
1035 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
1036
1037         PR binutils/24719
1038         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1039         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1040         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1041         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1042         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1043         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1044         EVEX_LEN_0F38C7_R_6_P_2_W_1.
1045         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1046         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1047         PREFIX_EVEX_0F38C6_REG_6 entries.
1048         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1049         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1050         EVEX_W_0F38C7_R_6_P_2 entries.
1051         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1052         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1053         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1054         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1055         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1056         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1057         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1058
1059 2019-06-27  Jan Beulich  <jbeulich@suse.com>
1060
1061         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1062         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1063         VEX_LEN_0F2D_P_3): Delete.
1064         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1065         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1066         (prefix_table): ... here.
1067
1068 2019-06-27  Jan Beulich  <jbeulich@suse.com>
1069
1070         * i386-dis.c (Iq): Delete.
1071         (Id): New.
1072         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1073         TBM insns.
1074         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1075         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1076         (OP_E_memory): Also honor needindex when deciding whether an
1077         address size prefix needs printing.
1078         (OP_I): Remove handling of q_mode. Add handling of d_mode.
1079
1080 2019-06-26  Jim Wilson  <jimw@sifive.com>
1081
1082         PR binutils/24739
1083         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1084         Set info->display_endian to info->endian_code.
1085
1086 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1087
1088         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1089         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1090         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1091         OPERAND_TYPE_ACC64 entries.
1092         * i386-init.h: Re-generate.
1093
1094 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1095
1096         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1097         Delete.
1098         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1099         of dqa_mode.
1100         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1101         entries here.
1102         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1103         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1104
1105 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1106
1107         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1108         variables.
1109
1110 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1111
1112         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1113         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1114         movnti.
1115         * i386-opc.tbl (movnti): Add IgnoreSize.
1116         * i386-tbl.h: Re-generate.
1117
1118 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1119
1120         * i386-opc.tbl (and): Mark Imm8S form for optimization.
1121         * i386-tbl.h: Re-generate.
1122
1123 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
1124
1125         * i386-dis-evex.h: Break into ...
1126         * i386-dis-evex-len.h: New file.
1127         * i386-dis-evex-mod.h: Likewise.
1128         * i386-dis-evex-prefix.h: Likewise.
1129         * i386-dis-evex-reg.h: Likewise.
1130         * i386-dis-evex-w.h: Likewise.
1131         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1132         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1133         i386-dis-evex-mod.h.
1134
1135 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
1136
1137         PR binutils/24700
1138         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1139         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1140         EVEX_W_0F385B_P_2.
1141         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1142         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1143         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1144         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1145         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1146         EVEX_LEN_0F385B_P_2_W_1.
1147         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1148         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1149         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1150         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1151         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1152         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1153         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1154         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1155         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1156         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1157
1158 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
1159
1160         PR binutils/24691
1161         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1162         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1163         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1164         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1165         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1166         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1167         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1168         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1169         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1170         EVEX_LEN_0F3A43_P_2_W_1.
1171         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1172         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1173         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1174         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1175         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1176         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1177         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1178         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1179         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1180         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1181         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1182         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1183
1184 2019-06-14  Nick Clifton  <nickc@redhat.com>
1185
1186         * po/fr.po; Updated French translation.
1187
1188 2019-06-13  Stafford Horne  <shorne@gmail.com>
1189
1190         * or1k-asm.c: Regenerated.
1191         * or1k-desc.c: Regenerated.
1192         * or1k-desc.h: Regenerated.
1193         * or1k-dis.c: Regenerated.
1194         * or1k-ibld.c: Regenerated.
1195         * or1k-opc.c: Regenerated.
1196         * or1k-opc.h: Regenerated.
1197         * or1k-opinst.c: Regenerated.
1198
1199 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
1200
1201         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1202
1203 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
1204
1205         PR binutils/24633
1206         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1207         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1208         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1209         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1210         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1211         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1212         EVEX_LEN_0F3A1B_P_2_W_1.
1213         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1214         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1215         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1216         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1217         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1218         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1219         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1220         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1221
1222 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
1223
1224         PR binutils/24626
1225         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1226         EVEX.vvvv when disassembling VEX and EVEX instructions.
1227         (OP_VEX): Set vex.register_specifier to 0 after readding
1228         vex.register_specifier.
1229         (OP_Vex_2src_1): Likewise.
1230         (OP_Vex_2src_2): Likewise.
1231         (OP_LWP_E): Likewise.
1232         (OP_EX_Vex): Don't check vex.register_specifier.
1233         (OP_XMM_Vex): Likewise.
1234
1235 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1236             Lili Cui  <lili.cui@intel.com>
1237
1238         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1239         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1240         instructions.
1241         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1242         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1243         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1244         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1245         (i386_cpu_flags): Add cpuavx512_vp2intersect.
1246         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1247         * i386-init.h: Regenerated.
1248         * i386-tbl.h: Likewise.
1249
1250 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
1251             Lili Cui  <lili.cui@intel.com>
1252
1253         * doc/c-i386.texi: Document enqcmd.
1254         * testsuite/gas/i386/enqcmd-intel.d: New file.
1255         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1256         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1257         * testsuite/gas/i386/enqcmd.d: Likewise.
1258         * testsuite/gas/i386/enqcmd.s: Likewise.
1259         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1260         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1261         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1262         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1263         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1264         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1265         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1266         and x86-64-enqcmd.
1267
1268 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
1269
1270         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1271
1272 2019-06-03  Alan Modra  <amodra@gmail.com>
1273
1274         * ppc-dis.c (prefix_opcd_indices): Correct size.
1275
1276 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
1277
1278         PR gas/24625
1279         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1280         Disp8ShiftVL.
1281         * i386-tbl.h: Regenerated.
1282
1283 2019-05-24  Alan Modra  <amodra@gmail.com>
1284
1285         * po/POTFILES.in: Regenerate.
1286
1287 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1288             Alan Modra  <amodra@gmail.com>
1289
1290         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1291         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1292         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1293         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1294         XTOP>): Define and add entries.
1295         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1296         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1297         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1298         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1299
1300 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1301             Alan Modra  <amodra@gmail.com>
1302
1303         * ppc-dis.c (ppc_opts): Add "future" entry.
1304         (PREFIX_OPCD_SEGS): Define.
1305         (prefix_opcd_indices): New array.
1306         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1307         (lookup_prefix): New function.
1308         (print_insn_powerpc): Handle 64-bit prefix instructions.
1309         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1310         (PMRR, POWERXX): Define.
1311         (prefix_opcodes): New instruction table.
1312         (prefix_num_opcodes): New constant.
1313
1314 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
1315
1316         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1317         * configure: Regenerated.
1318         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1319         and cpu/bpf.opc.
1320         (HFILES): Add bpf-desc.h and bpf-opc.h.
1321         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1322         bpf-ibld.c and bpf-opc.c.
1323         (BPF_DEPS): Define.
1324         * Makefile.in: Regenerated.
1325         * disassemble.c (ARCH_bpf): Define.
1326         (disassembler): Add case for bfd_arch_bpf.
1327         (disassemble_init_for_target): Likewise.
1328         (enum epbf_isa_attr): Define.
1329         * disassemble.h: extern print_insn_bpf.
1330         * bpf-asm.c: Generated.
1331         * bpf-opc.h: Likewise.
1332         * bpf-opc.c: Likewise.
1333         * bpf-ibld.c: Likewise.
1334         * bpf-dis.c: Likewise.
1335         * bpf-desc.h: Likewise.
1336         * bpf-desc.c: Likewise.
1337
1338 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1339
1340         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1341         and VMSR with the new operands.
1342
1343 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1344
1345         * arm-dis.c (enum mve_instructions): New enum
1346         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1347         and cneg.
1348         (mve_opcodes): New instructions as above.
1349         (is_mve_encoding_conflict): Add cases for csinc, csinv,
1350         csneg and csel.
1351         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1352
1353 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1354
1355         * arm-dis.c (emun mve_instructions): Updated for new instructions.
1356         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1357         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1358         uqshl, urshrl and urshr.
1359         (is_mve_okay_in_it): Add new instructions to TRUE list.
1360         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1361         (print_insn_mve): Updated to accept new %j,
1362         %<bitfield>m and %<bitfield>n patterns.
1363
1364 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1365
1366         * mips-opc.c (mips_builtin_opcodes): Change source register
1367         constraint for DAUI.
1368
1369 2019-05-20  Nick Clifton  <nickc@redhat.com>
1370
1371         * po/fr.po: Updated French translation.
1372
1373 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1374             Michael Collison <michael.collison@arm.com>
1375
1376         * arm-dis.c (thumb32_opcodes): Add new instructions.
1377         (enum mve_instructions): Likewise.
1378         (enum mve_undefined): Add new reasons.
1379         (is_mve_encoding_conflict): Handle new instructions.
1380         (is_mve_undefined): Likewise.
1381         (is_mve_unpredictable): Likewise.
1382         (print_mve_undefined): Likewise.
1383         (print_mve_size): Likewise.
1384
1385 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1386             Michael Collison <michael.collison@arm.com>
1387
1388         * arm-dis.c (thumb32_opcodes): Add new instructions.
1389         (enum mve_instructions): Likewise.
1390         (is_mve_encoding_conflict): Handle new instructions.
1391         (is_mve_undefined): Likewise.
1392         (is_mve_unpredictable): Likewise.
1393         (print_mve_size): Likewise.
1394
1395 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1396             Michael Collison <michael.collison@arm.com>
1397
1398         * arm-dis.c (thumb32_opcodes): Add new instructions.
1399         (enum mve_instructions): Likewise.
1400         (is_mve_encoding_conflict): Likewise.
1401         (is_mve_unpredictable): Likewise.
1402         (print_mve_size): Likewise.
1403
1404 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1405             Michael Collison <michael.collison@arm.com>
1406
1407         * arm-dis.c (thumb32_opcodes): Add new instructions.
1408         (enum mve_instructions): Likewise.
1409         (is_mve_encoding_conflict): Handle new instructions.
1410         (is_mve_undefined): Likewise.
1411         (is_mve_unpredictable): Likewise.
1412         (print_mve_size): Likewise.
1413
1414 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1415             Michael Collison <michael.collison@arm.com>
1416
1417         * arm-dis.c (thumb32_opcodes): Add new instructions.
1418         (enum mve_instructions): Likewise.
1419         (is_mve_encoding_conflict): Handle new instructions.
1420         (is_mve_undefined): Likewise.
1421         (is_mve_unpredictable): Likewise.
1422         (print_mve_size): Likewise.
1423         (print_insn_mve): Likewise.
1424
1425 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1426             Michael Collison <michael.collison@arm.com>
1427
1428         * arm-dis.c (thumb32_opcodes): Add new instructions.
1429         (print_insn_thumb32): Handle new instructions.
1430
1431 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1432             Michael Collison <michael.collison@arm.com>
1433
1434         * arm-dis.c (enum mve_instructions): Add new instructions.
1435         (enum mve_undefined): Add new reasons.
1436         (is_mve_encoding_conflict): Handle new instructions.
1437         (is_mve_undefined): Likewise.
1438         (is_mve_unpredictable): Likewise.
1439         (print_mve_undefined): Likewise.
1440         (print_mve_size): Likewise.
1441         (print_mve_shift_n): Likewise.
1442         (print_insn_mve): Likewise.
1443
1444 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1445             Michael Collison <michael.collison@arm.com>
1446
1447         * arm-dis.c (enum mve_instructions): Add new instructions.
1448         (is_mve_encoding_conflict): Handle new instructions.
1449         (is_mve_unpredictable): Likewise.
1450         (print_mve_rotate): Likewise.
1451         (print_mve_size): Likewise.
1452         (print_insn_mve): Likewise.
1453
1454 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1455             Michael Collison <michael.collison@arm.com>
1456
1457         * arm-dis.c (enum mve_instructions): Add new instructions.
1458         (is_mve_encoding_conflict): Handle new instructions.
1459         (is_mve_unpredictable): Likewise.
1460         (print_mve_size): Likewise.
1461         (print_insn_mve): Likewise.
1462
1463 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1464             Michael Collison <michael.collison@arm.com>
1465
1466         * arm-dis.c (enum mve_instructions): Add new instructions.
1467         (enum mve_undefined): Add new reasons.
1468         (is_mve_encoding_conflict): Handle new instructions.
1469         (is_mve_undefined): Likewise.
1470         (is_mve_unpredictable): Likewise.
1471         (print_mve_undefined): Likewise.
1472         (print_mve_size): Likewise.
1473         (print_insn_mve): Likewise.
1474
1475 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1476             Michael Collison <michael.collison@arm.com>
1477
1478         * arm-dis.c (enum mve_instructions): Add new instructions.
1479         (is_mve_encoding_conflict): Handle new instructions.
1480         (is_mve_undefined): Likewise.
1481         (is_mve_unpredictable): Likewise.
1482         (print_mve_size): Likewise.
1483         (print_insn_mve): Likewise.
1484
1485 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1486             Michael Collison <michael.collison@arm.com>
1487
1488         * arm-dis.c (enum mve_instructions): Add new instructions.
1489         (enum mve_unpredictable): Add new reasons.
1490         (enum mve_undefined): Likewise.
1491         (is_mve_okay_in_it): Handle new isntructions.
1492         (is_mve_encoding_conflict): Likewise.
1493         (is_mve_undefined): Likewise.
1494         (is_mve_unpredictable): Likewise.
1495         (print_mve_vmov_index): Likewise.
1496         (print_simd_imm8): Likewise.
1497         (print_mve_undefined): Likewise.
1498         (print_mve_unpredictable): Likewise.
1499         (print_mve_size): Likewise.
1500         (print_insn_mve): Likewise.
1501
1502 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1503             Michael Collison <michael.collison@arm.com>
1504
1505         * arm-dis.c (enum mve_instructions): Add new instructions.
1506         (enum mve_unpredictable): Add new reasons.
1507         (enum mve_undefined): Likewise.
1508         (is_mve_encoding_conflict): Handle new instructions.
1509         (is_mve_undefined): Likewise.
1510         (is_mve_unpredictable): Likewise.
1511         (print_mve_undefined): Likewise.
1512         (print_mve_unpredictable): Likewise.
1513         (print_mve_rounding_mode): Likewise.
1514         (print_mve_vcvt_size): Likewise.
1515         (print_mve_size): Likewise.
1516         (print_insn_mve): Likewise.
1517
1518 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1519             Michael Collison <michael.collison@arm.com>
1520
1521         * arm-dis.c (enum mve_instructions): Add new instructions.
1522         (enum mve_unpredictable): Add new reasons.
1523         (enum mve_undefined): Likewise.
1524         (is_mve_undefined): Handle new instructions.
1525         (is_mve_unpredictable): Likewise.
1526         (print_mve_undefined): Likewise.
1527         (print_mve_unpredictable): Likewise.
1528         (print_mve_size): Likewise.
1529         (print_insn_mve): Likewise.
1530
1531 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1532             Michael Collison <michael.collison@arm.com>
1533
1534         * arm-dis.c (enum mve_instructions): Add new instructions.
1535         (enum mve_undefined): Add new reasons.
1536         (insns): Add new instructions.
1537         (is_mve_encoding_conflict):
1538         (print_mve_vld_str_addr): New print function.
1539         (is_mve_undefined): Handle new instructions.
1540         (is_mve_unpredictable): Likewise.
1541         (print_mve_undefined): Likewise.
1542         (print_mve_size): Likewise.
1543         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1544         (print_insn_mve):  Handle new operands.
1545
1546 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1547             Michael Collison <michael.collison@arm.com>
1548
1549         * arm-dis.c (enum mve_instructions): Add new instructions.
1550         (enum mve_unpredictable): Add new reasons.
1551         (is_mve_encoding_conflict): Handle new instructions.
1552         (is_mve_unpredictable): Likewise.
1553         (mve_opcodes): Add new instructions.
1554         (print_mve_unpredictable): Handle new reasons.
1555         (print_mve_register_blocks): New print function.
1556         (print_mve_size): Handle new instructions.
1557         (print_insn_mve): Likewise.
1558
1559 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1560             Michael Collison <michael.collison@arm.com>
1561
1562         * arm-dis.c (enum mve_instructions): Add new instructions.
1563         (enum mve_unpredictable): Add new reasons.
1564         (enum mve_undefined): Likewise.
1565         (is_mve_encoding_conflict): Handle new instructions.
1566         (is_mve_undefined): Likewise.
1567         (is_mve_unpredictable): Likewise.
1568         (coprocessor_opcodes): Move NEON VDUP from here...
1569         (neon_opcodes): ... to here.
1570         (mve_opcodes): Add new instructions.
1571         (print_mve_undefined):  Handle new reasons.
1572         (print_mve_unpredictable): Likewise.
1573         (print_mve_size): Handle new instructions.
1574         (print_insn_neon): Handle vdup.
1575         (print_insn_mve): Handle new operands.
1576
1577 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1578             Michael Collison <michael.collison@arm.com>
1579
1580         * arm-dis.c (enum mve_instructions): Add new instructions.
1581         (enum mve_unpredictable): Add new values.
1582         (mve_opcodes): Add new instructions.
1583         (vec_condnames): New array with vector conditions.
1584         (mve_predicatenames): New array with predicate suffixes.
1585         (mve_vec_sizename): New array with vector sizes.
1586         (enum vpt_pred_state): New enum with vector predication states.
1587         (struct vpt_block): New struct type for vpt blocks.
1588         (vpt_block_state): Global struct to keep track of state.
1589         (mve_extract_pred_mask): New helper function.
1590         (num_instructions_vpt_block): Likewise.
1591         (mark_outside_vpt_block): Likewise.
1592         (mark_inside_vpt_block): Likewise.
1593         (invert_next_predicate_state): Likewise.
1594         (update_next_predicate_state): Likewise.
1595         (update_vpt_block_state): Likewise.
1596         (is_vpt_instruction): Likewise.
1597         (is_mve_encoding_conflict): Add entries for new instructions.
1598         (is_mve_unpredictable): Likewise.
1599         (print_mve_unpredictable): Handle new cases.
1600         (print_instruction_predicate): Likewise.
1601         (print_mve_size): New function.
1602         (print_vec_condition): New function.
1603         (print_insn_mve): Handle vpt blocks and new print operands.
1604
1605 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1606
1607         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1608         8, 14 and 15 for Armv8.1-M Mainline.
1609
1610 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1611             Michael Collison <michael.collison@arm.com>
1612
1613         * arm-dis.c (enum mve_instructions): New enum.
1614         (enum mve_unpredictable): Likewise.
1615         (enum mve_undefined): Likewise.
1616         (struct mopcode32): New struct.
1617         (is_mve_okay_in_it): New function.
1618         (is_mve_architecture): Likewise.
1619         (arm_decode_field): Likewise.
1620         (arm_decode_field_multiple): Likewise.
1621         (is_mve_encoding_conflict): Likewise.
1622         (is_mve_undefined): Likewise.
1623         (is_mve_unpredictable): Likewise.
1624         (print_mve_undefined): Likewise.
1625         (print_mve_unpredictable): Likewise.
1626         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1627         (print_insn_mve): New function.
1628         (print_insn_thumb32): Handle MVE architecture.
1629         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1630
1631 2019-05-10  Nick Clifton  <nickc@redhat.com>
1632
1633         PR 24538
1634         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1635         end of the table prematurely.
1636
1637 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1638
1639         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1640         macros for R6.
1641
1642 2019-05-11  Alan Modra  <amodra@gmail.com>
1643
1644         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1645         when -Mraw is in effect.
1646
1647 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1648
1649         * aarch64-dis-2.c: Regenerate.
1650         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1651         (OP_SVE_BBB): New variant set.
1652         (OP_SVE_DDDD): New variant set.
1653         (OP_SVE_HHH): New variant set.
1654         (OP_SVE_HHHU): New variant set.
1655         (OP_SVE_SSS): New variant set.
1656         (OP_SVE_SSSU): New variant set.
1657         (OP_SVE_SHH): New variant set.
1658         (OP_SVE_SBBU): New variant set.
1659         (OP_SVE_DSS): New variant set.
1660         (OP_SVE_DHHU): New variant set.
1661         (OP_SVE_VMV_HSD_BHS): New variant set.
1662         (OP_SVE_VVU_HSD_BHS): New variant set.
1663         (OP_SVE_VVVU_SD_BH): New variant set.
1664         (OP_SVE_VVVU_BHSD): New variant set.
1665         (OP_SVE_VVV_QHD_DBS): New variant set.
1666         (OP_SVE_VVV_HSD_BHS): New variant set.
1667         (OP_SVE_VVV_HSD_BHS2): New variant set.
1668         (OP_SVE_VVV_BHS_HSD): New variant set.
1669         (OP_SVE_VV_BHS_HSD): New variant set.
1670         (OP_SVE_VVV_SD): New variant set.
1671         (OP_SVE_VVU_BHS_HSD): New variant set.
1672         (OP_SVE_VZVV_SD): New variant set.
1673         (OP_SVE_VZVV_BH): New variant set.
1674         (OP_SVE_VZV_SD): New variant set.
1675         (aarch64_opcode_table): Add sve2 instructions.
1676
1677 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1678
1679         * aarch64-asm-2.c: Regenerated.
1680         * aarch64-dis-2.c: Regenerated.
1681         * aarch64-opc-2.c: Regenerated.
1682         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1683         for SVE_SHLIMM_UNPRED_22.
1684         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1685         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1686         operand.
1687
1688 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1689
1690         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1691         sve_size_tsz_bhs iclass encode.
1692         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1693         sve_size_tsz_bhs iclass decode.
1694
1695 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1696
1697         * aarch64-asm-2.c: Regenerated.
1698         * aarch64-dis-2.c: Regenerated.
1699         * aarch64-opc-2.c: Regenerated.
1700         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1701         for SVE_Zm4_11_INDEX.
1702         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1703         (fields): Handle SVE_i2h field.
1704         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1705         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1706
1707 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1708
1709         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1710         sve_shift_tsz_bhsd iclass encode.
1711         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1712         sve_shift_tsz_bhsd iclass decode.
1713
1714 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1715
1716         * aarch64-asm-2.c: Regenerated.
1717         * aarch64-dis-2.c: Regenerated.
1718         * aarch64-opc-2.c: Regenerated.
1719         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1720         (aarch64_encode_variant_using_iclass): Handle
1721         sve_shift_tsz_hsd iclass encode.
1722         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1723         sve_shift_tsz_hsd iclass decode.
1724         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1725         for SVE_SHRIMM_UNPRED_22.
1726         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1727         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1728         operand.
1729
1730 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1731
1732         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1733         sve_size_013 iclass encode.
1734         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1735         sve_size_013 iclass decode.
1736
1737 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1738
1739         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1740         sve_size_bh iclass encode.
1741         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1742         sve_size_bh iclass decode.
1743
1744 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1745
1746         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1747         sve_size_sd2 iclass encode.
1748         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1749         sve_size_sd2 iclass decode.
1750         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1751         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1752
1753 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1754
1755         * aarch64-asm-2.c: Regenerated.
1756         * aarch64-dis-2.c: Regenerated.
1757         * aarch64-opc-2.c: Regenerated.
1758         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1759         for SVE_ADDR_ZX.
1760         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1761         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1762
1763 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1764
1765         * aarch64-asm-2.c: Regenerated.
1766         * aarch64-dis-2.c: Regenerated.
1767         * aarch64-opc-2.c: Regenerated.
1768         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1769         for SVE_Zm3_11_INDEX.
1770         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1771         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1772         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1773         fields.
1774         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1775
1776 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1777
1778         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1779         sve_size_hsd2 iclass encode.
1780         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1781         sve_size_hsd2 iclass decode.
1782         * aarch64-opc.c (fields): Handle SVE_size field.
1783         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1784
1785 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1786
1787         * aarch64-asm-2.c: Regenerated.
1788         * aarch64-dis-2.c: Regenerated.
1789         * aarch64-opc-2.c: Regenerated.
1790         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1791         for SVE_IMM_ROT3.
1792         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1793         (fields): Handle SVE_rot3 field.
1794         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1795         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1796
1797 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1798
1799         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1800         instructions.
1801
1802 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1803
1804         * aarch64-tbl.h
1805         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1806         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1807         aarch64_feature_sve2bitperm): New feature sets.
1808         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1809         for feature set addresses.
1810         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1811         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1812
1813 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1814             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1815
1816         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1817         argument and set ASE_EVA_R6 appropriately.
1818         (set_default_mips_dis_options): Pass ISA to above.
1819         (parse_mips_dis_option): Likewise.
1820         * mips-opc.c (EVAR6): New macro.
1821         (mips_builtin_opcodes): Add llwpe, scwpe.
1822
1823 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1824
1825         * aarch64-asm-2.c: Regenerated.
1826         * aarch64-dis-2.c: Regenerated.
1827         * aarch64-opc-2.c: Regenerated.
1828         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1829         AARCH64_OPND_TME_UIMM16.
1830         (aarch64_print_operand): Likewise.
1831         * aarch64-tbl.h (QL_IMM_NIL): New.
1832         (TME): New.
1833         (_TME_INSN): New.
1834         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1835
1836 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1837
1838         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1839
1840 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1841             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1842
1843         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1844
1845 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1846
1847         * s12z-opc.h: Add extern "C" bracketing to help
1848         users who wish to use this interface in c++ code.
1849
1850 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1851
1852         * s12z-opc.c (bm_decode): Handle bit map operations with the
1853         "reserved0" mode.
1854
1855 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1856
1857         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1858         specifier.  Add entries for VLDR and VSTR of system registers.
1859         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1860         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1861         of %J and %K format specifier.
1862
1863 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1864
1865         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1866         Add new entries for VSCCLRM instruction.
1867         (print_insn_coprocessor): Handle new %C format control code.
1868
1869 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1870
1871         * arm-dis.c (enum isa): New enum.
1872         (struct sopcode32): New structure.
1873         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1874         set isa field of all current entries to ANY.
1875         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1876         Only match an entry if its isa field allows the current mode.
1877
1878 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1879
1880         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1881         CLRM.
1882         (print_insn_thumb32): Add logic to print %n CLRM register list.
1883
1884 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1885
1886         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1887         and %Q patterns.
1888
1889 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1890
1891         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1892         (print_insn_thumb32): Edit the switch case for %Z.
1893
1894 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1895
1896         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1897
1898 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1899
1900         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1901
1902 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1903
1904         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1905
1906 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1907
1908         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1909         Arm register with r13 and r15 unpredictable.
1910         (thumb32_opcodes): New instructions for bfx and bflx.
1911
1912 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1913
1914         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1915
1916 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1917
1918         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1919
1920 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1921
1922         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1923
1924 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1925
1926         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1927
1928 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1929
1930         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1931         "optr". ("operator" is a reserved word in c++).
1932
1933 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1934
1935         * aarch64-opc.c (aarch64_print_operand): Add case for
1936         AARCH64_OPND_Rt_SP.
1937         (verify_constraints): Likewise.
1938         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1939         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1940         to accept Rt|SP as first operand.
1941         (AARCH64_OPERANDS): Add new Rt_SP.
1942         * aarch64-asm-2.c: Regenerated.
1943         * aarch64-dis-2.c: Regenerated.
1944         * aarch64-opc-2.c: Regenerated.
1945
1946 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1947
1948         * aarch64-asm-2.c: Regenerated.
1949         * aarch64-dis-2.c: Likewise.
1950         * aarch64-opc-2.c: Likewise.
1951         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1952
1953 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1954
1955         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1956
1957 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1958
1959         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1960         * i386-init.h: Regenerated.
1961
1962 2019-04-07  Alan Modra  <amodra@gmail.com>
1963
1964         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1965         op_separator to control printing of spaces, comma and parens
1966         rather than need_comma, need_paren and spaces vars.
1967
1968 2019-04-07  Alan Modra  <amodra@gmail.com>
1969
1970         PR 24421
1971         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1972         (print_insn_neon, print_insn_arm): Likewise.
1973
1974 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1975
1976         * i386-dis-evex.h (evex_table): Updated to support BF16
1977         instructions.
1978         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1979         and EVEX_W_0F3872_P_3.
1980         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1981         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1982         * i386-opc.h (enum): Add CpuAVX512_BF16.
1983         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1984         * i386-opc.tbl: Add AVX512 BF16 instructions.
1985         * i386-init.h: Regenerated.
1986         * i386-tbl.h: Likewise.
1987
1988 2019-04-05  Alan Modra  <amodra@gmail.com>
1989
1990         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1991         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1992         to favour printing of "-" branch hint when using the "y" bit.
1993         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1994
1995 2019-04-05  Alan Modra  <amodra@gmail.com>
1996
1997         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1998         opcode until first operand is output.
1999
2000 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
2001
2002         PR gas/24349
2003         * ppc-opc.c (valid_bo_pre_v2): Add comments.
2004         (valid_bo_post_v2): Add support for 'at' branch hints.
2005         (insert_bo): Only error on branch on ctr.
2006         (get_bo_hint_mask): New function.
2007         (insert_boe): Add new 'branch_taken' formal argument.  Add support
2008         for inserting 'at' branch hints.
2009         (extract_boe): Add new 'branch_taken' formal argument.  Add support
2010         for extracting 'at' branch hints.
2011         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
2012         (BOE): Delete operand.
2013         (BOM, BOP): New operands.
2014         (RM): Update value.
2015         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
2016         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
2017         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
2018         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
2019         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
2020         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
2021         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
2022         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
2023         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
2024         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
2025         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
2026         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
2027         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2028         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2029         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2030         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2031         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2032         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2033         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2034         bttarl+>: New extended mnemonics.
2035
2036 2019-03-28  Alan Modra  <amodra@gmail.com>
2037
2038         PR 24390
2039         * ppc-opc.c (BTF): Define.
2040         (powerpc_opcodes): Use for mtfsb*.
2041         * ppc-dis.c (print_insn_powerpc): Print fields with both
2042         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2043
2044 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2045
2046         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2047         (mapping_symbol_for_insn): Implement new algorithm.
2048         (print_insn): Remove duplicate code.
2049
2050 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2051
2052         * aarch64-dis.c (print_insn_aarch64):
2053         Implement override.
2054
2055 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2056
2057         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2058         order.
2059
2060 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2061
2062         * aarch64-dis.c (last_stop_offset): New.
2063         (print_insn_aarch64): Use stop_offset.
2064
2065 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
2066
2067         PR gas/24359
2068         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2069         CPU_ANY_AVX2_FLAGS.
2070         * i386-init.h: Regenerated.
2071
2072 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
2073
2074         PR gas/24348
2075         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2076         vmovdqu16, vmovdqu32 and vmovdqu64.
2077         * i386-tbl.h: Regenerated.
2078
2079 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2080
2081         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
2082         from vstrszb, vstrszh, and vstrszf.
2083
2084 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2085
2086         * s390-opc.txt: Add instruction descriptions.
2087
2088 2019-02-08  Jim Wilson  <jimw@sifive.com>
2089
2090         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2091         <bne>: Likewise.
2092
2093 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2094
2095         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2096
2097 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2098
2099         PR binutils/23212
2100         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2101         * aarch64-opc.c (verify_elem_sd): New.
2102         (fields): Add FLD_sz entr.
2103         * aarch64-tbl.h (_SIMD_INSN): New.
2104         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2105         fmulx scalar and vector by element isns.
2106
2107 2019-02-07  Nick Clifton  <nickc@redhat.com>
2108
2109         * po/sv.po: Updated Swedish translation.
2110
2111 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
2112
2113         * s390-mkopc.c (main): Accept arch13 as cpu string.
2114         * s390-opc.c: Add new instruction formats and instruction opcode
2115         masks.
2116         * s390-opc.txt: Add new arch13 instructions.
2117
2118 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2119
2120         * aarch64-tbl.h (QL_LDST_AT): Update macro.
2121         (aarch64_opcode): Change encoding for stg, stzg
2122         st2g and st2zg.
2123         * aarch64-asm-2.c: Regenerated.
2124         * aarch64-dis-2.c: Regenerated.
2125         * aarch64-opc-2.c: Regenerated.
2126
2127 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2128
2129         * aarch64-asm-2.c: Regenerated.
2130         * aarch64-dis-2.c: Likewise.
2131         * aarch64-opc-2.c: Likewise.
2132         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2133
2134 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2135             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
2136
2137         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2138         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2139         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2140         * aarch64-dis.h (ext_addr_simple_2): Likewise.
2141         * aarch64-opc.c (operand_general_constraint_met_p): Remove
2142         case for ldstgv_indexed.
2143         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2144         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2145         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2146         * aarch64-asm-2.c: Regenerated.
2147         * aarch64-dis-2.c: Regenerated.
2148         * aarch64-opc-2.c: Regenerated.
2149
2150 2019-01-23  Nick Clifton  <nickc@redhat.com>
2151
2152         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2153
2154 2019-01-21  Nick Clifton  <nickc@redhat.com>
2155
2156         * po/de.po: Updated German translation.
2157         * po/uk.po: Updated Ukranian translation.
2158
2159 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
2160         * mips-dis.c (mips_arch_choices): Fix typo in
2161         gs464, gs464e and gs264e descriptors.
2162
2163 2019-01-19  Nick Clifton  <nickc@redhat.com>
2164
2165         * configure: Regenerate.
2166         * po/opcodes.pot: Regenerate.
2167
2168 2018-06-24  Nick Clifton  <nickc@redhat.com>
2169
2170         2.32 branch created.
2171
2172 2019-01-09  John Darrington <john@darrington.wattle.id.au>
2173
2174         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
2175         if it is null.
2176         -dis.c (opr_emit_disassembly): Do not omit an index if it is
2177         zero.
2178
2179 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
2180
2181         * configure: Regenerate.
2182
2183 2019-01-07  Alan Modra  <amodra@gmail.com>
2184
2185         * configure: Regenerate.
2186         * po/POTFILES.in: Regenerate.
2187
2188 2019-01-03  John Darrington <john@darrington.wattle.id.au>
2189
2190         * s12z-opc.c: New file.
2191         * s12z-opc.h: New file.
2192         * s12z-dis.c: Removed all code not directly related to display
2193         of instructions.  Used the interface provided by the new files
2194         instead.
2195         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
2196         * Makefile.in: Regenerate.
2197         * configure.ac (bfd_s12z_arch): Correct the dependencies.
2198         * configure: Regenerate.
2199
2200 2019-01-01  Alan Modra  <amodra@gmail.com>
2201
2202         Update year range in copyright notice of all files.
2203
2204 For older changes see ChangeLog-2018
2205 \f
2206 Copyright (C) 2019 Free Software Foundation, Inc.
2207
2208 Copying and distribution of this file, with or without modification,
2209 are permitted in any medium without royalty provided the copyright
2210 notice and this notice are preserved.
2211
2212 Local Variables:
2213 mode: change-log
2214 left-margin: 8
2215 fill-column: 74
2216 version-control: never
2217 End: