opcodes/ChangeLog

   1 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
   2
   3         * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
   4         * aarch64-dis.c (print_operands): Refactor to take notes.
   5         (print_verifier_notes): New.
   6         (print_aarch64_insn): Apply constraint verifier.
   7         (print_insn_aarch64_word): Update call to print_aarch64_insn.
   8         * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
   9
  10 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
  11
  12         * aarch64-opc.c (init_insn_block): New.
  13         (verify_constraints, aarch64_is_destructive_by_operands): New.
  14         * aarch64-opc.h (verify_constraints): New.
  15
  16 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
  17
  18         * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
  19         * aarch64-opc.c (verify_ldpsw): Update arguments.
  20
  21 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
  22
  23         * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
  24         (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
  25
  26 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
  27
  28         * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
  29         * aarch64-dis.c (insn_sequence): New.
  30
  31 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
  32
  33         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
  34         _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
  35         _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
  36         V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
  37         constraints.
  38         (_SVE_INSNC): New.
  39         (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
  40         constraints.
  41         (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
  42         F_SCAN flags.
  43         (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
  44         sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
  45         sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
  46         sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
  47         uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
  48         uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
  49         C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
  50
  51 2018-10-02  Palmer Dabbelt  <palmer@sifive.com>
  52
  53         * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
  54
  55 2018-09-23  Sandra Loosemore  <sandra@codesourcery.com>
  56
  57         * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
  58         are used when extracting signed fields and converting them to
  59         potentially 64-bit types.
  60
  61 2018-09-21  Simon Marchi  <simon.marchi@ericsson.com>
  62
  63         * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
  64         * Makefile.in: Re-generate.
  65         * aclocal.m4: Re-generate.
  66         * configure: Re-generate.
  67         * configure.ac: Remove check for -Wno-missing-field-initializers.
  68         * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
  69         (csky_v2_opcodes): Likewise.
  70
  71 2018-09-20  Maciej W. Rozycki  <macro@linux-mips.org>
  72
  73         * arc-nps400-tbl.h: Append `ull' to large constants throughout.
  74
  75 2018-09-20  Nelson Chu <nelson.chu1990@gmail.com>
  76
  77         * nds32-asm.c (operand_fields): Remove the unused fields.
  78         (nds32_opcodes): Remove the unused instructions.
  79         * nds32-dis.c (nds32_ex9_info): Removed.
  80         (nds32_parse_opcode): Updated.
  81         (print_insn_nds32): Likewise.
  82         * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
  83         (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
  84         (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
  85         build_opcode_hash_table): New functions.
  86         (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
  87         nds32_opcode_table): New.
  88         (hw_ktabs): Declare it to a pointer rather than an array.
  89         (build_hash_table): Removed.
  90         * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
  91         SYN_ROPT and upadte HW_GPR and HW_INT.
  92         * nds32-dis.c (keywords): Remove const.
  93         (match_field): New function.
  94         (nds32_parse_opcode): Updated.
  95         * disassemble.c (disassemble_init_for_target):
  96         Add disassemble_init_nds32.
  97         * nds32-dis.c (eum map_type): New.
  98         (nds32_private_data): Likewise.
  99         (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
 100         nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
 101         (print_insn_nds32): Updated.
 102         * nds32-asm.c (parse_aext_reg): Add new parameter.
 103         (parse_re, parse_re2, parse_aext_reg): Only reduced registers
 104         are allowed to use.
 105         All callers changed.
 106         * nds32-asm.c (keyword_usr, keyword_sr): Updated.
 107         (operand_fields): Add new fields.
 108         (nds32_opcodes): Add new instructions.
 109         (keyword_aridxi_mx): New keyword.
 110         * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
 111         and NASM_ATTR_ZOL.
 112         (ALU2_1, ALU2_2, ALU2_3): New macros.
 113         * nds32-dis.c (nds32_filter_unknown_insn): Updated.
 114
 115 2018-09-17  Kito Cheng  <kito@andestech.com>
 116
 117         * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
 118
 119 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 120
 121         PR gas/23670
 122         * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
 123         EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
 124         (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
 125         (EVEX_LEN_0F7E_P_1): Likewise.
 126         (EVEX_LEN_0F7E_P_2): Likewise.
 127         (EVEX_LEN_0FD6_P_2): Likewise.
 128         * i386-dis.c (USE_EVEX_LEN_TABLE): New.
 129         (EVEX_LEN_TABLE): Likewise.
 130         (EVEX_LEN_0F6E_P_2): New enum.
 131         (EVEX_LEN_0F7E_P_1): Likewise.
 132         (EVEX_LEN_0F7E_P_2): Likewise.
 133         (EVEX_LEN_0FD6_P_2): Likewise.
 134         (evex_len_table): New.
 135         (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
 136         * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
 137         * i386-tbl.h: Regenerated.
 138
 139 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 140
 141         PR gas/23665
 142         * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
 143         VEX_LEN_0F7E_P_2 entries.
 144         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
 145         * i386-tbl.h: Regenerated.
 146
 147 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 148
 149         * i386-dis.c (VZERO_Fixup): Removed.
 150         (VZERO): Likewise.
 151         (VEX_LEN_0F10_P_1): Likewise.
 152         (VEX_LEN_0F10_P_3): Likewise.
 153         (VEX_LEN_0F11_P_1): Likewise.
 154         (VEX_LEN_0F11_P_3): Likewise.
 155         (VEX_LEN_0F2E_P_0): Likewise.
 156         (VEX_LEN_0F2E_P_2): Likewise.
 157         (VEX_LEN_0F2F_P_0): Likewise.
 158         (VEX_LEN_0F2F_P_2): Likewise.
 159         (VEX_LEN_0F51_P_1): Likewise.
 160         (VEX_LEN_0F51_P_3): Likewise.
 161         (VEX_LEN_0F52_P_1): Likewise.
 162         (VEX_LEN_0F53_P_1): Likewise.
 163         (VEX_LEN_0F58_P_1): Likewise.
 164         (VEX_LEN_0F58_P_3): Likewise.
 165         (VEX_LEN_0F59_P_1): Likewise.
 166         (VEX_LEN_0F59_P_3): Likewise.
 167         (VEX_LEN_0F5A_P_1): Likewise.
 168         (VEX_LEN_0F5A_P_3): Likewise.
 169         (VEX_LEN_0F5C_P_1): Likewise.
 170         (VEX_LEN_0F5C_P_3): Likewise.
 171         (VEX_LEN_0F5D_P_1): Likewise.
 172         (VEX_LEN_0F5D_P_3): Likewise.
 173         (VEX_LEN_0F5E_P_1): Likewise.
 174         (VEX_LEN_0F5E_P_3): Likewise.
 175         (VEX_LEN_0F5F_P_1): Likewise.
 176         (VEX_LEN_0F5F_P_3): Likewise.
 177         (VEX_LEN_0FC2_P_1): Likewise.
 178         (VEX_LEN_0FC2_P_3): Likewise.
 179         (VEX_LEN_0F3A0A_P_2): Likewise.
 180         (VEX_LEN_0F3A0B_P_2): Likewise.
 181         (VEX_W_0F10_P_0): Likewise.
 182         (VEX_W_0F10_P_1): Likewise.
 183         (VEX_W_0F10_P_2): Likewise.
 184         (VEX_W_0F10_P_3): Likewise.
 185         (VEX_W_0F11_P_0): Likewise.
 186         (VEX_W_0F11_P_1): Likewise.
 187         (VEX_W_0F11_P_2): Likewise.
 188         (VEX_W_0F11_P_3): Likewise.
 189         (VEX_W_0F12_P_0_M_0): Likewise.
 190         (VEX_W_0F12_P_0_M_1): Likewise.
 191         (VEX_W_0F12_P_1): Likewise.
 192         (VEX_W_0F12_P_2): Likewise.
 193         (VEX_W_0F12_P_3): Likewise.
 194         (VEX_W_0F13_M_0): Likewise.
 195         (VEX_W_0F14): Likewise.
 196         (VEX_W_0F15): Likewise.
 197         (VEX_W_0F16_P_0_M_0): Likewise.
 198         (VEX_W_0F16_P_0_M_1): Likewise.
 199         (VEX_W_0F16_P_1): Likewise.
 200         (VEX_W_0F16_P_2): Likewise.
 201         (VEX_W_0F17_M_0): Likewise.
 202         (VEX_W_0F28): Likewise.
 203         (VEX_W_0F29): Likewise.
 204         (VEX_W_0F2B_M_0): Likewise.
 205         (VEX_W_0F2E_P_0): Likewise.
 206         (VEX_W_0F2E_P_2): Likewise.
 207         (VEX_W_0F2F_P_0): Likewise.
 208         (VEX_W_0F2F_P_2): Likewise.
 209         (VEX_W_0F50_M_0): Likewise.
 210         (VEX_W_0F51_P_0): Likewise.
 211         (VEX_W_0F51_P_1): Likewise.
 212         (VEX_W_0F51_P_2): Likewise.
 213         (VEX_W_0F51_P_3): Likewise.
 214         (VEX_W_0F52_P_0): Likewise.
 215         (VEX_W_0F52_P_1): Likewise.
 216         (VEX_W_0F53_P_0): Likewise.
 217         (VEX_W_0F53_P_1): Likewise.
 218         (VEX_W_0F58_P_0): Likewise.
 219         (VEX_W_0F58_P_1): Likewise.
 220         (VEX_W_0F58_P_2): Likewise.
 221         (VEX_W_0F58_P_3): Likewise.
 222         (VEX_W_0F59_P_0): Likewise.
 223         (VEX_W_0F59_P_1): Likewise.
 224         (VEX_W_0F59_P_2): Likewise.
 225         (VEX_W_0F59_P_3): Likewise.
 226         (VEX_W_0F5A_P_0): Likewise.
 227         (VEX_W_0F5A_P_1): Likewise.
 228         (VEX_W_0F5A_P_3): Likewise.
 229         (VEX_W_0F5B_P_0): Likewise.
 230         (VEX_W_0F5B_P_1): Likewise.
 231         (VEX_W_0F5B_P_2): Likewise.
 232         (VEX_W_0F5C_P_0): Likewise.
 233         (VEX_W_0F5C_P_1): Likewise.
 234         (VEX_W_0F5C_P_2): Likewise.
 235         (VEX_W_0F5C_P_3): Likewise.
 236         (VEX_W_0F5D_P_0): Likewise.
 237         (VEX_W_0F5D_P_1): Likewise.
 238         (VEX_W_0F5D_P_2): Likewise.
 239         (VEX_W_0F5D_P_3): Likewise.
 240         (VEX_W_0F5E_P_0): Likewise.
 241         (VEX_W_0F5E_P_1): Likewise.
 242         (VEX_W_0F5E_P_2): Likewise.
 243         (VEX_W_0F5E_P_3): Likewise.
 244         (VEX_W_0F5F_P_0): Likewise.
 245         (VEX_W_0F5F_P_1): Likewise.
 246         (VEX_W_0F5F_P_2): Likewise.
 247         (VEX_W_0F5F_P_3): Likewise.
 248         (VEX_W_0F60_P_2): Likewise.
 249         (VEX_W_0F61_P_2): Likewise.
 250         (VEX_W_0F62_P_2): Likewise.
 251         (VEX_W_0F63_P_2): Likewise.
 252         (VEX_W_0F64_P_2): Likewise.
 253         (VEX_W_0F65_P_2): Likewise.
 254         (VEX_W_0F66_P_2): Likewise.
 255         (VEX_W_0F67_P_2): Likewise.
 256         (VEX_W_0F68_P_2): Likewise.
 257         (VEX_W_0F69_P_2): Likewise.
 258         (VEX_W_0F6A_P_2): Likewise.
 259         (VEX_W_0F6B_P_2): Likewise.
 260         (VEX_W_0F6C_P_2): Likewise.
 261         (VEX_W_0F6D_P_2): Likewise.
 262         (VEX_W_0F6F_P_1): Likewise.
 263         (VEX_W_0F6F_P_2): Likewise.
 264         (VEX_W_0F70_P_1): Likewise.
 265         (VEX_W_0F70_P_2): Likewise.
 266         (VEX_W_0F70_P_3): Likewise.
 267         (VEX_W_0F71_R_2_P_2): Likewise.
 268         (VEX_W_0F71_R_4_P_2): Likewise.
 269         (VEX_W_0F71_R_6_P_2): Likewise.
 270         (VEX_W_0F72_R_2_P_2): Likewise.
 271         (VEX_W_0F72_R_4_P_2): Likewise.
 272         (VEX_W_0F72_R_6_P_2): Likewise.
 273         (VEX_W_0F73_R_2_P_2): Likewise.
 274         (VEX_W_0F73_R_3_P_2): Likewise.
 275         (VEX_W_0F73_R_6_P_2): Likewise.
 276         (VEX_W_0F73_R_7_P_2): Likewise.
 277         (VEX_W_0F74_P_2): Likewise.
 278         (VEX_W_0F75_P_2): Likewise.
 279         (VEX_W_0F76_P_2): Likewise.
 280         (VEX_W_0F77_P_0): Likewise.
 281         (VEX_W_0F7C_P_2): Likewise.
 282         (VEX_W_0F7C_P_3): Likewise.
 283         (VEX_W_0F7D_P_2): Likewise.
 284         (VEX_W_0F7D_P_3): Likewise.
 285         (VEX_W_0F7E_P_1): Likewise.
 286         (VEX_W_0F7F_P_1): Likewise.
 287         (VEX_W_0F7F_P_2): Likewise.
 288         (VEX_W_0FAE_R_2_M_0): Likewise.
 289         (VEX_W_0FAE_R_3_M_0): Likewise.
 290         (VEX_W_0FC2_P_0): Likewise.
 291         (VEX_W_0FC2_P_1): Likewise.
 292         (VEX_W_0FC2_P_2): Likewise.
 293         (VEX_W_0FC2_P_3): Likewise.
 294         (VEX_W_0FD0_P_2): Likewise.
 295         (VEX_W_0FD0_P_3): Likewise.
 296         (VEX_W_0FD1_P_2): Likewise.
 297         (VEX_W_0FD2_P_2): Likewise.
 298         (VEX_W_0FD3_P_2): Likewise.
 299         (VEX_W_0FD4_P_2): Likewise.
 300         (VEX_W_0FD5_P_2): Likewise.
 301         (VEX_W_0FD6_P_2): Likewise.
 302         (VEX_W_0FD7_P_2_M_1): Likewise.
 303         (VEX_W_0FD8_P_2): Likewise.
 304         (VEX_W_0FD9_P_2): Likewise.
 305         (VEX_W_0FDA_P_2): Likewise.
 306         (VEX_W_0FDB_P_2): Likewise.
 307         (VEX_W_0FDC_P_2): Likewise.
 308         (VEX_W_0FDD_P_2): Likewise.
 309         (VEX_W_0FDE_P_2): Likewise.
 310         (VEX_W_0FDF_P_2): Likewise.
 311         (VEX_W_0FE0_P_2): Likewise.
 312         (VEX_W_0FE1_P_2): Likewise.
 313         (VEX_W_0FE2_P_2): Likewise.
 314         (VEX_W_0FE3_P_2): Likewise.
 315         (VEX_W_0FE4_P_2): Likewise.
 316         (VEX_W_0FE5_P_2): Likewise.
 317         (VEX_W_0FE6_P_1): Likewise.
 318         (VEX_W_0FE6_P_2): Likewise.
 319         (VEX_W_0FE6_P_3): Likewise.
 320         (VEX_W_0FE7_P_2_M_0): Likewise.
 321         (VEX_W_0FE8_P_2): Likewise.
 322         (VEX_W_0FE9_P_2): Likewise.
 323         (VEX_W_0FEA_P_2): Likewise.
 324         (VEX_W_0FEB_P_2): Likewise.
 325         (VEX_W_0FEC_P_2): Likewise.
 326         (VEX_W_0FED_P_2): Likewise.
 327         (VEX_W_0FEE_P_2): Likewise.
 328         (VEX_W_0FEF_P_2): Likewise.
 329         (VEX_W_0FF0_P_3_M_0): Likewise.
 330         (VEX_W_0FF1_P_2): Likewise.
 331         (VEX_W_0FF2_P_2): Likewise.
 332         (VEX_W_0FF3_P_2): Likewise.
 333         (VEX_W_0FF4_P_2): Likewise.
 334         (VEX_W_0FF5_P_2): Likewise.
 335         (VEX_W_0FF6_P_2): Likewise.
 336         (VEX_W_0FF7_P_2): Likewise.
 337         (VEX_W_0FF8_P_2): Likewise.
 338         (VEX_W_0FF9_P_2): Likewise.
 339         (VEX_W_0FFA_P_2): Likewise.
 340         (VEX_W_0FFB_P_2): Likewise.
 341         (VEX_W_0FFC_P_2): Likewise.
 342         (VEX_W_0FFD_P_2): Likewise.
 343         (VEX_W_0FFE_P_2): Likewise.
 344         (VEX_W_0F3800_P_2): Likewise.
 345         (VEX_W_0F3801_P_2): Likewise.
 346         (VEX_W_0F3802_P_2): Likewise.
 347         (VEX_W_0F3803_P_2): Likewise.
 348         (VEX_W_0F3804_P_2): Likewise.
 349         (VEX_W_0F3805_P_2): Likewise.
 350         (VEX_W_0F3806_P_2): Likewise.
 351         (VEX_W_0F3807_P_2): Likewise.
 352         (VEX_W_0F3808_P_2): Likewise.
 353         (VEX_W_0F3809_P_2): Likewise.
 354         (VEX_W_0F380A_P_2): Likewise.
 355         (VEX_W_0F380B_P_2): Likewise.
 356         (VEX_W_0F3817_P_2): Likewise.
 357         (VEX_W_0F381C_P_2): Likewise.
 358         (VEX_W_0F381D_P_2): Likewise.
 359         (VEX_W_0F381E_P_2): Likewise.
 360         (VEX_W_0F3820_P_2): Likewise.
 361         (VEX_W_0F3821_P_2): Likewise.
 362         (VEX_W_0F3822_P_2): Likewise.
 363         (VEX_W_0F3823_P_2): Likewise.
 364         (VEX_W_0F3824_P_2): Likewise.
 365         (VEX_W_0F3825_P_2): Likewise.
 366         (VEX_W_0F3828_P_2): Likewise.
 367         (VEX_W_0F3829_P_2): Likewise.
 368         (VEX_W_0F382A_P_2_M_0): Likewise.
 369         (VEX_W_0F382B_P_2): Likewise.
 370         (VEX_W_0F3830_P_2): Likewise.
 371         (VEX_W_0F3831_P_2): Likewise.
 372         (VEX_W_0F3832_P_2): Likewise.
 373         (VEX_W_0F3833_P_2): Likewise.
 374         (VEX_W_0F3834_P_2): Likewise.
 375         (VEX_W_0F3835_P_2): Likewise.
 376         (VEX_W_0F3837_P_2): Likewise.
 377         (VEX_W_0F3838_P_2): Likewise.
 378         (VEX_W_0F3839_P_2): Likewise.
 379         (VEX_W_0F383A_P_2): Likewise.
 380         (VEX_W_0F383B_P_2): Likewise.
 381         (VEX_W_0F383C_P_2): Likewise.
 382         (VEX_W_0F383D_P_2): Likewise.
 383         (VEX_W_0F383E_P_2): Likewise.
 384         (VEX_W_0F383F_P_2): Likewise.
 385         (VEX_W_0F3840_P_2): Likewise.
 386         (VEX_W_0F3841_P_2): Likewise.
 387         (VEX_W_0F38DB_P_2): Likewise.
 388         (VEX_W_0F3A08_P_2): Likewise.
 389         (VEX_W_0F3A09_P_2): Likewise.
 390         (VEX_W_0F3A0A_P_2): Likewise.
 391         (VEX_W_0F3A0B_P_2): Likewise.
 392         (VEX_W_0F3A0C_P_2): Likewise.
 393         (VEX_W_0F3A0D_P_2): Likewise.
 394         (VEX_W_0F3A0E_P_2): Likewise.
 395         (VEX_W_0F3A0F_P_2): Likewise.
 396         (VEX_W_0F3A21_P_2): Likewise.
 397         (VEX_W_0F3A40_P_2): Likewise.
 398         (VEX_W_0F3A41_P_2): Likewise.
 399         (VEX_W_0F3A42_P_2): Likewise.
 400         (VEX_W_0F3A62_P_2): Likewise.
 401         (VEX_W_0F3A63_P_2): Likewise.
 402         (VEX_W_0F3ADF_P_2): Likewise.
 403         (VEX_LEN_0F77_P_0): New.
 404         (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
 405         PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
 406         PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
 407         PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
 408         PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
 409         PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
 410         PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
 411         PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
 412         PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
 413         PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
 414         PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
 415         PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
 416         PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
 417         PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
 418         PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
 419         PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
 420         PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
 421         PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
 422         PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
 423         PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
 424         PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
 425         PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
 426         PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
 427         PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
 428         PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
 429         PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
 430         PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
 431         PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
 432         PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
 433         PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
 434         PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
 435         PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
 436         PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
 437         PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
 438         PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
 439         PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
 440         PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
 441         PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
 442         PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
 443         PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
 444         PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
 445         PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
 446         PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
 447         PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
 448         PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
 449         PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
 450         PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
 451         PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
 452         PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
 453         (vex_table): Update VEX 0F28 and 0F29 entries.
 454         (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
 455         VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
 456         VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
 457         VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
 458         VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
 459         VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
 460         VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
 461         VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
 462         VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
 463         VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
 464         VEX_LEN_0F3A0B_P_2 entries.
 465         (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
 466         VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
 467         VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
 468         VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
 469         VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
 470         VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
 471         VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
 472         VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
 473         VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
 474         VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
 475         VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
 476         VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
 477         VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
 478         VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
 479         VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
 480         VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
 481         VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
 482         VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
 483         VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
 484         VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
 485         VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
 486         VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
 487         VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
 488         VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
 489         VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
 490         VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
 491         VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
 492         VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
 493         VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
 494         VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
 495         VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
 496         VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
 497         VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
 498         VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
 499         VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
 500         VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
 501         VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
 502         VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
 503         VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
 504         VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
 505         VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
 506         VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
 507         VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
 508         VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
 509         VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
 510         VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
 511         VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
 512         VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
 513         VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
 514         VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
 515         VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
 516         VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
 517         VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
 518         VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
 519         VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
 520         VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
 521         VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
 522         VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
 523         VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
 524         VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
 525         VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
 526         VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
 527         VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
 528         VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
 529         VEX_W_0F3ADF_P_2 entries.
 530         (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
 531         MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
 532         MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
 533
 534 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 535
 536         * i386-opc.tbl (VexWIG): New.
 537         Replace VexW=3 with VexWIG.
 538
 539 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 540
 541         * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
 542         * i386-tbl.h: Regenerated.
 543
 544 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 545
 546         PR gas/23665
 547         * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
 548         VEX_LEN_0FD6_P_2 entries.
 549         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
 550         * i386-tbl.h: Regenerated.
 551
 552 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 553
 554         PR gas/23642
 555         * i386-opc.h (VEXWIG): New.
 556         * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
 557         * i386-tbl.h: Regenerated.
 558
 559 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 560
 561         PR binutils/23655
 562         * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
 563         vcvtsi2sd%LQ and vcvtusi2sd%LQ.
 564         * i386-dis.c (EXxEVexR64): New.
 565         (evex_rounding_64_mode): Likewise.
 566         (OP_Rounding): Handle evex_rounding_64_mode.
 567
 568 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 569
 570         PR binutils/23655
 571         * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
 572         vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
 573         * i386-dis.c (Edqa): New.
 574         (dqa_mode): Likewise.
 575         (intel_operand_size): Handle dqa_mode as m_mode.
 576         (OP_E_register): Handle dqa_mode as dq_mode.
 577         (OP_E_memory): Set shift for dqa_mode based on address_mode.
 578
 579 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 580
 581         * i386-dis.c (OP_E_memory): Reformat.
 582
 583 2018-09-14  Jan Beulich  <jbeulich@suse.com>
 584
 585         * i386-opc.tbl (crc32): Fold byte and word forms.
 586         * i386-tbl.h: Re-generate.
 587
 588 2018-09-13  H.J. Lu  <hongjiu.lu@intel.com>
 589
 590         * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
 591         pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
 592         Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
 593         vpinsrq.  Remove VexW=1 from WIG VEX movq and vmovq.
 594         * i386-tbl.h: Regenerated.
 595
 596 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 597
 598         * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
 599         meaningless.
 600         (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
 601         xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
 602         rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
 603         * i386-tbl.h: Re-generate.
 604
 605 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 606
 607         * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
 608         AVX512_4VNNIW insns.
 609         * i386-tbl.h: Re-generate.
 610
 611 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 612
 613         * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
 614         meaningless.
 615         * i386-tbl.h: Re-generate.
 616
 617 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 618
 619         * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
 620         meaningless.
 621         * i386-tbl.h: Re-generate.
 622
 623 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 624
 625         * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
 626         meaningless.
 627         * i386-tbl.h: Re-generate.
 628
 629 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 630
 631         * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
 632         meaningless.
 633         * i386-tbl.h: Re-generate.
 634
 635 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 636
 637         * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
 638         meaningless.
 639         * i386-tbl.h: Re-generate.
 640
 641 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 642
 643         * i386-opc.tbl: Drop IgnoreSize from SHA insns.
 644         * i386-tbl.h: Re-generate.
 645
 646 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 647
 648         * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
 649         * i386-tbl.h: Re-generate.
 650
 651 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 652
 653         * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
 654         meaningless.
 655         * i386-tbl.h: Re-generate.
 656
 657 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 658
 659         * i386-opc.tbl: Drop IgnoreSize from AVX insns where
 660         meaningless.
 661         * i386-tbl.h: Re-generate.
 662
 663 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 664
 665         * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
 666         * i386-tbl.h: Re-generate.
 667
 668 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 669
 670         * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
 671         * i386-tbl.h: Re-generate.
 672
 673 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 674
 675         * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
 676         * i386-tbl.h: Re-generate.
 677
 678 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 679
 680         * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
 681         meaningless.
 682         * i386-tbl.h: Re-generate.
 683
 684 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 685
 686         * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
 687         meaningless.
 688         * i386-tbl.h: Re-generate.
 689
 690 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 691
 692         * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
 693         meaningless.
 694         * i386-tbl.h: Re-generate.
 695
 696 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 697
 698         * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
 699         * i386-tbl.h: Re-generate.
 700
 701 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 702
 703         * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
 704         * i386-tbl.h: Re-generate.
 705
 706 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 707
 708         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
 709         * i386-tbl.h: Re-generate.
 710
 711 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 712
 713         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
 714         (vpbroadcastw, rdpid): Drop NoRex64.
 715         * i386-tbl.h: Re-generate.
 716
 717 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 718
 719         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
 720         store templates, adding D.
 721         * i386-tbl.h: Re-generate.
 722
 723 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 724
 725         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
 726         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
 727         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
 728         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
 729         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
 730         Fold load and store templates where possible, adding D. Drop
 731         IgnoreSize where it was pointlessly present. Drop redundant
 732         *word.
 733         * i386-tbl.h: Re-generate.
 734
 735 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 736
 737         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
 738         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
 739         (intel_operand_size): Handle v_bndmk_mode.
 740         (OP_E_memory): Likewise. Produce (bad) when also riprel.
 741
 742 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
 743
 744         * disassemble.c (ARCH_s12z): Define if ARCH_all.
 745
 746 2018-08-31  Kito Cheng  <kito@andestech.com>
 747
 748         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
 749         compressed floating point instructions.
 750
 751 2018-08-30  Kito Cheng  <kito@andestech.com>
 752
 753         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
 754         riscv_opcode.xlen_requirement.
 755         * riscv-opc.c (riscv_opcodes): Update for struct change.
 756
 757 2018-08-29  Martin Aberg  <maberg@gaisler.com>
 758
 759         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
 760         psr (PWRPSR) instruction.
 761
 762 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 763
 764         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
 765
 766 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 767
 768         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
 769
 770 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 771
 772         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
 773         loongson3a as an alias of gs464 for compatibility.
 774         * mips-opc.c (mips_opcodes): Change Comments.
 775
 776 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 777
 778         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
 779         option.
 780         (print_mips_disassembler_options): Document -M loongson-ext.
 781         * mips-opc.c (LEXT2): New macro.
 782         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
 783
 784 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 785
 786          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
 787          descriptors.
 788          (parse_mips_ase_option): Handle -M loongson-ext option.
 789          (print_mips_disassembler_options): Document -M loongson-ext.
 790          * mips-opc.c (IL3A): Delete.
 791          * mips-opc.c (LEXT): New macro.
 792          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
 793          instructions.
 794
 795 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 796
 797         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
 798         descriptors.
 799         (parse_mips_ase_option): Handle -M loongson-cam option.
 800         (print_mips_disassembler_options): Document -M loongson-cam.
 801         * mips-opc.c (LCAM): New macro.
 802         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
 803         instructions.
 804
 805 2018-08-21  Alan Modra  <amodra@gmail.com>
 806
 807         * ppc-dis.c (operand_value_powerpc): Init "invalid".
 808         (skip_optional_operands): Count optional operands, and update
 809         ppc_optional_operand_value call.
 810         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
 811         (extract_vlensi): Likewise.
 812         (extract_fxm): Return default value for missing optional operand.
 813         (extract_ls, extract_raq, extract_tbr): Likewise.
 814         (insert_sxl, extract_sxl): New functions.
 815         (insert_esync, extract_esync): Remove Power9 handling and simplify.
 816         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
 817         flag and extra entry.
 818         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
 819         extract_sxl.
 820
 821 2018-08-20  Alan Modra  <amodra@gmail.com>
 822
 823         * sh-opc.h (MASK): Simplify.
 824
 825 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 826
 827         * s12z-dis.c (bm_decode): Deal with cases where the mode is
 828         BM_RESERVED0 or BM_RESERVED1
 829         (bm_rel_decode, bm_n_bytes): Ditto.
 830
 831 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 832
 833         * s12z.h: Delete.
 834
 835 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
 836
 837         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
 838         address with the addr32 prefix and without base nor index
 839         registers.
 840
 841 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
 842
 843         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
 844         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
 845         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
 846         (cpu_flags): Add CpuCMOV and CpuFXSR.
 847         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
 848         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
 849         * i386-init.h: Regenerated.
 850         * i386-tbl.h: Likewise.
 851
 852 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
 853
 854         * arc-regs.h: Update auxiliary registers.
 855
 856 2018-08-06  Jan Beulich  <jbeulich@suse.com>
 857
 858         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
 859         (RegIP, RegIZ): Define.
 860         * i386-reg.tbl: Adjust comments.
 861         (rip): Use Qword instead of BaseIndex. Use RegIP.
 862         (eip): Use Dword instead of BaseIndex. Use RegIP.
 863         (riz): Add Qword. Use RegIZ.
 864         (eiz): Add Dword. Use RegIZ.
 865         * i386-tbl.h: Re-generate.
 866
 867 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 868
 869         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
 870         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
 871         vpmovzxdq, vpmovzxwd): Remove NoRex64.
 872         * i386-tbl.h: Re-generate.
 873
 874 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 875
 876         * i386-gen.c (operand_types): Remove Mem field.
 877         * i386-opc.h (union i386_operand_type): Remove mem field.
 878         * i386-init.h, i386-tbl.h: Re-generate.
 879
 880 2018-08-01  Alan Modra  <amodra@gmail.com>
 881
 882         * po/POTFILES.in: Regenerate.
 883
 884 2018-07-31  Nick Clifton  <nickc@redhat.com>
 885
 886         * po/sv.po: Updated Swedish translation.
 887
 888 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 889
 890         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
 891         * i386-init.h, i386-tbl.h: Re-generate.
 892
 893 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 894
 895         * i386-opc.h (ZEROING_MASKING) Rename to ...
 896         (DYNAMIC_MASKING): ... this. Adjust comment.
 897         * i386-opc.tbl (MaskingMorZ): Define.
 898         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
 899         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
 900         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
 901         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
 902         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
 903         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
 904         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
 905         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
 906         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
 907
 908 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 909
 910         * i386-opc.tbl: Use element rather than vector size for AVX512*
 911         scatter/gather insns.
 912         * i386-tbl.h: Re-generate.
 913
 914 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 915
 916         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
 917         (cpu_flags): Drop CpuVREX.
 918         * i386-opc.h (CpuVREX): Delete.
 919         (union i386_cpu_flags): Remove cpuvrex.
 920         * i386-init.h, i386-tbl.h: Re-generate.
 921
 922 2018-07-30  Jim Wilson  <jimw@sifive.com>
 923
 924         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
 925         fields.
 926         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
 927
 928 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
 929
 930         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
 931         * Makefile.in: Regenerated.
 932         * configure.ac: Add C-SKY.
 933         * configure: Regenerated.
 934         * csky-dis.c: New file.
 935         * csky-opc.h: New file.
 936         * disassemble.c (ARCH_csky): Define.
 937         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
 938         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
 939
 940 2018-07-27  Alan Modra  <amodra@gmail.com>
 941
 942         * ppc-opc.c (insert_sprbat): Correct function parameter and
 943         return type.
 944         (extract_sprbat): Likewise, variable too.
 945
 946 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
 947             Alan Modra  <amodra@gmail.com>
 948
 949         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
 950         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
 951         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
 952         support disjointed BAT.
 953         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
 954         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
 955         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
 956
 957 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
 958             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 959
 960         * i386-gen.c (adjust_broadcast_modifier): New function.
 961         (process_i386_opcode_modifier): Add an argument for operands.
 962         Adjust the Broadcast value based on operands.
 963         (output_i386_opcode): Pass operand_types to
 964         process_i386_opcode_modifier.
 965         (process_i386_opcodes): Pass NULL as operands to
 966         process_i386_opcode_modifier.
 967         * i386-opc.h (BYTE_BROADCAST): New.
 968         (WORD_BROADCAST): Likewise.
 969         (DWORD_BROADCAST): Likewise.
 970         (QWORD_BROADCAST): Likewise.
 971         (i386_opcode_modifier): Expand broadcast to 3 bits.
 972         * i386-tbl.h: Regenerated.
 973
 974 2018-07-24  Alan Modra  <amodra@gmail.com>
 975
 976         PR 23430
 977         * or1k-desc.h: Regenerate.
 978
 979 2018-07-24  Jan Beulich  <jbeulich@suse.com>
 980
 981         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
 982         vcvtusi2ss, and vcvtusi2sd.
 983         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
 984         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
 985         * i386-tbl.h: Re-generate.
 986
 987 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 988
 989         * arc-opc.c (extract_w6): Fix extending the sign.
 990
 991 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
 992
 993         * arc-tbl.h (vewt): Allow it for ARC EM family.
 994
 995 2018-07-23  Alan Modra  <amodra@gmail.com>
 996
 997         PR 23419
 998         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
 999         opcode variants for mtspr/mfspr encodings.
1000
1001 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1002             Maciej W. Rozycki  <macro@mips.com>
1003
1004         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1005         loongson3a descriptors.
1006         (parse_mips_ase_option): Handle -M loongson-mmi option.
1007         (print_mips_disassembler_options): Document -M loongson-mmi.
1008         * mips-opc.c (LMMI): New macro.
1009         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1010         instructions.
1011
1012 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1013
1014         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1015         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1016         IgnoreSize and [XYZ]MMword where applicable.
1017         * i386-tbl.h: Re-generate.
1018
1019 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1020
1021         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1022         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1023         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1024         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1025         * i386-tbl.h: Re-generate.
1026
1027 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1028
1029         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1030         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1031         VPCLMULQDQ templates into their respective AVX512VL counterparts
1032         where possible, using Disp8ShiftVL and CheckRegSize instead of
1033         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1034         * i386-tbl.h: Re-generate.
1035
1036 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1037
1038         * i386-opc.tbl: Fold AVX512DQ templates into their respective
1039         AVX512VL counterparts where possible, using Disp8ShiftVL and
1040         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1041         IgnoreSize) as appropriate.
1042         * i386-tbl.h: Re-generate.
1043
1044 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1045
1046         * i386-opc.tbl: Fold AVX512BW templates into their respective
1047         AVX512VL counterparts where possible, using Disp8ShiftVL and
1048         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1049         IgnoreSize) as appropriate.
1050         * i386-tbl.h: Re-generate.
1051
1052 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1053
1054         * i386-opc.tbl: Fold AVX512CD templates into their respective
1055         AVX512VL counterparts where possible, using Disp8ShiftVL and
1056         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1057         IgnoreSize) as appropriate.
1058         * i386-tbl.h: Re-generate.
1059
1060 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1061
1062         * i386-opc.h (DISP8_SHIFT_VL): New.
1063         * i386-opc.tbl (Disp8ShiftVL):  Define.
1064         (various): Fold AVX512VL templates into their respective
1065         AVX512F counterparts where possible, using Disp8ShiftVL and
1066         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1067         IgnoreSize) as appropriate.
1068         * i386-tbl.h: Re-generate.
1069
1070 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1071
1072         * Makefile.am: Change dependencies and rule for
1073         $(srcdir)/i386-init.h.
1074         * Makefile.in: Re-generate.
1075         * i386-gen.c (process_i386_opcodes): New local variable
1076         "marker". Drop opening of input file. Recognize marker and line
1077         number directives.
1078         * i386-opc.tbl (OPCODE_I386_H): Define.
1079         (i386-opc.h): Include it.
1080         (None): Undefine.
1081
1082 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
1083
1084         PR gas/23418
1085         * i386-opc.h (Byte): Update comments.
1086         (Word): Likewise.
1087         (Dword): Likewise.
1088         (Fword): Likewise.
1089         (Qword): Likewise.
1090         (Tbyte): Likewise.
1091         (Xmmword): Likewise.
1092         (Ymmword): Likewise.
1093         (Zmmword): Likewise.
1094         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1095         vcvttps2uqq.
1096         * i386-tbl.h: Regenerated.
1097
1098 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
1099
1100         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1101         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1102         * aarch64-asm-2.c: Regenerate.
1103         * aarch64-dis-2.c: Regenerate.
1104         * aarch64-opc-2.c: Regenerate.
1105
1106 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
1107
1108         PR binutils/23192
1109         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1110         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1111         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1112         sqdmulh, sqrdmulh): Use Em16.
1113
1114 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
1115
1116         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1117         csdb together with them.
1118         (thumb32_opcodes): Likewise.
1119
1120 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1121
1122         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1123         requiring 32-bit registers as operands 2 and 3. Improve
1124         comments.
1125         (mwait, mwaitx): Fold templates. Improve comments.
1126         OPERAND_TYPE_INOUTPORTREG.
1127         * i386-tbl.h: Re-generate.
1128
1129 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1130
1131         * i386-gen.c (operand_type_init): Remove
1132         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1133         OPERAND_TYPE_INOUTPORTREG.
1134         * i386-init.h: Re-generate.
1135
1136 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1137
1138         * i386-opc.tbl (wrssd, wrussd): Add Dword.
1139         (wrssq, wrussq): Add Qword.
1140         * i386-tbl.h: Re-generate.
1141
1142 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1143
1144         * i386-opc.h: Rename OTMax to OTNum.
1145         (OTNumOfUints): Adjust calculation.
1146         (OTUnused): Directly alias to OTNum.
1147
1148 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
1149
1150         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1151         `reg_xys'.
1152         (lea_reg_xys): Likewise.
1153         (print_insn_loop_primitive): Rename `reg' local variable to
1154         `reg_dxy'.
1155
1156 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1157
1158         PR binutils/23242
1159         * aarch64-tbl.h (ldarh): Fix disassembly mask.
1160
1161 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1162
1163         PR binutils/23369
1164         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1165         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1166
1167 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
1168
1169         PR tdep/8282
1170         * mips-dis.c (mips_option_arg_t): New enumeration.
1171         (mips_options): New variable.
1172         (disassembler_options_mips): New function.
1173         (print_mips_disassembler_options): Reimplement in terms of
1174         `disassembler_options_mips'.
1175         * arm-dis.c (disassembler_options_arm): Adapt to using the
1176         `disasm_options_and_args_t' structure.
1177         * ppc-dis.c (disassembler_options_powerpc): Likewise.
1178         * s390-dis.c (disassembler_options_s390): Likewise.
1179
1180 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1181
1182         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1183         expected result.
1184         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1185         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1186         * testsuite/ld-arm/tls-longplt.d: Likewise.
1187
1188 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
1189
1190         PR binutils/23192
1191         * aarch64-asm-2.c: Regenerate.
1192         * aarch64-dis-2.c: Likewise.
1193         * aarch64-opc-2.c: Likewise.
1194         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1195         * aarch64-opc.c (operand_general_constraint_met_p,
1196         aarch64_print_operand): Likewise.
1197         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1198         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1199         fmlal2, fmlsl2.
1200         (AARCH64_OPERANDS): Add Em2.
1201
1202 2018-06-26  Nick Clifton  <nickc@redhat.com>
1203
1204         * po/uk.po: Updated Ukranian translation.
1205         * po/de.po: Updated German translation.
1206         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1207
1208 2018-06-26  Nick Clifton  <nickc@redhat.com>
1209
1210         * nfp-dis.c: Fix spelling mistake.
1211
1212 2018-06-24  Nick Clifton  <nickc@redhat.com>
1213
1214         * configure: Regenerate.
1215         * po/opcodes.pot: Regenerate.
1216
1217 2018-06-24  Nick Clifton  <nickc@redhat.com>
1218
1219         2.31 branch created.
1220
1221 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
1222
1223         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1224         * aarch64-asm-2.c: Regenerate.
1225         * aarch64-dis-2.c: Likewise.
1226
1227 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
1228
1229         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1230         `-M ginv' option description.
1231
1232 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
1233
1234         PR gas/23305
1235         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1236         la and lla.
1237
1238 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
1239
1240         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1241         * configure.ac: Remove AC_PREREQ.
1242         * Makefile.in: Re-generate.
1243         * aclocal.m4: Re-generate.
1244         * configure: Re-generate.
1245
1246 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1247
1248         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1249         mips64r6 descriptors.
1250         (parse_mips_ase_option): Handle -Mginv option.
1251         (print_mips_disassembler_options): Document -Mginv.
1252         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1253         (GINV): New macro.
1254         (mips_opcodes): Define ginvi and ginvt.
1255
1256 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
1257             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1258
1259         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1260         * mips-opc.c (CRC, CRC64): New macros.
1261         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1262         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
1263         crc32cd for CRC64.
1264
1265 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
1266
1267         PR 20319
1268         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1269         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1270
1271 2018-06-06  Alan Modra  <amodra@gmail.com>
1272
1273         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1274         setjmp.  Move init for some other vars later too.
1275
1276 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
1277
1278         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1279         (dis_private): Add new fields for property section tracking.
1280         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1281         (xtensa_instruction_fits): New functions.
1282         (fetch_data): Bump minimal fetch size to 4.
1283         (print_insn_xtensa): Make struct dis_private static.
1284         Load and prepare property table on section change.
1285         Don't disassemble literals. Don't disassemble instructions that
1286         cross property table boundaries.
1287
1288 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
1289
1290         * configure: Regenerated.
1291
1292 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1293
1294         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1295         * i386-tbl.h: Re-generate.
1296
1297 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1298
1299         * i386-opc.tbl (sldt, str): Add NoRex64.
1300         * i386-tbl.h: Re-generate.
1301
1302 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1303
1304         * i386-opc.tbl (invpcid): Add Oword.
1305         * i386-tbl.h: Re-generate.
1306
1307 2018-06-01  Alan Modra  <amodra@gmail.com>
1308
1309         * sysdep.h (_bfd_error_handler): Don't declare.
1310         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
1311         * rl78-decode.opc: Likewise.
1312         * msp430-decode.c: Regenerate.
1313         * rl78-decode.c: Regenerate.
1314
1315 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
1316
1317         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1318         * i386-init.h : Regenerated.
1319
1320 2018-05-25  Alan Modra  <amodra@gmail.com>
1321
1322         * Makefile.in: Regenerate.
1323         * po/POTFILES.in: Regenerate.
1324
1325 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
1326
1327         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1328         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1329         (insert_bab, extract_bab, insert_btab, extract_btab,
1330         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1331         (BAT, BBA VBA RBS XB6S): Delete macros.
1332         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1333         (BB, BD, RBX, XC6): Update for new macros.
1334         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1335         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1336         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1337         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1338
1339 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
1340
1341         * Makefile.am: Add support for s12z architecture.
1342         * configure.ac: Likewise.
1343         * disassemble.c: Likewise.
1344         * disassemble.h: Likewise.
1345         * Makefile.in: Regenerate.
1346         * configure: Regenerate.
1347         * s12z-dis.c: New file.
1348         * s12z.h: New file.
1349
1350 2018-05-18  Alan Modra  <amodra@gmail.com>
1351
1352         * nfp-dis.c: Don't #include libbfd.h.
1353         (init_nfp3200_priv): Use bfd_get_section_contents.
1354         (nit_nfp6000_mecsr_sec): Likewise.
1355
1356 2018-05-17  Nick Clifton  <nickc@redhat.com>
1357
1358         * po/zh_CN.po: Updated simplified Chinese translation.
1359
1360 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
1361
1362         PR binutils/23109
1363         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1364         * aarch64-dis-2.c: Regenerate.
1365
1366 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1367
1368         PR binutils/21446
1369         * aarch64-asm.c (opintl.h): Include.
1370         (aarch64_ins_sysreg): Enforce read/write constraints.
1371         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1372         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1373         (F_REG_READ, F_REG_WRITE): New.
1374         * aarch64-opc.c (aarch64_print_operand): Generate notes for
1375         AARCH64_OPND_SYSREG.
1376         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1377         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1378         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1379         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1380         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1381         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1382         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1383         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1384         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1385         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1386         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1387         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1388         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1389         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1390         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1391         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1392         msr (F_SYS_WRITE), mrs (F_SYS_READ).
1393
1394 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1395
1396         PR binutils/21446
1397         * aarch64-dis.c (no_notes: New.
1398         (parse_aarch64_dis_option): Support notes.
1399         (aarch64_decode_insn, print_operands): Likewise.
1400         (print_aarch64_disassembler_options): Document notes.
1401         * aarch64-opc.c (aarch64_print_operand): Support notes.
1402
1403 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1404
1405         PR binutils/21446
1406         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1407         and take error struct.
1408         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1409         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1410         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1411         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1412         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1413         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1414         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1415         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1416         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1417         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1418         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1419         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1420         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1421         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1422         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1423         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1424         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1425         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1426         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1427         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1428         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1429         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1430         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1431         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1432         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1433         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1434         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1435         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1436         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1437         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1438         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1439         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1440         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1441         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1442         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1443         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1444         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1445         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1446         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1447         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1448         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1449         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1450         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1451         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1452         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1453         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1454         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1455         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1456         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1457         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1458         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1459         (determine_disassembling_preference, aarch64_decode_insn,
1460         print_insn_aarch64_word, print_insn_data): Take errors struct.
1461         (print_insn_aarch64): Use errors.
1462         * aarch64-asm-2.c: Regenerate.
1463         * aarch64-dis-2.c: Regenerate.
1464         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1465         boolean in aarch64_insert_operan.
1466         (print_operand_extractor): Likewise.
1467         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1468
1469 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
1470
1471         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1472
1473 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
1474
1475         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1476
1477 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
1478
1479         * cr16-opc.c (cr16_instruction): Comment typo fix.
1480         * hppa-dis.c (print_insn_hppa): Likewise.
1481
1482 2018-05-08  Jim Wilson  <jimw@sifive.com>
1483
1484         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1485         (match_c_slli64, match_srxi_as_c_srxi): New.
1486         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1487         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1488         <c.slli, c.srli, c.srai>: Use match_s_slli.
1489         <c.slli64, c.srli64, c.srai64>: New.
1490
1491 2018-05-08  Alan Modra  <amodra@gmail.com>
1492
1493         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1494         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1495         partition opcode space for index lookup.
1496
1497 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1498
1499         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1500         <insn_length>: ...with this.  Update usage.
1501         Remove duplicate call to *info->memory_error_func.
1502
1503 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1504             H.J. Lu  <hongjiu.lu@intel.com>
1505
1506         * i386-dis.c (Gva): New.
1507         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1508         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1509         (prefix_table): New instructions (see prefix above).
1510         (mod_table): New instructions (see prefix above).
1511         (OP_G): Handle va_mode.
1512         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1513         CPU_MOVDIR64B_FLAGS.
1514         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1515         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1516         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1517         * i386-opc.tbl: Add movidir{i,64b}.
1518         * i386-init.h: Regenerated.
1519         * i386-tbl.h: Likewise.
1520
1521 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
1522
1523         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1524         AddrPrefixOpReg.
1525         * i386-opc.h (AddrPrefixOp0): Renamed to ...
1526         (AddrPrefixOpReg): This.
1527         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1528         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1529
1530 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1531
1532         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1533         (vle_num_opcodes): Likewise.
1534         (spe2_num_opcodes): Likewise.
1535         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1536         initialization loop.
1537         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1538         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
1539         only once.
1540
1541 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
1542
1543         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1544
1545 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
1546
1547         Makefile.am: Added nfp-dis.c.
1548         configure.ac: Added bfd_nfp_arch.
1549         disassemble.h: Added print_insn_nfp prototype.
1550         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1551         nfp-dis.c: New, for NFP support.
1552         po/POTFILES.in: Added nfp-dis.c to the list.
1553         Makefile.in: Regenerate.
1554         configure: Regenerate.
1555
1556 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1557
1558         * i386-opc.tbl: Fold various non-memory operand AVX512VL
1559         templates into their base ones.
1560         * i386-tlb.h: Re-generate.
1561
1562 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1563
1564         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1565         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1566         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1567         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1568         * i386-init.h: Re-generate.
1569
1570 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1571
1572         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1573         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1574         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1575         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1576         comment.
1577         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1578         and CpuRegMask.
1579         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1580         CpuRegMask: Delete.
1581         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1582         cpuregzmm, and cpuregmask.
1583         * i386-init.h: Re-generate.
1584         * i386-tbl.h: Re-generate.
1585
1586 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1587
1588         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1589         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1590         * i386-init.h: Re-generate.
1591
1592 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1593
1594         * i386-gen.c (VexImmExt): Delete.
1595         * i386-opc.h (VexImmExt, veximmext): Delete.
1596         * i386-opc.tbl: Drop all VexImmExt uses.
1597         * i386-tlb.h: Re-generate.
1598
1599 2018-04-25  Jan Beulich  <jbeulich@suse.com>
1600
1601         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1602         register-only forms.
1603         * i386-tlb.h: Re-generate.
1604
1605 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
1606
1607         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1608
1609 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1610
1611         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1612         PREFIX_0F1C.
1613         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1614         (cpu_flags): Add CpuCLDEMOTE.
1615         * i386-init.h: Regenerate.
1616         * i386-opc.h (enum): Add CpuCLDEMOTE,
1617         (i386_cpu_flags): Add cpucldemote.
1618         * i386-opc.tbl: Add cldemote.
1619         * i386-tbl.h: Regenerate.
1620
1621 2018-04-16  Alan Modra  <amodra@gmail.com>
1622
1623         * Makefile.am: Remove sh5 and sh64 support.
1624         * configure.ac: Likewise.
1625         * disassemble.c: Likewise.
1626         * disassemble.h: Likewise.
1627         * sh-dis.c: Likewise.
1628         * sh64-dis.c: Delete.
1629         * sh64-opc.c: Delete.
1630         * sh64-opc.h: Delete.
1631         * Makefile.in: Regenerate.
1632         * configure: Regenerate.
1633         * po/POTFILES.in: Regenerate.
1634
1635 2018-04-16  Alan Modra  <amodra@gmail.com>
1636
1637         * Makefile.am: Remove w65 support.
1638         * configure.ac: Likewise.
1639         * disassemble.c: Likewise.
1640         * disassemble.h: Likewise.
1641         * w65-dis.c: Delete.
1642         * w65-opc.h: Delete.
1643         * Makefile.in: Regenerate.
1644         * configure: Regenerate.
1645         * po/POTFILES.in: Regenerate.
1646
1647 2018-04-16  Alan Modra  <amodra@gmail.com>
1648
1649         * configure.ac: Remove we32k support.
1650         * configure: Regenerate.
1651
1652 2018-04-16  Alan Modra  <amodra@gmail.com>
1653
1654         * Makefile.am: Remove m88k support.
1655         * configure.ac: Likewise.
1656         * disassemble.c: Likewise.
1657         * disassemble.h: Likewise.
1658         * m88k-dis.c: Delete.
1659         * Makefile.in: Regenerate.
1660         * configure: Regenerate.
1661         * po/POTFILES.in: Regenerate.
1662
1663 2018-04-16  Alan Modra  <amodra@gmail.com>
1664
1665         * Makefile.am: Remove i370 support.
1666         * configure.ac: Likewise.
1667         * disassemble.c: Likewise.
1668         * disassemble.h: Likewise.
1669         * i370-dis.c: Delete.
1670         * i370-opc.c: Delete.
1671         * Makefile.in: Regenerate.
1672         * configure: Regenerate.
1673         * po/POTFILES.in: Regenerate.
1674
1675 2018-04-16  Alan Modra  <amodra@gmail.com>
1676
1677         * Makefile.am: Remove h8500 support.
1678         * configure.ac: Likewise.
1679         * disassemble.c: Likewise.
1680         * disassemble.h: Likewise.
1681         * h8500-dis.c: Delete.
1682         * h8500-opc.h: Delete.
1683         * Makefile.in: Regenerate.
1684         * configure: Regenerate.
1685         * po/POTFILES.in: Regenerate.
1686
1687 2018-04-16  Alan Modra  <amodra@gmail.com>
1688
1689         * configure.ac: Remove tahoe support.
1690         * configure: Regenerate.
1691
1692 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1693
1694         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1695         umwait.
1696         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1697         64-bit mode.
1698         * i386-tbl.h: Regenerated.
1699
1700 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1701
1702         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1703         PREFIX_MOD_1_0FAE_REG_6.
1704         (va_mode): New.
1705         (OP_E_register): Use va_mode.
1706         * i386-dis-evex.h (prefix_table):
1707         New instructions (see prefixes above).
1708         * i386-gen.c (cpu_flag_init): Add WAITPKG.
1709         (cpu_flags): Likewise.
1710         * i386-opc.h (enum): Likewise.
1711         (i386_cpu_flags): Likewise.
1712         * i386-opc.tbl: Add umonitor, umwait, tpause.
1713         * i386-init.h: Regenerate.
1714         * i386-tbl.h: Likewise.
1715
1716 2018-04-11  Alan Modra  <amodra@gmail.com>
1717
1718         * opcodes/i860-dis.c: Delete.
1719         * opcodes/i960-dis.c: Delete.
1720         * Makefile.am: Remove i860 and i960 support.
1721         * configure.ac: Likewise.
1722         * disassemble.c: Likewise.
1723         * disassemble.h: Likewise.
1724         * Makefile.in: Regenerate.
1725         * configure: Regenerate.
1726         * po/POTFILES.in: Regenerate.
1727
1728 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
1729
1730         PR binutils/23025
1731         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1732         to 0.
1733         (print_insn): Clear vex instead of vex.evex.
1734
1735 2018-04-04  Nick Clifton  <nickc@redhat.com>
1736
1737         * po/es.po: Updated Spanish translation.
1738
1739 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1740
1741         * i386-gen.c (opcode_modifiers): Delete VecESize.
1742         * i386-opc.h (VecESize): Delete.
1743         (struct i386_opcode_modifier): Delete vecesize.
1744         * i386-opc.tbl: Drop VecESize.
1745         * i386-tlb.h: Re-generate.
1746
1747 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1748
1749         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1750         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1751         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1752         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1753         * i386-tlb.h: Re-generate.
1754
1755 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1756
1757         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1758         Fold AVX512 forms
1759         * i386-tlb.h: Re-generate.
1760
1761 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1762
1763         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1764         (vex_len_table): Drop Y for vcvt*2si.
1765         (putop): Replace plain 'Y' handling by abort().
1766
1767 2018-03-28  Nick Clifton  <nickc@redhat.com>
1768
1769         PR 22988
1770         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1771         instructions with only a base address register.
1772         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1773         handle AARHC64_OPND_SVE_ADDR_R.
1774         (aarch64_print_operand): Likewise.
1775         * aarch64-asm-2.c: Regenerate.
1776         * aarch64_dis-2.c: Regenerate.
1777         * aarch64-opc-2.c: Regenerate.
1778
1779 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1780
1781         * i386-opc.tbl: Drop VecESize from register only insn forms and
1782         memory forms not allowing broadcast.
1783         * i386-tlb.h: Re-generate.
1784
1785 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1786
1787         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1788         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1789         sha256*): Drop Disp<N>.
1790
1791 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1792
1793         * i386-dis.c (EbndS, bnd_swap_mode): New.
1794         (prefix_table): Use EbndS.
1795         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1796         * i386-opc.tbl (bndmov): Move misplaced Load.
1797         * i386-tlb.h: Re-generate.
1798
1799 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1800
1801         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1802         templates allowing memory operands and folded ones for register
1803         only flavors.
1804         * i386-tlb.h: Re-generate.
1805
1806 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1807
1808         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1809         256-bit templates. Drop redundant leftover Disp<N>.
1810         * i386-tlb.h: Re-generate.
1811
1812 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
1813
1814         * riscv-opc.c (riscv_insn_types): New.
1815
1816 2018-03-13  Nick Clifton  <nickc@redhat.com>
1817
1818         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1819
1820 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1821
1822         * i386-opc.tbl: Add Optimize to clr.
1823         * i386-tbl.h: Regenerated.
1824
1825 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1826
1827         * i386-gen.c (opcode_modifiers): Remove OldGcc.
1828         * i386-opc.h (OldGcc): Removed.
1829         (i386_opcode_modifier): Remove oldgcc.
1830         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1831         instructions for old (<= 2.8.1) versions of gcc.
1832         * i386-tbl.h: Regenerated.
1833
1834 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1835
1836         * i386-opc.h (EVEXDYN): New.
1837         * i386-opc.tbl: Fold various AVX512VL templates.
1838         * i386-tlb.h: Re-generate.
1839
1840 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1841
1842         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1843         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1844         vpexpandd, vpexpandq): Fold AFX512VF templates.
1845         * i386-tlb.h: Re-generate.
1846
1847 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1848
1849         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1850         Fold 128- and 256-bit VEX-encoded templates.
1851         * i386-tlb.h: Re-generate.
1852
1853 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1854
1855         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1856         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1857         vpexpandd, vpexpandq): Fold AVX512F templates.
1858         * i386-tlb.h: Re-generate.
1859
1860 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1861
1862         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1863         64-bit templates. Drop Disp<N>.
1864         * i386-tlb.h: Re-generate.
1865
1866 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1867
1868         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1869         and 256-bit templates.
1870         * i386-tlb.h: Re-generate.
1871
1872 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1873
1874         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1875         * i386-tlb.h: Re-generate.
1876
1877 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1878
1879         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1880         Drop NoAVX.
1881         * i386-tlb.h: Re-generate.
1882
1883 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1884
1885         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1886         * i386-tlb.h: Re-generate.
1887
1888 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1889
1890         * i386-gen.c (opcode_modifiers): Delete FloatD.
1891         * i386-opc.h (FloatD): Delete.
1892         (struct i386_opcode_modifier): Delete floatd.
1893         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1894         FloatD by D.
1895         * i386-tlb.h: Re-generate.
1896
1897 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1898
1899         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1900
1901 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1902
1903         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1904         * i386-tlb.h: Re-generate.
1905
1906 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1907
1908         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1909         forms.
1910         * i386-tlb.h: Re-generate.
1911
1912 2018-03-07  Alan Modra  <amodra@gmail.com>
1913
1914         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1915         bfd_arch_rs6000.
1916         * disassemble.h (print_insn_rs6000): Delete.
1917         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1918         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1919         (print_insn_rs6000): Delete.
1920
1921 2018-03-03  Alan Modra  <amodra@gmail.com>
1922
1923         * sysdep.h (opcodes_error_handler): Define.
1924         (_bfd_error_handler): Declare.
1925         * Makefile.am: Remove stray #.
1926         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
1927         EDIT" comment.
1928         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1929         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1930         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1931         opcodes_error_handler to print errors.  Standardize error messages.
1932         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1933         and include opintl.h.
1934         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1935         * i386-gen.c: Standardize error messages.
1936         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1937         * Makefile.in: Regenerate.
1938         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1939         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1940         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1941         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1942         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1943         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1944         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1945         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1946         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1947         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1948         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1949         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1950         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1951
1952 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1953
1954         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1955         vpsub[bwdq] instructions.
1956         * i386-tbl.h: Regenerated.
1957
1958 2018-03-01  Alan Modra  <amodra@gmail.com>
1959
1960         * configure.ac (ALL_LINGUAS): Sort.
1961         * configure: Regenerate.
1962
1963 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1964
1965         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1966         macro by assignements.
1967
1968 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
1969
1970         PR gas/22871
1971         * i386-gen.c (opcode_modifiers): Add Optimize.
1972         * i386-opc.h (Optimize): New enum.
1973         (i386_opcode_modifier): Add optimize.
1974         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1975         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1976         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1977         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1978         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1979         vpxord and vpxorq.
1980         * i386-tbl.h: Regenerated.
1981
1982 2018-02-26  Alan Modra  <amodra@gmail.com>
1983
1984         * crx-dis.c (getregliststring): Allocate a large enough buffer
1985         to silence false positive gcc8 warning.
1986
1987 2018-02-22  Shea Levy <shea@shealevy.com>
1988
1989         * disassemble.c (ARCH_riscv): Define if ARCH_all.
1990
1991 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
1992
1993         * i386-opc.tbl: Add {rex},
1994         * i386-tbl.h: Regenerated.
1995
1996 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
1997
1998         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1999         (mips16_opcodes): Replace `M' with `m' for "restore".
2000
2001 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2002
2003         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2004
2005 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
2006
2007         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2008         variable to `function_index'.
2009
2010 2018-02-13  Nick Clifton  <nickc@redhat.com>
2011
2012         PR 22823
2013         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2014         about truncation of printing.
2015
2016 2018-02-12  Henry Wong <henry@stuffedcow.net>
2017
2018         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2019
2020 2018-02-05  Nick Clifton  <nickc@redhat.com>
2021
2022         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2023
2024 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2025
2026         * i386-dis.c (enum): Add pconfig.
2027         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2028         (cpu_flags): Add CpuPCONFIG.
2029         * i386-opc.h (enum): Add CpuPCONFIG.
2030         (i386_cpu_flags): Add cpupconfig.
2031         * i386-opc.tbl: Add PCONFIG instruction.
2032         * i386-init.h: Regenerate.
2033         * i386-tbl.h: Likewise.
2034
2035 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2036
2037         * i386-dis.c (enum): Add PREFIX_0F09.
2038         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2039         (cpu_flags): Add CpuWBNOINVD.
2040         * i386-opc.h (enum): Add CpuWBNOINVD.
2041         (i386_cpu_flags): Add cpuwbnoinvd.
2042         * i386-opc.tbl: Add WBNOINVD instruction.
2043         * i386-init.h: Regenerate.
2044         * i386-tbl.h: Likewise.
2045
2046 2018-01-17  Jim Wilson  <jimw@sifive.com>
2047
2048         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2049
2050 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2051
2052         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2053         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2054         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2055         (cpu_flags): Add CpuIBT, CpuSHSTK.
2056         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2057         (i386_cpu_flags): Add cpuibt, cpushstk.
2058         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2059         * i386-init.h: Regenerate.
2060         * i386-tbl.h: Likewise.
2061
2062 2018-01-16  Nick Clifton  <nickc@redhat.com>
2063
2064         * po/pt_BR.po: Updated Brazilian Portugese translation.
2065         * po/de.po: Updated German translation.
2066
2067 2018-01-15  Jim Wilson  <jimw@sifive.com>
2068
2069         * riscv-opc.c (match_c_nop): New.
2070         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2071
2072 2018-01-15  Nick Clifton  <nickc@redhat.com>
2073
2074         * po/uk.po: Updated Ukranian translation.
2075
2076 2018-01-13  Nick Clifton  <nickc@redhat.com>
2077
2078         * po/opcodes.pot: Regenerated.
2079
2080 2018-01-13  Nick Clifton  <nickc@redhat.com>
2081
2082         * configure: Regenerate.
2083
2084 2018-01-13  Nick Clifton  <nickc@redhat.com>
2085
2086         2.30 branch created.
2087
2088 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2089
2090         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2091         * i386-tbl.h: Regenerate.
2092
2093 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2094
2095         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2096         * i386-tbl.h: Re-generate.
2097
2098 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2099
2100         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2101         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2102         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2103         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2104         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2105         Disp8MemShift of AVX512VL forms.
2106         * i386-tbl.h: Re-generate.
2107
2108 2018-01-09  Jim Wilson  <jimw@sifive.com>
2109
2110         * riscv-dis.c (maybe_print_address): If base_reg is zero,
2111         then the hi_addr value is zero.
2112
2113 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2114
2115         * arm-dis.c (arm_opcodes): Add csdb.
2116         (thumb32_opcodes): Add csdb.
2117
2118 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2119
2120         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2121         * aarch64-asm-2.c: Regenerate.
2122         * aarch64-dis-2.c: Regenerate.
2123         * aarch64-opc-2.c: Regenerate.
2124
2125 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
2126
2127         PR gas/22681
2128         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2129         Remove AVX512 vmovd with 64-bit operands.
2130         * i386-tbl.h: Regenerated.
2131
2132 2018-01-05  Jim Wilson  <jimw@sifive.com>
2133
2134         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2135         jalr.
2136
2137 2018-01-03  Alan Modra  <amodra@gmail.com>
2138
2139         Update year range in copyright notice of all files.
2140
2141 2018-01-02  Jan Beulich  <jbeulich@suse.com>
2142
2143         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2144         and OPERAND_TYPE_REGZMM entries.
2145
2146 For older changes see ChangeLog-2017
2147 \f
2148 Copyright (C) 2018 Free Software Foundation, Inc.
2149
2150 Copying and distribution of this file, with or without modification,
2151 are permitted in any medium without royalty provided the copyright
2152 notice and this notice are preserved.
2153
2154 Local Variables:
2155 mode: change-log
2156 left-margin: 8
2157 fill-column: 74
2158 version-control: never
2159 End: