opcodes/ChangeLog

   1 2020-03-06  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-dis.c (OP_E_memory): Exclude recording of used address
   4         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
   5         addressed memory operands for MPX insns.
   6
   7 2020-03-06  Jan Beulich  <jbeulich@suse.com>
   8
   9         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
  10         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
  11         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
  12         (ptwrite): Split into non-64-bit and 64-bit forms.
  13         * i386-tbl.h: Re-generate.
  14
  15 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  16
  17         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
  18         template.
  19         * i386-tbl.h: Re-generate.
  20
  21 2020-03-04  Jan Beulich  <jbeulich@suse.com>
  22
  23         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
  24         (prefix_table): Move vmmcall here. Add vmgexit.
  25         (rm_table): Replace vmmcall entry by prefix_table[] escape.
  26         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
  27         (cpu_flags): Add CpuSEV_ES entry.
  28         * i386-opc.h (CpuSEV_ES): New.
  29         (union i386_cpu_flags): Add cpusev_es field.
  30         * i386-opc.tbl (vmgexit): New.
  31         * i386-init.h, i386-tbl.h: Re-generate.
  32
  33 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
  34
  35         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
  36         with MnemonicSize.
  37         * i386-opc.h (IGNORESIZE): New.
  38         (DEFAULTSIZE): Likewise.
  39         (IgnoreSize): Removed.
  40         (DefaultSize): Likewise.
  41         (MnemonicSize): New.
  42         (i386_opcode_modifier): Replace ignoresize/defaultsize with
  43         mnemonicsize.
  44         * i386-opc.tbl (IgnoreSize): New.
  45         (DefaultSize): Likewise.
  46         * i386-tbl.h: Regenerated.
  47
  48 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
  49
  50         PR 25627
  51         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
  52         instructions.
  53
  54 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
  55
  56         PR gas/25622
  57         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
  58         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
  59         * i386-tbl.h: Regenerated.
  60
  61 2020-02-26  Alan Modra  <amodra@gmail.com>
  62
  63         * aarch64-asm.c: Indent labels correctly.
  64         * aarch64-dis.c: Likewise.
  65         * aarch64-gen.c: Likewise.
  66         * aarch64-opc.c: Likewise.
  67         * alpha-dis.c: Likewise.
  68         * i386-dis.c: Likewise.
  69         * nds32-asm.c: Likewise.
  70         * nfp-dis.c: Likewise.
  71         * visium-dis.c: Likewise.
  72
  73 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
  74
  75         * arc-regs.h (int_vector_base): Make it available for all ARC
  76         CPUs.
  77
  78 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
  79
  80         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
  81         changed.
  82
  83 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
  84
  85         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
  86         c.mv/c.li if rs1 is zero.
  87
  88 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
  89
  90         * i386-gen.c (cpu_flag_init): Replace CpuABM with
  91         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
  92         CPU_POPCNT_FLAGS.
  93         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
  94         * i386-opc.h (CpuABM): Removed.
  95         (CpuPOPCNT): New.
  96         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
  97         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
  98         popcnt.  Remove CpuABM from lzcnt.
  99         * i386-init.h: Regenerated.
 100         * i386-tbl.h: Likewise.
 101
 102 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 103
 104         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 105         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 106         VexW1 instead of open-coding them.
 107         * i386-tbl.h: Re-generate.
 108
 109 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 110
 111         * i386-opc.tbl (AddrPrefixOpReg): Define.
 112         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 113         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 114         templates. Drop NoRex64.
 115         * i386-tbl.h: Re-generate.
 116
 117 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 118
 119         PR gas/6518
 120         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 121         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 122         into Intel syntax instance (with Unpsecified) and AT&T one
 123         (without).
 124         (vcvtneps2bf16): Likewise, along with folding the two so far
 125         separate ones.
 126         * i386-tbl.h: Re-generate.
 127
 128 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 129
 130         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 131         CPU_ANY_SSE4A_FLAGS.
 132
 133 2020-02-17  Alan Modra  <amodra@gmail.com>
 134
 135         * i386-gen.c (cpu_flag_init): Correct last change.
 136
 137 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 138
 139         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 140         CPU_ANY_SSE4_FLAGS.
 141
 142 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 143
 144         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 145         (movzx): Likewise.
 146
 147 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 148
 149         PR gas/25438
 150         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 151         destination for Cpu64-only variant.
 152         (movzx): Fold patterns.
 153         * i386-tbl.h: Re-generate.
 154
 155 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 156
 157         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 158         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 159         CPU_ANY_SSE4_FLAGS entry.
 160         * i386-init.h: Re-generate.
 161
 162 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 163
 164         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 165         with Unspecified, making the present one AT&T syntax only.
 166         * i386-tbl.h: Re-generate.
 167
 168 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 169
 170         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 171         * i386-tbl.h: Re-generate.
 172
 173 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 174
 175         PR gas/24546
 176         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 177         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 178         Amd64 and Intel64 templates.
 179         (call, jmp): Likewise for far indirect variants. Dro
 180         Unspecified.
 181         * i386-tbl.h: Re-generate.
 182
 183 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 184
 185         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 186         * i386-opc.h (ShortForm): Delete.
 187         (struct i386_opcode_modifier): Remove shortform field.
 188         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 189         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 190         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 191         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 192         Drop ShortForm.
 193         * i386-tbl.h: Re-generate.
 194
 195 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 196
 197         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 198         fucompi): Drop ShortForm from operand-less templates.
 199         * i386-tbl.h: Re-generate.
 200
 201 2020-02-11  Alan Modra  <amodra@gmail.com>
 202
 203         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 204         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 205         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 206         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 207         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 208
 209 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 210
 211         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 212         (cde_opcodes): Add VCX* instructions.
 213
 214 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 215             Matthew Malcomson  <matthew.malcomson@arm.com>
 216
 217         * arm-dis.c (struct cdeopcode32): New.
 218         (CDE_OPCODE): New macro.
 219         (cde_opcodes): New disassembly table.
 220         (regnames): New option to table.
 221         (cde_coprocs): New global variable.
 222         (print_insn_cde): New
 223         (print_insn_thumb32): Use print_insn_cde.
 224         (parse_arm_disassembler_options): Parse coprocN args.
 225
 226 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 227
 228         PR gas/25516
 229         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 230         with ISA64.
 231         * i386-opc.h (AMD64): Removed.
 232         (Intel64): Likewose.
 233         (AMD64): New.
 234         (INTEL64): Likewise.
 235         (INTEL64ONLY): Likewise.
 236         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 237         * i386-opc.tbl (Amd64): New.
 238         (Intel64): Likewise.
 239         (Intel64Only): Likewise.
 240         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 241         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 242         * i386-tbl.h: Regenerated.
 243
 244 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 245
 246         PR 25469
 247         * z80-dis.c: Add support for GBZ80 opcodes.
 248
 249 2020-02-04  Alan Modra  <amodra@gmail.com>
 250
 251         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 252
 253 2020-02-03  Alan Modra  <amodra@gmail.com>
 254
 255         * m32c-ibld.c: Regenerate.
 256
 257 2020-02-01  Alan Modra  <amodra@gmail.com>
 258
 259         * frv-ibld.c: Regenerate.
 260
 261 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 262
 263         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 264         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 265         (OP_E_memory): Replace xmm_mdq_mode case label by
 266         vex_scalar_w_dq_mode one.
 267         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 268
 269 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 270
 271         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 272         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 273         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 274         (intel_operand_size): Drop vex_w_dq_mode case label.
 275
 276 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 277
 278         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 279         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 280
 281 2020-01-30  Alan Modra  <amodra@gmail.com>
 282
 283         * m32c-ibld.c: Regenerate.
 284
 285 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 286
 287         * bpf-opc.c: Regenerate.
 288
 289 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 290
 291         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 292         (dis386): Use them to replace C2/C3 table entries.
 293         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 294         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 295         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 296         * i386-tbl.h: Re-generate.
 297
 298 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 299
 300         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 301         forms.
 302         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 303         DefaultSize.
 304         * i386-tbl.h: Re-generate.
 305
 306 2020-01-30  Alan Modra  <amodra@gmail.com>
 307
 308         * tic4x-dis.c (tic4x_dp): Make unsigned.
 309
 310 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 311             Jan Beulich  <jbeulich@suse.com>
 312
 313         PR binutils/25445
 314         * i386-dis.c (MOVSXD_Fixup): New function.
 315         (movsxd_mode): New enum.
 316         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 317         (intel_operand_size): Handle movsxd_mode.
 318         (OP_E_register): Likewise.
 319         (OP_G): Likewise.
 320         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 321         register on movsxd.  Add movsxd with 16-bit destination register
 322         for AMD64 and Intel64 ISAs.
 323         * i386-tbl.h: Regenerated.
 324
 325 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 326
 327         PR 25403
 328         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 329         * aarch64-asm-2.c: Regenerate
 330         * aarch64-dis-2.c: Likewise.
 331         * aarch64-opc-2.c: Likewise.
 332
 333 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 334
 335         * i386-opc.tbl (sysret): Drop DefaultSize.
 336         * i386-tbl.h: Re-generate.
 337
 338 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 339
 340         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 341         Dword.
 342         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 343         * i386-tbl.h: Re-generate.
 344
 345 2020-01-20  Nick Clifton  <nickc@redhat.com>
 346
 347         * po/de.po: Updated German translation.
 348         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 349         * po/uk.po: Updated Ukranian translation.
 350
 351 2020-01-20  Alan Modra  <amodra@gmail.com>
 352
 353         * hppa-dis.c (fput_const): Remove useless cast.
 354
 355 2020-01-20  Alan Modra  <amodra@gmail.com>
 356
 357         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 358
 359 2020-01-18  Nick Clifton  <nickc@redhat.com>
 360
 361         * configure: Regenerate.
 362         * po/opcodes.pot: Regenerate.
 363
 364 2020-01-18  Nick Clifton  <nickc@redhat.com>
 365
 366         Binutils 2.34 branch created.
 367
 368 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 369
 370         * opintl.h: Fix spelling error (seperate).
 371
 372 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 373
 374         * i386-opc.tbl: Add {vex} pseudo prefix.
 375         * i386-tbl.h: Regenerated.
 376
 377 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 378
 379         PR 25376
 380         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 381         (neon_opcodes): Likewise.
 382         (select_arm_features): Make sure we enable MVE bits when selecting
 383         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 384         any architecture.
 385
 386 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 387
 388         * i386-opc.tbl: Drop stale comment from XOP section.
 389
 390 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 391
 392         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 393         (extractps): Add VexWIG to SSE2AVX forms.
 394         * i386-tbl.h: Re-generate.
 395
 396 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 397
 398         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 399         Size64 from and use VexW1 on SSE2AVX forms.
 400         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 401         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 402         * i386-tbl.h: Re-generate.
 403
 404 2020-01-15  Alan Modra  <amodra@gmail.com>
 405
 406         * tic4x-dis.c (tic4x_version): Make unsigned long.
 407         (optab, optab_special, registernames): New file scope vars.
 408         (tic4x_print_register): Set up registernames rather than
 409         malloc'd registertable.
 410         (tic4x_disassemble): Delete optable and optable_special.  Use
 411         optab and optab_special instead.  Throw away old optab,
 412         optab_special and registernames when info->mach changes.
 413
 414 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 415
 416         PR 25377
 417         * z80-dis.c (suffix): Use .db instruction to generate double
 418         prefix.
 419
 420 2020-01-14  Alan Modra  <amodra@gmail.com>
 421
 422         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 423         values to unsigned before shifting.
 424
 425 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 426
 427         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 428         flow instructions.
 429         (print_insn_thumb16, print_insn_thumb32): Likewise.
 430         (print_insn): Initialize the insn info.
 431         * i386-dis.c (print_insn): Initialize the insn info fields, and
 432         detect jumps.
 433
 434 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 435
 436         * arc-opc.c (C_NE): Make it required.
 437
 438 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 439
 440         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 441         reserved register name.
 442
 443 2020-01-13  Alan Modra  <amodra@gmail.com>
 444
 445         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 446         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 447
 448 2020-01-13  Alan Modra  <amodra@gmail.com>
 449
 450         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 451         result of wasm_read_leb128 in a uint64_t and check that bits
 452         are not lost when copying to other locals.  Use uint32_t for
 453         most locals.  Use PRId64 when printing int64_t.
 454
 455 2020-01-13  Alan Modra  <amodra@gmail.com>
 456
 457         * score-dis.c: Formatting.
 458         * score7-dis.c: Formatting.
 459
 460 2020-01-13  Alan Modra  <amodra@gmail.com>
 461
 462         * score-dis.c (print_insn_score48): Use unsigned variables for
 463         unsigned values.  Don't left shift negative values.
 464         (print_insn_score32): Likewise.
 465         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 466
 467 2020-01-13  Alan Modra  <amodra@gmail.com>
 468
 469         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 470
 471 2020-01-13  Alan Modra  <amodra@gmail.com>
 472
 473         * fr30-ibld.c: Regenerate.
 474
 475 2020-01-13  Alan Modra  <amodra@gmail.com>
 476
 477         * xgate-dis.c (print_insn): Don't left shift signed value.
 478         (ripBits): Formatting, use 1u.
 479
 480 2020-01-10  Alan Modra  <amodra@gmail.com>
 481
 482         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 483         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 484
 485 2020-01-10  Alan Modra  <amodra@gmail.com>
 486
 487         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 488         and XRREG value earlier to avoid a shift with negative exponent.
 489         * m10200-dis.c (disassemble): Similarly.
 490
 491 2020-01-09  Nick Clifton  <nickc@redhat.com>
 492
 493         PR 25224
 494         * z80-dis.c (ld_ii_ii): Use correct cast.
 495
 496 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 497
 498         PR 25224
 499         * z80-dis.c (ld_ii_ii): Use character constant when checking
 500         opcode byte value.
 501
 502 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 503
 504         * i386-dis.c (SEP_Fixup): New.
 505         (SEP): Define.
 506         (dis386_twobyte): Use it for sysenter/sysexit.
 507         (enum x86_64_isa): Change amd64 enumerator to value 1.
 508         (OP_J): Compare isa64 against intel64 instead of amd64.
 509         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 510         forms.
 511         * i386-tbl.h: Re-generate.
 512
 513 2020-01-08  Alan Modra  <amodra@gmail.com>
 514
 515         * z8k-dis.c: Include libiberty.h
 516         (instr_data_s): Make max_fetched unsigned.
 517         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 518         Don't exceed byte_info bounds.
 519         (output_instr): Make num_bytes unsigned.
 520         (unpack_instr): Likewise for nibl_count and loop.
 521         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 522         idx unsigned.
 523         * z8k-opc.h: Regenerate.
 524
 525 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 526
 527         * arc-tbl.h (llock): Use 'LLOCK' as class.
 528         (llockd): Likewise.
 529         (scond): Use 'SCOND' as class.
 530         (scondd): Likewise.
 531         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 532         (scondd): Likewise.
 533
 534 2020-01-06  Alan Modra  <amodra@gmail.com>
 535
 536         * m32c-ibld.c: Regenerate.
 537
 538 2020-01-06  Alan Modra  <amodra@gmail.com>
 539
 540         PR 25344
 541         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 542         Peek at next byte to prevent recursion on repeated prefix bytes.
 543         Ensure uninitialised "mybuf" is not accessed.
 544         (print_insn_z80): Don't zero n_fetch and n_used here,..
 545         (print_insn_z80_buf): ..do it here instead.
 546
 547 2020-01-04  Alan Modra  <amodra@gmail.com>
 548
 549         * m32r-ibld.c: Regenerate.
 550
 551 2020-01-04  Alan Modra  <amodra@gmail.com>
 552
 553         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 554
 555 2020-01-04  Alan Modra  <amodra@gmail.com>
 556
 557         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 558
 559 2020-01-04  Alan Modra  <amodra@gmail.com>
 560
 561         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 562
 563 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 564
 565         * aarch64-tbl.h (aarch64_opcode_table): Use
 566         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 567
 568 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 569
 570         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 571         forms of SUDOT and USDOT.
 572
 573 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 574
 575         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 576         uzip{1,2}.
 577         * opcodes/aarch64-dis-2.c: Re-generate.
 578
 579 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 580
 581         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 582         FMMLA encoding.
 583         * opcodes/aarch64-dis-2.c: Re-generate.
 584
 585 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 586
 587         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 588
 589 2020-01-01  Alan Modra  <amodra@gmail.com>
 590
 591         Update year range in copyright notice of all files.
 592
 593 For older changes see ChangeLog-2019
 594 \f
 595 Copyright (C) 2020 Free Software Foundation, Inc.
 596
 597 Copying and distribution of this file, with or without modification,
 598 are permitted in any medium without royalty provided the copyright
 599 notice and this notice are preserved.
 600
 601 Local Variables:
 602 mode: change-log
 603 left-margin: 8
 604 fill-column: 74
 605 version-control: never
 606 End: