opcodes/ChangeLog

   1 2016-10-11  Jiong Wang  <jiong.wang@arm.com>
   2
   3         PR target/20666
   4         * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
   5
   6 2016-10-07  Jiong Wang  <jiong.wang@arm.com>
   7
   8         PR target/20667
   9         * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
  10         available.
  11
  12 2016-10-07  Alan Modra  <amodra@gmail.com>
  13
  14         * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
  15
  16 2016-10-06  Alan Modra  <amodra@gmail.com>
  17
  18         * aarch64-opc.c: Spell fall through comments consistently.
  19         * i386-dis.c: Likewise.
  20         * aarch64-dis.c: Add missing fall through comments.
  21         * aarch64-opc.c: Likewise.
  22         * arc-dis.c: Likewise.
  23         * arm-dis.c: Likewise.
  24         * i386-dis.c: Likewise.
  25         * m68k-dis.c: Likewise.
  26         * mep-asm.c: Likewise.
  27         * ns32k-dis.c: Likewise.
  28         * sh-dis.c: Likewise.
  29         * tic4x-dis.c: Likewise.
  30         * tic6x-dis.c: Likewise.
  31         * vax-dis.c: Likewise.
  32
  33 2016-10-06  Alan Modra  <amodra@gmail.com>
  34
  35         * arc-ext.c (create_map): Add missing break.
  36         * msp430-decode.opc (encode_as): Likewise.
  37         * msp430-decode.c: Regenerate.
  38
  39 2016-10-06  Alan Modra  <amodra@gmail.com>
  40
  41         * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
  42         * crx-dis.c (print_insn_crx): Likewise.
  43
  44 2016-09-30  H.J. Lu  <hongjiu.lu@intel.com>
  45
  46         PR binutils/20657
  47         * i386-dis.c (putop): Don't assign alt twice.
  48
  49 2016-09-29  Jiong Wang  <jiong.wang@arm.com>
  50
  51         PR target/20553
  52         * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
  53
  54 2016-09-29  Alan Modra  <amodra@gmail.com>
  55
  56         * ppc-opc.c (L): Make compulsory.
  57         (LOPT): New, optional form of L.
  58         (HTM_R): Define as LOPT.
  59         (L0, L1): Delete.
  60         (L32OPT): New, optional for 32-bit L.
  61         (L2OPT): New, 2-bit L for dcbf.
  62         (SVC_LEC): Update.
  63         (L2): Define.
  64         (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
  65         (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
  66         <dcbf>: Use L2OPT.
  67         <tlbiel, tlbie>: Use LOPT.
  68         <wclr, wclrall>: Use L2.
  69
  70 2016-09-26  Vlad Zakharov  <vzakhar@synopsys.com>
  71
  72         * Makefile.in: Regenerate.
  73         * configure: Likewise.
  74
  75 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
  76
  77         * arc-ext-tbl.h (EXTINSN2OPF): Define.
  78         (EXTINSN2OP): Use EXTINSN2OPF.
  79         (bspeekm, bspop, modapp): New extension instructions.
  80         * arc-opc.c (F_DNZ_ND): Define.
  81         (F_DNZ_D): Likewise.
  82         (F_SIZEB1): Changed.
  83         (C_DNZ_D): Define.
  84         (C_HARD): Changed.
  85         * arc-tbl.h (dbnz): New instruction.
  86         (prealloc): Allow it for ARC EM.
  87         (xbfu): Likewise.
  88
  89 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  90
  91         * aarch64-opc.c (print_immediate_offset_address): Print spaces
  92         after commas in addresses.
  93         (aarch64_print_operand): Likewise.
  94
  95 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
  96
  97         * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
  98         rather than "should be" or "expected to be" in error messages.
  99
 100 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 101
 102         * aarch64-dis.c (remove_dot_suffix): New function, split out from...
 103         (print_mnemonic_name): ...here.
 104         (print_comment): New function.
 105         (print_aarch64_insn): Call it.
 106         * aarch64-opc.c (aarch64_conds): Add SVE names.
 107         (aarch64_print_operand): Print alternative condition names in
 108         a comment.
 109
 110 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 111
 112         * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
 113         (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
 114         (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
 115         (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
 116         (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
 117         (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
 118         (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
 119         (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
 120         (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
 121         (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
 122         (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
 123         (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
 124         (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
 125         (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
 126         (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
 127         (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
 128         (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
 129         (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
 130         (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
 131         (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
 132         (OP_SVE_XWU, OP_SVE_XXU): New macros.
 133         (aarch64_feature_sve): New variable.
 134         (SVE): New macro.
 135         (_SVE_INSN): Likewise.
 136         (aarch64_opcode_table): Add SVE instructions.
 137         * aarch64-opc.h (extract_fields): Declare.
 138         * aarch64-opc-2.c: Regenerate.
 139         * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
 140         * aarch64-asm-2.c: Regenerate.
 141         * aarch64-dis.c (extract_fields): Make global.
 142         (do_misc_decoding): Handle the new SVE aarch64_ops.
 143         * aarch64-dis-2.c: Regenerate.
 144
 145 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 146
 147         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
 148         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
 149         aarch64_field_kinds.
 150         * aarch64-opc.c (fields): Add corresponding entries.
 151         * aarch64-asm.c (aarch64_get_variant): New function.
 152         (aarch64_encode_variant_using_iclass): Likewise.
 153         (aarch64_opcode_encode): Call it.
 154         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
 155         (aarch64_opcode_decode): Call it.
 156
 157 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 158
 159         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
 160         and FP register operands.
 161         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
 162         (FLD_SVE_Vn): New aarch64_field_kinds.
 163         * aarch64-opc.c (fields): Add corresponding entries.
 164         (aarch64_print_operand): Handle the new SVE core and FP register
 165         operands.
 166         * aarch64-opc-2.c: Regenerate.
 167         * aarch64-asm-2.c: Likewise.
 168         * aarch64-dis-2.c: Likewise.
 169
 170 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 171
 172         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
 173         immediate operands.
 174         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
 175         * aarch64-opc.c (fields): Add corresponding entry.
 176         (operand_general_constraint_met_p): Handle the new SVE FP immediate
 177         operands.
 178         (aarch64_print_operand): Likewise.
 179         * aarch64-opc-2.c: Regenerate.
 180         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
 181         (ins_sve_float_zero_one): New inserters.
 182         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
 183         (aarch64_ins_sve_float_half_two): Likewise.
 184         (aarch64_ins_sve_float_zero_one): Likewise.
 185         * aarch64-asm-2.c: Regenerate.
 186         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
 187         (ext_sve_float_zero_one): New extractors.
 188         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
 189         (aarch64_ext_sve_float_half_two): Likewise.
 190         (aarch64_ext_sve_float_zero_one): Likewise.
 191         * aarch64-dis-2.c: Regenerate.
 192
 193 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 194
 195         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 196         integer immediate operands.
 197         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
 198         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
 199         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
 200         * aarch64-opc.c (fields): Add corresponding entries.
 201         (operand_general_constraint_met_p): Handle the new SVE integer
 202         immediate operands.
 203         (aarch64_print_operand): Likewise.
 204         (aarch64_sve_dupm_mov_immediate_p): New function.
 205         * aarch64-opc-2.c: Regenerate.
 206         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
 207         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
 208         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
 209         (aarch64_ins_limm): ...here.
 210         (aarch64_ins_inv_limm): New function.
 211         (aarch64_ins_sve_aimm): Likewise.
 212         (aarch64_ins_sve_asimm): Likewise.
 213         (aarch64_ins_sve_limm_mov): Likewise.
 214         (aarch64_ins_sve_shlimm): Likewise.
 215         (aarch64_ins_sve_shrimm): Likewise.
 216         * aarch64-asm-2.c: Regenerate.
 217         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
 218         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
 219         * aarch64-dis.c (decode_limm): New function, split out from...
 220         (aarch64_ext_limm): ...here.
 221         (aarch64_ext_inv_limm): New function.
 222         (decode_sve_aimm): Likewise.
 223         (aarch64_ext_sve_aimm): Likewise.
 224         (aarch64_ext_sve_asimm): Likewise.
 225         (aarch64_ext_sve_limm_mov): Likewise.
 226         (aarch64_top_bit): Likewise.
 227         (aarch64_ext_sve_shlimm): Likewise.
 228         (aarch64_ext_sve_shrimm): Likewise.
 229         * aarch64-dis-2.c: Regenerate.
 230
 231 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 232
 233         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
 234         operands.
 235         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
 236         the AARCH64_MOD_MUL_VL entry.
 237         (value_aligned_p): Cope with non-power-of-two alignments.
 238         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
 239         (print_immediate_offset_address): Likewise.
 240         (aarch64_print_operand): Likewise.
 241         * aarch64-opc-2.c: Regenerate.
 242         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
 243         (ins_sve_addr_ri_s9xvl): New inserters.
 244         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 245         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 246         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 247         * aarch64-asm-2.c: Regenerate.
 248         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 249         (ext_sve_addr_ri_s9xvl): New extractors.
 250         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 251         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 252         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 253         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 254         * aarch64-dis-2.c: Regenerate.
 255
 256 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 257
 258         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 259         address operands.
 260         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 261         (FLD_SVE_xs_22): New aarch64_field_kinds.
 262         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 263         (get_operand_specific_data): New function.
 264         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 265         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 266         (operand_general_constraint_met_p): Handle the new SVE address
 267         operands.
 268         (sve_reg): New array.
 269         (get_addr_sve_reg_name): New function.
 270         (aarch64_print_operand): Handle the new SVE address operands.
 271         * aarch64-opc-2.c: Regenerate.
 272         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 273         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 274         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 275         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 276         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 277         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 278         (aarch64_ins_sve_addr_zi_u5): Likewise.
 279         (aarch64_ins_sve_addr_zz): Likewise.
 280         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 281         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 282         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 283         * aarch64-asm-2.c: Regenerate.
 284         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 285         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 286         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 287         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 288         (aarch64_ext_sve_addr_ri_u6): Likewise.
 289         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 290         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 291         (aarch64_ext_sve_addr_zi_u5): Likewise.
 292         (aarch64_ext_sve_addr_zz): Likewise.
 293         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 294         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 295         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 296         * aarch64-dis-2.c: Regenerate.
 297
 298 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 299
 300         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 301         AARCH64_OPND_SVE_PATTERN_SCALED.
 302         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 303         * aarch64-opc.c (fields): Add a corresponding entry.
 304         (set_multiplier_out_of_range_error): New function.
 305         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 306         (operand_general_constraint_met_p): Handle
 307         AARCH64_OPND_SVE_PATTERN_SCALED.
 308         (print_register_offset_address): Use PRIi64 to print the
 309         shift amount.
 310         (aarch64_print_operand): Likewise.  Handle
 311         AARCH64_OPND_SVE_PATTERN_SCALED.
 312         * aarch64-opc-2.c: Regenerate.
 313         * aarch64-asm.h (ins_sve_scale): New inserter.
 314         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 315         * aarch64-asm-2.c: Regenerate.
 316         * aarch64-dis.h (ext_sve_scale): New inserter.
 317         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 318         * aarch64-dis-2.c: Regenerate.
 319
 320 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 321
 322         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 323         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 324         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 325         (FLD_SVE_prfop): Likewise.
 326         * aarch64-opc.c: Include libiberty.h.
 327         (aarch64_sve_pattern_array): New variable.
 328         (aarch64_sve_prfop_array): Likewise.
 329         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 330         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 331         AARCH64_OPND_SVE_PRFOP.
 332         * aarch64-asm-2.c: Regenerate.
 333         * aarch64-dis-2.c: Likewise.
 334         * aarch64-opc-2.c: Likewise.
 335
 336 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 337
 338         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 339         AARCH64_OPND_QLF_P_[ZM].
 340         (aarch64_print_operand): Print /z and /m where appropriate.
 341
 342 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 343
 344         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 345         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
 346         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
 347         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
 348         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
 349         * aarch64-opc.c (fields): Add corresponding entries here.
 350         (operand_general_constraint_met_p): Check that SVE register lists
 351         have the correct length.  Check the ranges of SVE index registers.
 352         Check for cases where p8-p15 are used in 3-bit predicate fields.
 353         (aarch64_print_operand): Handle the new SVE operands.
 354         * aarch64-opc-2.c: Regenerate.
 355         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 356         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 357         (aarch64_ins_sve_reglist): Likewise.
 358         * aarch64-asm-2.c: Regenerate.
 359         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 360         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 361         (aarch64_ext_sve_reglist): Likewise.
 362         * aarch64-dis-2.c: Regenerate.
 363
 364 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 365
 366         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 367         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 368         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 369         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 370         tied operands.
 371
 372 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 373
 374         * aarch64-opc.c (get_offset_int_reg_name): New function.
 375         (print_immediate_offset_address): Likewise.
 376         (print_register_offset_address): Take the base and offset
 377         registers as parameters.
 378         (aarch64_print_operand): Update caller accordingly.  Use
 379         print_immediate_offset_address.
 380
 381 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 382
 383         * aarch64-opc.c (BANK): New macro.
 384         (R32, R64): Take a register number as argument
 385         (int_reg): Use BANK.
 386
 387 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 388
 389         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 390         (aarch64_print_operand): Update accordingly.
 391
 392 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 393
 394         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
 395         for FPIMM.
 396         * aarch64-asm.h (ins_fpimm): New inserter.
 397         * aarch64-asm.c (aarch64_ins_fpimm): New function.
 398         * aarch64-asm-2.c: Regenerate.
 399         * aarch64-dis.h (ext_fpimm): New extractor.
 400         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
 401         (aarch64_ext_fpimm): New function.
 402         * aarch64-dis-2.c: Regenerate.
 403
 404 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 405
 406         * aarch64-asm.c: Include libiberty.h.
 407         (insert_fields): New function.
 408         (aarch64_ins_imm): Use it.
 409         * aarch64-dis.c (extract_fields): New function.
 410         (aarch64_ext_imm): Use it.
 411
 412 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 413
 414         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
 415         with an esize parameter.
 416         (operand_general_constraint_met_p): Update accordingly.
 417         Fix misindented code.
 418         * aarch64-asm.c (aarch64_ins_limm): Update call to
 419         aarch64_logical_immediate_p.
 420
 421 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 422
 423         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
 424
 425 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 426
 427         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
 428
 429 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
 430
 431         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
 432
 433 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
 434
 435         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
 436         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
 437         xor3>: Delete mnemonics.
 438         <cp_abort>: Rename mnemonic from ...
 439         <cpabort>: ...to this.
 440         <setb>: Change to a X form instruction.
 441         <sync>: Change to 1 operand form.
 442         <copy>: Delete mnemonic.
 443         <copy_first>: Rename mnemonic from ...
 444         <copy>: ...to this.
 445         <paste, paste.>: Delete mnemonics.
 446         <paste_last>: Rename mnemonic from ...
 447         <paste.>: ...to this.
 448
 449 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 450
 451         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
 452
 453 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 454
 455         * s390-mkopc.c (main): Support alternate arch strings.
 456
 457 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
 458
 459         * s390-opc.txt: Fix kmctr instruction type.
 460
 461 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
 462
 463         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
 464         * i386-init.h: Regenerated.
 465
 466 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
 467
 468         * opcodes/arc-dis.c (print_insn_arc): Changed.
 469
 470 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
 471
 472         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
 473         camellia_fl.
 474
 475 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 476
 477         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
 478         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
 479         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
 480
 481 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
 482
 483         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
 484         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
 485         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
 486         PREFIX_MOD_3_0FAE_REG_4.
 487         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
 488         PREFIX_MOD_3_0FAE_REG_4.
 489         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
 490         (cpu_flags): Add CpuPTWRITE.
 491         * i386-opc.h (CpuPTWRITE): New.
 492         (i386_cpu_flags): Add cpuptwrite.
 493         * i386-opc.tbl: Add ptwrite instruction.
 494         * i386-init.h: Regenerated.
 495         * i386-tbl.h: Likewise.
 496
 497 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 498
 499         * arc-dis.h: Wrap around in extern "C".
 500
 501 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 502
 503         * aarch64-tbl.h (V8_2_INSN): New macro.
 504         (aarch64_opcode_table): Use it.
 505
 506 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 507
 508         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
 509         CORE_INSN, __FP_INSN and SIMD_INSN.
 510
 511 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 512
 513         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
 514         (aarch64_opcode_table): Update uses accordingly.
 515
 516 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
 517         Kwok Cheung Yeung  <kcy@codesourcery.com>
 518
 519         opcodes/
 520         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
 521         'e_cmplwi' to 'e_cmpli' instead.
 522         (OPVUPRT, OPVUPRT_MASK): Define.
 523         (powerpc_opcodes): Add E200Z4 insns.
 524         (vle_opcodes): Add context save/restore insns.
 525
 526 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
 527
 528         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
 529         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
 530         "j".
 531
 532 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 533
 534         * arc-nps400-tbl.h: Change block comments to GNU format.
 535         * arc-dis.c: Add new globals addrtypenames,
 536         addrtypenames_max, and addtypeunknown.
 537         (get_addrtype): New function.
 538         (print_insn_arc): Print colons and address types when
 539         required.
 540         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
 541         define insert and extract functions for all address types.
 542         (arc_operands): Add operands for colon and all address
 543         types.
 544         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
 545         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
 546         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
 547         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
 548         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
 549         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
 550
 551 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
 552
 553         * configure: Regenerated.
 554
 555 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
 556
 557         * arc-dis.c (skipclass): New structure.
 558         (decodelist): New variable.
 559         (is_compatible_p): New function.
 560         (new_element): Likewise.
 561         (skip_class_p): Likewise.
 562         (find_format_from_table): Use skip_class_p function.
 563         (find_format): Decode first the extension instructions.
 564         (print_insn_arc): Select either ARCEM or ARCHS based on elf
 565         e_flags.
 566         (parse_option): New function.
 567         (parse_disassembler_options): Likewise.
 568         (print_arc_disassembler_options): Likewise.
 569         (print_insn_arc): Use parse_disassembler_options function.  Proper
 570         select ARCv2 cpu variant.
 571         * disassemble.c (disassembler_usage): Add ARC disassembler
 572         options.
 573
 574 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
 575
 576         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
 577         annotation from the "nal" entry and reorder it beyond "bltzal".
 578
 579 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
 580
 581         * sparc-opc.c (ldtxa): New macro.
 582         (sparc_opcodes): Use the macro defined above to add entries for
 583         the LDTXA instructions.
 584         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
 585         instruction.
 586
 587 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
 588
 589         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
 590         and "jmpc".
 591
 592 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 593
 594         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
 595         (movzb): Adjust to cover all permitted suffixes.
 596         (movzw): New.
 597         * i386-tbl.h: Re-generate.
 598
 599 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 600
 601         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
 602         (lgdt): Remove Tbyte from non-64-bit variant.
 603         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
 604         xsaves64, xsavec64): Remove Disp16.
 605         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
 606         Remove Disp32S from non-64-bit variants. Remove Disp16 from
 607         64-bit variants.
 608         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
 609         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
 610         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
 611         64-bit variants.
 612         * i386-tbl.h: Re-generate.
 613
 614 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 615
 616         * i386-opc.tbl (xlat): Remove RepPrefixOk.
 617         * i386-tbl.h: Re-generate.
 618
 619 2016-06-30  Yao Qi  <yao.qi@linaro.org>
 620
 621         * arm-dis.c (print_insn): Fix typo in comment.
 622
 623 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
 624
 625         * aarch64-opc.c (operand_general_constraint_met_p): Check the
 626         range of ldst_elemlist operands.
 627         (print_register_list): Use PRIi64 to print the index.
 628         (aarch64_print_operand): Likewise.
 629
 630 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 631
 632         * mcore-opc.h: Remove sentinal.
 633         * mcore-dis.c (print_insn_mcore): Adjust.
 634
 635 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
 636
 637         * arc-opc.c: Correct description of availability of NPS400
 638         features.
 639
 640 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
 641
 642         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
 643         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
 644         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
 645         xor3>: New mnemonics.
 646         <setb>: Change to a VX form instruction.
 647         (insert_sh6): Add support for rldixor.
 648         (extract_sh6): Likewise.
 649
 650 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 651
 652         * arc-ext.h: Wrap in extern C.
 653
 654 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
 655
 656         * arc-dis.c (arc_insn_length): Add comment on instruction length.
 657         Use same method for determining instruction length on ARC700 and
 658         NPS-400.
 659         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
 660         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
 661         with the NPS400 subclass.
 662         * arc-opc.c: Likewise.
 663
 664 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 665
 666         * sparc-opc.c (rdasr): New macro.
 667         (wrasr): Likewise.
 668         (rdpr): Likewise.
 669         (wrpr): Likewise.
 670         (rdhpr): Likewise.
 671         (wrhpr): Likewise.
 672         (sparc_opcodes): Use the macros above to fix and expand the
 673         definition of read/write instructions from/to
 674         asr/privileged/hyperprivileged instructions.
 675         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
 676         %hva_mask_nz.  Prefer softint_set and softint_clear over
 677         set_softint and clear_softint.
 678         (print_insn_sparc): Support %ver in Rd.
 679
 680 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 681
 682         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
 683         architecture according to the hardware capabilities they require.
 684
 685 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 686
 687         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
 688         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
 689         bfd_mach_sparc_v9{c,d,e,v,m}.
 690         * sparc-opc.c (MASK_V9C): Define.
 691         (MASK_V9D): Likewise.
 692         (MASK_V9E): Likewise.
 693         (MASK_V9V): Likewise.
 694         (MASK_V9M): Likewise.
 695         (v6): Add MASK_V9{C,D,E,V,M}.
 696         (v6notlet): Likewise.
 697         (v7): Likewise.
 698         (v8): Likewise.
 699         (v9): Likewise.
 700         (v9andleon): Likewise.
 701         (v9a): Likewise.
 702         (v9b): Likewise.
 703         (v9c): Define.
 704         (v9d): Likewise.
 705         (v9e): Likewise.
 706         (v9v): Likewise.
 707         (v9m): Likewise.
 708         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
 709
 710 2016-06-15  Nick Clifton  <nickc@redhat.com>
 711
 712         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
 713         constants to match expected behaviour.
 714         (nds32_parse_opcode): Likewise.  Also for whitespace.
 715
 716 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
 717
 718         * arc-opc.c (extract_rhv1): Extract value from insn.
 719
 720 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 721
 722         * arc-nps400-tbl.h: Add ldbit instruction.
 723         * arc-opc.c: Add flag classes required for ldbit.
 724
 725 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 726
 727         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
 728         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 729         support the above instructions.
 730
 731 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 732
 733         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
 734         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
 735         csma, cbba, zncv, and hofs.
 736         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 737         support the above instructions.
 738
 739 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 740
 741         * arc-nps400-tbl.h: Add andab and orab instructions.
 742
 743 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 744
 745         * arc-nps400-tbl.h: Add addl-like instructions.
 746
 747 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 748
 749         * arc-nps400-tbl.h: Add mxb and imxb instructions.
 750
 751 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 752
 753         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
 754         instructions.
 755
 756 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 757
 758         * s390-dis.c (option_use_insn_len_bits_p): New file scope
 759         variable.
 760         (init_disasm): Handle new command line option "insnlength".
 761         (print_s390_disassembler_options): Mention new option in help
 762         output.
 763         (print_insn_s390): Use the encoded insn length when dumping
 764         unknown instructions.
 765
 766 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 767
 768         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
 769          to the address and set as symbol address for LDS/ STS immediate operands.
 770
 771 2016-06-07  Alan Modra  <amodra@gmail.com>
 772
 773         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
 774         cpu for "vle" to e500.
 775         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
 776         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
 777         (PPCNONE): Delete, substitute throughout.
 778         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
 779         except for major opcode 4 and 31.
 780         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
 781
 782 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
 783
 784         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
 785         ARM_EXT_RAS in relevant entries.
 786
 787 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
 788
 789         PR binutils/20196
 790         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
 791         opcodes for E6500.
 792
 793 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
 794
 795         PR binutis/18386
 796         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
 797         (indir_v_mode): New.
 798         Add comments for '&'.
 799         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
 800         (putop): Handle '&'.
 801         (intel_operand_size): Handle indir_v_mode.
 802         (OP_E_register): Likewise.
 803         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
 804         64-bit indirect call/jmp for AMD64.
 805         * i386-tbl.h: Regenerated
 806
 807 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 808
 809         * arc-dis.c (struct arc_operand_iterator): New structure.
 810         (find_format_from_table): All the old content from find_format,
 811         with some minor adjustments, and parameter renaming.
 812         (find_format_long_instructions): New function.
 813         (find_format): Rewritten.
 814         (arc_insn_length): Add LSB parameter.
 815         (extract_operand_value): New function.
 816         (operand_iterator_next): New function.
 817         (print_insn_arc): Use new functions to find opcode, and iterator
 818         over operands.
 819         * arc-opc.c (insert_nps_3bit_dst_short): New function.
 820         (extract_nps_3bit_dst_short): New function.
 821         (insert_nps_3bit_src2_short): New function.
 822         (extract_nps_3bit_src2_short): New function.
 823         (insert_nps_bitop1_size): New function.
 824         (extract_nps_bitop1_size): New function.
 825         (insert_nps_bitop2_size): New function.
 826         (extract_nps_bitop2_size): New function.
 827         (insert_nps_bitop_mod4_msb): New function.
 828         (extract_nps_bitop_mod4_msb): New function.
 829         (insert_nps_bitop_mod4_lsb): New function.
 830         (extract_nps_bitop_mod4_lsb): New function.
 831         (insert_nps_bitop_dst_pos3_pos4): New function.
 832         (extract_nps_bitop_dst_pos3_pos4): New function.
 833         (insert_nps_bitop_ins_ext): New function.
 834         (extract_nps_bitop_ins_ext): New function.
 835         (arc_operands): Add new operands.
 836         (arc_long_opcodes): New global array.
 837         (arc_num_long_opcodes): New global.
 838         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
 839
 840 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 841
 842         * nds32-asm.h: Add extern "C".
 843         * sh-opc.h: Likewise.
 844
 845 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
 846
 847         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
 848         0,b,limm to the rflt instruction.
 849
 850 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 851
 852         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
 853         constant.
 854
 855 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
 856
 857         PR gas/20145
 858         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
 859         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
 860         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
 861         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
 862         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
 863         * i386-init.h: Regenerated.
 864
 865 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 866
 867         PR gas/20145
 868         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
 869         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
 870         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
 871         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
 872         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
 873         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
 874         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
 875         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
 876         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
 877         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
 878         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
 879         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
 880         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
 881         CpuRegMask for AVX512.
 882         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
 883         and CpuRegMask.
 884         (set_bitfield_from_cpu_flag_init): New function.
 885         (set_bitfield): Remove const on f.  Call
 886         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
 887         * i386-opc.h (CpuRegMMX): New.
 888         (CpuRegXMM): Likewise.
 889         (CpuRegYMM): Likewise.
 890         (CpuRegZMM): Likewise.
 891         (CpuRegMask): Likewise.
 892         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
 893         and cpuregmask.
 894         * i386-init.h: Regenerated.
 895         * i386-tbl.h: Likewise.
 896
 897 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 898
 899         PR gas/20154
 900         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
 901         (opcode_modifiers): Add AMD64 and Intel64.
 902         (main): Properly verify CpuMax.
 903         * i386-opc.h (CpuAMD64): Removed.
 904         (CpuIntel64): Likewise.
 905         (CpuMax): Set to CpuNo64.
 906         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
 907         (AMD64): New.
 908         (Intel64): Likewise.
 909         (i386_opcode_modifier): Add amd64 and intel64.
 910         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
 911         on call and jmp.
 912         * i386-init.h: Regenerated.
 913         * i386-tbl.h: Likewise.
 914
 915 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 916
 917         PR gas/20154
 918         * i386-gen.c (main): Fail if CpuMax is incorrect.
 919         * i386-opc.h (CpuMax): Set to CpuIntel64.
 920         * i386-tbl.h: Regenerated.
 921
 922 2016-05-27  Nick Clifton  <nickc@redhat.com>
 923
 924         PR target/20150
 925         * msp430-dis.c (msp430dis_read_two_bytes): New function.
 926         (msp430dis_opcode_unsigned): New function.
 927         (msp430dis_opcode_signed): New function.
 928         (msp430_singleoperand): Use the new opcode reading functions.
 929         Only disassenmble bytes if they were successfully read.
 930         (msp430_doubleoperand): Likewise.
 931         (msp430_branchinstr): Likewise.
 932         (msp430x_callx_instr): Likewise.
 933         (print_insn_msp430): Check that it is safe to read bytes before
 934         attempting disassembly.  Use the new opcode reading functions.
 935
 936 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
 937
 938         * ppc-opc.c (CY): New define.  Document it.
 939         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
 940
 941 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 942
 943         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
 944         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
 945         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
 946         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
 947         CPU_ANY_AVX_FLAGS.
 948         * i386-init.h: Regenerated.
 949
 950 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 951
 952         PR gas/20141
 953         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
 954         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 955         * i386-init.h: Regenerated.
 956
 957 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 958
 959         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
 960         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
 961         * i386-init.h: Regenerated.
 962
 963 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 964
 965         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
 966         information.
 967         (print_insn_arc): Set insn_type information.
 968         * arc-opc.c (C_CC): Add F_CLASS_COND.
 969         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
 970         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
 971         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
 972         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
 973         (brne, brne_s, jeq_s, jne_s): Likewise.
 974
 975 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 976
 977         * arc-tbl.h (neg): New instruction variant.
 978
 979 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
 980
 981         * arc-dis.c (find_format, find_format, get_auxreg)
 982         (print_insn_arc): Changed.
 983         * arc-ext.h (INSERT_XOP): Likewise.
 984
 985 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 986
 987         * tic54x-dis.c (sprint_mmr): Adjust.
 988         * tic54x-opc.c: Likewise.
 989
 990 2016-05-19  Alan Modra  <amodra@gmail.com>
 991
 992         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
 993
 994 2016-05-19  Alan Modra  <amodra@gmail.com>
 995
 996         * ppc-opc.c: Formatting.
 997         (NSISIGNOPT): Define.
 998         (powerpc_opcodes <subis>): Use NSISIGNOPT.
 999
1000 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
1001
1002         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1003         replacing references to `micromips_ase' throughout.
1004         (_print_insn_mips): Don't use file-level microMIPS annotation to
1005         determine the disassembly mode with the symbol table.
1006
1007 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
1008
1009         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1010
1011 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
1012
1013         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1014         mips64r6.
1015         * mips-opc.c (D34): New macro.
1016         (mips_builtin_opcodes): Define bposge32c for DSPr3.
1017
1018 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
1019
1020         * i386-dis.c (prefix_table): Add RDPID instruction.
1021         * i386-gen.c (cpu_flag_init): Add RDPID flag.
1022         (cpu_flags): Add RDPID bitfield.
1023         * i386-opc.h (enum): Add RDPID element.
1024         (i386_cpu_flags): Add RDPID field.
1025         * i386-opc.tbl: Add RDPID instruction.
1026         * i386-init.h: Regenerate.
1027         * i386-tbl.h: Regenerate.
1028
1029 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1030
1031         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1032         branch type of a symbol.
1033         (print_insn): Likewise.
1034
1035 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1036
1037         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1038         Mainline Security Extensions instructions.
1039         (thumb_opcodes): Add entries for narrow ARMv8-M Security
1040         Extensions instructions.
1041         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1042         instructions.
1043         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1044         special registers.
1045
1046 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
1047
1048         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1049
1050 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
1051
1052         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1053         (arcExtMap_genOpcode): Likewise.
1054         * arc-opc.c (arg_32bit_rc): Define new variable.
1055         (arg_32bit_u6): Likewise.
1056         (arg_32bit_limm): Likewise.
1057
1058 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1059
1060         * aarch64-gen.c (VERIFIER): Define.
1061         * aarch64-opc.c (VERIFIER): Define.
1062         (verify_ldpsw): Use static linkage.
1063         * aarch64-opc.h (verify_ldpsw): Remove.
1064         * aarch64-tbl.h: Use VERIFIER for verifiers.
1065
1066 2016-04-28  Nick Clifton  <nickc@redhat.com>
1067
1068         PR target/19722
1069         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1070         * aarch64-opc.c (verify_ldpsw): New function.
1071         * aarch64-opc.h (verify_ldpsw): New prototype.
1072         * aarch64-tbl.h: Add initialiser for verifier field.
1073         (LDPSW): Set verifier to verify_ldpsw.
1074
1075 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
1076
1077         PR binutils/19983
1078         PR binutils/19984
1079         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1080         smaller than address size.
1081
1082 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1083
1084         * alpha-dis.c: Regenerate.
1085         * crx-dis.c: Likewise.
1086         * disassemble.c: Likewise.
1087         * epiphany-opc.c: Likewise.
1088         * fr30-opc.c: Likewise.
1089         * frv-opc.c: Likewise.
1090         * ip2k-opc.c: Likewise.
1091         * iq2000-opc.c: Likewise.
1092         * lm32-opc.c: Likewise.
1093         * lm32-opinst.c: Likewise.
1094         * m32c-opc.c: Likewise.
1095         * m32r-opc.c: Likewise.
1096         * m32r-opinst.c: Likewise.
1097         * mep-opc.c: Likewise.
1098         * mt-opc.c: Likewise.
1099         * or1k-opc.c: Likewise.
1100         * or1k-opinst.c: Likewise.
1101         * tic80-opc.c: Likewise.
1102         * xc16x-opc.c: Likewise.
1103         * xstormy16-opc.c: Likewise.
1104
1105 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1106
1107         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1108         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1109         calcsd, and calcxd instructions.
1110         * arc-opc.c (insert_nps_bitop_size): Delete.
1111         (extract_nps_bitop_size): Delete.
1112         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1113         (extract_nps_qcmp_m3): Define.
1114         (extract_nps_qcmp_m2): Define.
1115         (extract_nps_qcmp_m1): Define.
1116         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1117         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1118         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1119         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1120         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1121         NPS_QCMP_M3.
1122
1123 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1124
1125         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1126
1127 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1128
1129         * Makefile.in: Regenerated with automake 1.11.6.
1130         * aclocal.m4: Likewise.
1131
1132 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1133
1134         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1135         instructions.
1136         * arc-opc.c (insert_nps_cmem_uimm16): New function.
1137         (extract_nps_cmem_uimm16): New function.
1138         (arc_operands): Add NPS_XLDST_UIMM16 operand.
1139
1140 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1141
1142         * arc-dis.c (arc_insn_length): New function.
1143         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1144         (find_format): Change insnLen parameter to unsigned.
1145
1146 2016-04-13  Nick Clifton  <nickc@redhat.com>
1147
1148         PR target/19937
1149         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1150         the LD.B and LD.BU instructions.
1151
1152 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1153
1154         * arc-dis.c (find_format): Check for extension flags.
1155         (print_flags): New function.
1156         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1157         .extAuxRegister.
1158         * arc-ext.c (arcExtMap_coreRegName): Use
1159         LAST_EXTENSION_CORE_REGISTER.
1160         (arcExtMap_coreReadWrite): Likewise.
1161         (dump_ARC_extmap): Update printing.
1162         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1163         (arc_aux_regs): Add cpu field.
1164         * arc-regs.h: Add cpu field, lower case name aux registers.
1165
1166 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1167
1168         * arc-tbl.h: Add rtsc, sleep with no arguments.
1169
1170 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1171
1172         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1173         Initialize.
1174         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1175         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1176         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1177         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1178         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1179         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1180         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1181         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1182         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1183         (arc_opcode arc_opcodes): Null terminate the array.
1184         (arc_num_opcodes): Remove.
1185         * arc-ext.h (INSERT_XOP): Define.
1186         (extInstruction_t): Likewise.
1187         (arcExtMap_instName): Delete.
1188         (arcExtMap_insn): New function.
1189         (arcExtMap_genOpcode): Likewise.
1190         * arc-ext.c (ExtInstruction): Remove.
1191         (create_map): Zero initialize instruction fields.
1192         (arcExtMap_instName): Remove.
1193         (arcExtMap_insn): New function.
1194         (dump_ARC_extmap): More info while debuging.
1195         (arcExtMap_genOpcode): New function.
1196         * arc-dis.c (find_format): New function.
1197         (print_insn_arc): Use find_format.
1198         (arc_get_disassembler): Enable dump_ARC_extmap only when
1199         debugging.
1200
1201 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1202
1203         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1204         instruction bits out.
1205
1206 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1207
1208         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1209         * arc-opc.c (arc_flag_operands): Add new flags.
1210         (arc_flag_classes): Add new classes.
1211
1212 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1213
1214         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1215
1216 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1217
1218         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1219         encode1, rflt, crc16, and crc32 instructions.
1220         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1221         (arc_flag_classes): Add C_NPS_R.
1222         (insert_nps_bitop_size_2b): New function.
1223         (extract_nps_bitop_size_2b): Likewise.
1224         (insert_nps_bitop_uimm8): Likewise.
1225         (extract_nps_bitop_uimm8): Likewise.
1226         (arc_operands): Add new operand entries.
1227
1228 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1229
1230         * arc-regs.h: Add a new subclass field.  Add double assist
1231         accumulator register values.
1232         * arc-tbl.h: Use DPA subclass to mark the double assist
1233         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1234         * arc-opc.c (RSP): Define instead of SP.
1235         (arc_aux_regs): Add the subclass field.
1236
1237 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1238
1239         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1240
1241 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1242
1243         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1244         NPS_R_SRC1.
1245
1246 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1247
1248         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1249         issues.  No functional changes.
1250
1251 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1252
1253         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1254         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1255         (RTT): Remove duplicate.
1256         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1257         (PCT_CONFIG*): Remove.
1258         (D1L, D1H, D2H, D2L): Define.
1259
1260 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1261
1262         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1263
1264 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1265
1266         * arc-tbl.h (invld07): Remove.
1267         * arc-ext-tbl.h: New file.
1268         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1269         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1270
1271 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1272
1273         Fix -Wstack-usage warnings.
1274         * aarch64-dis.c (print_operands): Substitute size.
1275         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1276
1277 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1278
1279         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1280         to get a proper diagnostic when an invalid ASR register is used.
1281
1282 2016-03-22  Nick Clifton  <nickc@redhat.com>
1283
1284         * configure: Regenerate.
1285
1286 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1287
1288         * arc-nps400-tbl.h: New file.
1289         * arc-opc.c: Add top level comment.
1290         (insert_nps_3bit_dst): New function.
1291         (extract_nps_3bit_dst): New function.
1292         (insert_nps_3bit_src2): New function.
1293         (extract_nps_3bit_src2): New function.
1294         (insert_nps_bitop_size): New function.
1295         (extract_nps_bitop_size): New function.
1296         (arc_flag_operands): Add nps400 entries.
1297         (arc_flag_classes): Add nps400 entries.
1298         (arc_operands): Add nps400 entries.
1299         (arc_opcodes): Add nps400 include.
1300
1301 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1302
1303         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1304         the new class enum values.
1305
1306 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1307
1308         * arc-dis.c (print_insn_arc): Handle nps400.
1309
1310 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1311
1312         * arc-opc.c (BASE): Delete.
1313
1314 2016-03-18  Nick Clifton  <nickc@redhat.com>
1315
1316         PR target/19721
1317         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1318         of MOV insn that aliases an ORR insn.
1319
1320 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1321
1322         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1323
1324 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1325
1326         * mcore-opc.h: Add const qualifiers.
1327         * microblaze-opc.h (struct op_code_struct): Likewise.
1328         * sh-opc.h: Likewise.
1329         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1330         (tic4x_print_op): Likewise.
1331
1332 2016-03-02  Alan Modra  <amodra@gmail.com>
1333
1334         * or1k-desc.h: Regenerate.
1335         * fr30-ibld.c: Regenerate.
1336         * rl78-decode.c: Regenerate.
1337
1338 2016-03-01  Nick Clifton  <nickc@redhat.com>
1339
1340         PR target/19747
1341         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1342
1343 2016-02-24  Renlin Li  <renlin.li@arm.com>
1344
1345         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1346         (print_insn_coprocessor): Support fp16 instructions.
1347
1348 2016-02-24  Renlin Li  <renlin.li@arm.com>
1349
1350         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1351         vminnm, vrint(mpna).
1352
1353 2016-02-24  Renlin Li  <renlin.li@arm.com>
1354
1355         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1356         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1357
1358 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1359
1360         * i386-dis.c (print_insn): Parenthesize expression to prevent
1361         truncated addresses.
1362         (OP_J): Likewise.
1363
1364 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1365             Janek van Oirschot  <jvanoirs@synopsys.com>
1366
1367         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1368         variable.
1369
1370 2016-02-04  Nick Clifton  <nickc@redhat.com>
1371
1372         PR target/19561
1373         * msp430-dis.c (print_insn_msp430): Add a special case for
1374         decoding an RRC instruction with the ZC bit set in the extension
1375         word.
1376
1377 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1378
1379         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1380         * epiphany-ibld.c: Regenerate.
1381         * fr30-ibld.c: Regenerate.
1382         * frv-ibld.c: Regenerate.
1383         * ip2k-ibld.c: Regenerate.
1384         * iq2000-ibld.c: Regenerate.
1385         * lm32-ibld.c: Regenerate.
1386         * m32c-ibld.c: Regenerate.
1387         * m32r-ibld.c: Regenerate.
1388         * mep-ibld.c: Regenerate.
1389         * mt-ibld.c: Regenerate.
1390         * or1k-ibld.c: Regenerate.
1391         * xc16x-ibld.c: Regenerate.
1392         * xstormy16-ibld.c: Regenerate.
1393
1394 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1395
1396         * epiphany-dis.c: Regenerated from latest cpu files.
1397
1398 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1399
1400         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1401         test bit.
1402
1403 2016-01-25  Renlin Li  <renlin.li@arm.com>
1404
1405         * arm-dis.c (mapping_symbol_for_insn): New function.
1406         (find_ifthen_state): Call mapping_symbol_for_insn().
1407
1408 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1409
1410         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1411         of MSR UAO immediate operand.
1412
1413 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1414
1415         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1416         instruction support.
1417
1418 2016-01-17  Alan Modra  <amodra@gmail.com>
1419
1420         * configure: Regenerate.
1421
1422 2016-01-14  Nick Clifton  <nickc@redhat.com>
1423
1424         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1425         instructions that can support stack pointer operations.
1426         * rl78-decode.c: Regenerate.
1427         * rl78-dis.c: Fix display of stack pointer in MOVW based
1428         instructions.
1429
1430 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1431
1432         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1433         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1434         erxtatus_el1 and erxaddr_el1.
1435
1436 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1437
1438         * arm-dis.c (arm_opcodes): Add "esb".
1439         (thumb_opcodes): Likewise.
1440
1441 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1442
1443         * ppc-opc.c <xscmpnedp>: Delete.
1444         <xvcmpnedp>: Likewise.
1445         <xvcmpnedp.>: Likewise.
1446         <xvcmpnesp>: Likewise.
1447         <xvcmpnesp.>: Likewise.
1448
1449 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1450
1451         PR gas/13050
1452         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1453         addition to ISA_A.
1454
1455 2016-01-01  Alan Modra  <amodra@gmail.com>
1456
1457         Update year range in copyright notice of all files.
1458
1459 For older changes see ChangeLog-2015
1460 \f
1461 Copyright (C) 2016 Free Software Foundation, Inc.
1462
1463 Copying and distribution of this file, with or without modification,
1464 are permitted in any medium without royalty provided the copyright
1465 notice and this notice are preserved.
1466
1467 Local Variables:
1468 mode: change-log
1469 left-margin: 8
1470 fill-column: 74
1471 version-control: never
1472 End: