opcodes/ChangeLog

   1 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
   2 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
   3
   4         * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
   5         Armv8.6-A.
   6         (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
   7         (neon_opcodes): Add bfloat SIMD instructions.
   8         (print_insn_coprocessor): Add new control character %b to print
   9         condition code without checking cp_num.
  10         (print_insn_neon): Account for BFloat16 instructions that have no
  11         special top-byte handling.
  12
  13 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
  14 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
  15
  16         * arm-dis.c (print_insn_coprocessor,
  17         print_insn_generic_coprocessor): Create wrapper functions around
  18         the implementation of the print_insn_coprocessor control codes.
  19         (print_insn_coprocessor_1): Original print_insn_coprocessor
  20         function that now takes which array to look at as an argument.
  21         (print_insn_arm): Use both print_insn_coprocessor and
  22         print_insn_generic_coprocessor.
  23         (print_insn_thumb32): As above.
  24
  25 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
  26 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
  27
  28         * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
  29         in reglane special case.
  30         * aarch64-dis-2.c (aarch64_opcode_lookup_1,
  31         aarch64_find_next_opcode): Account for new instructions.
  32         * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
  33         in reglane special case.
  34         * aarch64-opc.c (struct operand_qualifier_data): Add data for
  35         new AARCH64_OPND_QLF_S_2H qualifier.
  36         * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
  37         QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
  38         (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
  39         sets.
  40         (BFLOAT_SVE, BFLOAT): New feature set macros.
  41         (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
  42         instructions.
  43         (aarch64_opcode_table): Define new instructions bfdot,
  44         bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
  45         bfcvtn2, bfcvt.
  46
  47 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
  48 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
  49
  50         * aarch64-tbl.h (ARMV8_6): New macro.
  51
  52 2019-11-07  Jan Beulich  <jbeulich@suse.com>
  53
  54         * i386-dis.c (prefix_table): Add mcommit.
  55         (rm_table): Add rdpru.
  56         * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
  57         CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
  58         (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
  59         * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
  60         (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
  61         * i386-opc.tbl (mcommit, rdpru): New.
  62         * i386-init.h, i386-tbl.h: Re-generate.
  63
  64 2019-11-07  Jan Beulich  <jbeulich@suse.com>
  65
  66         * i386-dis.c (OP_Mwait): Drop local variable "names", use
  67         "names32" instead.
  68         (OP_Monitor): Drop local variable "op1_names", re-purpose
  69         "names" for it instead, and replace former "names" uses by
  70         "names32" ones.
  71
  72 2019-11-07  Jan Beulich  <jbeulich@suse.com>
  73
  74         PR/gas 25167
  75         * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
  76         operand-less forms.
  77         * opcodes/i386-tbl.h: Re-generate.
  78
  79 2019-11-05  Jan Beulich  <jbeulich@suse.com>
  80
  81         * i386-dis.c (OP_Mwaitx): Delete.
  82         (prefix_table): Use OP_Mwait for mwaitx entry.
  83         (OP_Mwait): Also handle mwaitx.
  84
  85 2019-11-05  Jan Beulich  <jbeulich@suse.com>
  86
  87         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
  88         PREFIX_0F01_REG_7_MOD_3_RM_3): New.
  89         (prefix_table): Add respective entries.
  90         (rm_table): Link to those entries.
  91
  92 2019-11-05  Jan Beulich  <jbeulich@suse.com>
  93
  94         * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
  95         (REG_0F1C_P_0_MOD_0): ... this.
  96         (REG_0F1E_MOD_3): Rename to ...
  97         (REG_0F1E_P_1_MOD_3): ... this.
  98         (RM_0F01_REG_5): Rename to ...
  99         (RM_0F01_REG_5_MOD_3): ... this.
 100         (RM_0F01_REG_7): Rename to ...
 101         (RM_0F01_REG_7_MOD_3): ... this.
 102         (RM_0F1E_MOD_3_REG_7): Rename to ...
 103         (RM_0F1E_P_1_MOD_3_REG_7): ... this.
 104         (RM_0FAE_REG_6): Rename to ...
 105         (RM_0FAE_REG_6_MOD_3_P_0): ... this.
 106         (RM_0FAE_REG_7): Rename to ...
 107         (RM_0FAE_REG_7_MOD_3): ... this.
 108         (PREFIX_MOD_0_0F01_REG_5): Rename to ...
 109         (PREFIX_0F01_REG_5_MOD_0): ... this.
 110         (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
 111         (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
 112         (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
 113         (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
 114         (PREFIX_0FAE_REG_0): Rename to ...
 115         (PREFIX_0FAE_REG_0_MOD_3): ... this.
 116         (PREFIX_0FAE_REG_1): Rename to ...
 117         (PREFIX_0FAE_REG_1_MOD_3): ... this.
 118         (PREFIX_0FAE_REG_2): Rename to ...
 119         (PREFIX_0FAE_REG_2_MOD_3): ... this.
 120         (PREFIX_0FAE_REG_3): Rename to ...
 121         (PREFIX_0FAE_REG_3_MOD_3): ... this.
 122         (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
 123         (PREFIX_0FAE_REG_4_MOD_0): ... this.
 124         (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
 125         (PREFIX_0FAE_REG_4_MOD_3): ... this.
 126         (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
 127         (PREFIX_0FAE_REG_5_MOD_0): ... this.
 128         (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
 129         (PREFIX_0FAE_REG_5_MOD_3): ... this.
 130         (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
 131         (PREFIX_0FAE_REG_6_MOD_0): ... this.
 132         (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
 133         (PREFIX_0FAE_REG_6_MOD_3): ... this.
 134         (PREFIX_0FAE_REG_7): Rename to ...
 135         (PREFIX_0FAE_REG_7_MOD_0): ... this.
 136         (PREFIX_MOD_0_0FC3): Rename to ...
 137         (PREFIX_0FC3_MOD_0): ... this.
 138         (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
 139         (PREFIX_0FC7_REG_6_MOD_0): ... this.
 140         (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
 141         (PREFIX_0FC7_REG_6_MOD_3): ... this.
 142         (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
 143         (PREFIX_0FC7_REG_7_MOD_3): ... this.
 144         (reg_table, prefix_table, mod_table, rm_table): Adjust
 145         accordingly.
 146
 147 2019-11-04  Nick Clifton  <nickc@redhat.com>
 148
 149         * v850-dis.c (get_v850_sreg_name): New function.  Returns the name
 150         of a v850 system register.  Move the v850_sreg_names array into
 151         this function.
 152         (get_v850_reg_name): Likewise for ordinary register names.
 153         (get_v850_vreg_name): Likewise for vector register names.
 154         (get_v850_cc_name): Likewise for condition codes.
 155         * get_v850_float_cc_name): Likewise for floating point condition
 156         codes.
 157         (get_v850_cacheop_name): Likewise for cache-ops.
 158         (get_v850_prefop_name): Likewise for pref-ops.
 159         (disassemble): Use the new accessor functions.
 160
 161 2019-10-30  Delia Burduv   <delia.burduv@arm.com>
 162
 163         * aarch64-opc.c (print_immediate_offset_address): Don't print the
 164         immediate for the writeback form of ldraa/ldrab if it is 0.
 165         * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
 166         * aarch64-opc-2.c: Regenerated.
 167
 168 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 169
 170         * i386-gen.c (operand_type_shorthands): Delete.
 171         (operand_type_init): Expand previous shorthands.
 172         (set_bitfield_from_shorthand): Rename back to ...
 173         (set_bitfield_from_cpu_flag_init): ... this.  Drop processing
 174         of operand_type_init[].
 175         (set_bitfield): Adjust call to the above function.
 176         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
 177         RegXMM, RegYMM, RegZMM): Define.
 178         * i386-reg.tbl: Expand prior shorthands.
 179
 180 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 181
 182         * i386-gen.c (output_i386_opcode): Change order of fields
 183         emitted to output.
 184         * i386-opc.h (struct insn_template): Move operands field.
 185         Convert extension_opcode field to unsigned short.
 186         * i386-tbl.h: Re-generate.
 187
 188 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 189
 190         * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
 191         of W.
 192         * i386-opc.h (W): Extend comment.
 193         * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
 194         general purpose variants not allowing for byte operands.
 195         * i386-tbl.h: Re-generate.
 196
 197 2019-10-29  Nick Clifton  <nickc@redhat.com>
 198
 199         * tic30-dis.c (print_branch): Correct size of operand array.
 200
 201 2019-10-29  Nick Clifton  <nickc@redhat.com>
 202
 203         * d30v-dis.c (print_insn): Check that operand index is valid
 204         before attempting to access the operands array.
 205
 206 2019-10-29  Nick Clifton  <nickc@redhat.com>
 207
 208         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
 209         locating the bit to be tested.
 210
 211 2019-10-29  Nick Clifton  <nickc@redhat.com>
 212
 213         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
 214         values.
 215         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
 216         (print_insn_s12z):  Check for illegal size values.
 217
 218 2019-10-28  Nick Clifton  <nickc@redhat.com>
 219
 220         * csky-dis.c (csky_chars_to_number): Check for a negative
 221         count. Use an unsigned integer to construct the return value.
 222
 223 2019-10-28  Nick Clifton  <nickc@redhat.com>
 224
 225         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
 226         operand buffer.  Set value to 15 not 13.
 227         (get_register_operand): Use OPERAND_BUFFER_LEN.
 228         (get_indirect_operand): Likewise.
 229         (print_two_operand): Likewise.
 230         (print_three_operand): Likewise.
 231         (print_oar_insn): Likewise.
 232
 233 2019-10-28  Nick Clifton  <nickc@redhat.com>
 234
 235         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
 236         (bit_extract_simple): Likewise.
 237         (bit_copy): Likewise.
 238         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
 239         index_offset array are not accessed.
 240
 241 2019-10-28  Nick Clifton  <nickc@redhat.com>
 242
 243         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
 244         operand.
 245
 246 2019-10-25  Nick Clifton  <nickc@redhat.com>
 247
 248         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
 249         access to opcodes.op array element.
 250
 251 2019-10-23  Nick Clifton  <nickc@redhat.com>
 252
 253         * rx-dis.c (get_register_name): Fix spelling typo in error
 254         message.
 255         (get_condition_name, get_flag_name, get_double_register_name)
 256         (get_double_register_high_name, get_double_register_low_name)
 257         (get_double_control_register_name, get_double_condition_name)
 258         (get_opsize_name, get_size_name): Likewise.
 259
 260 2019-10-22  Nick Clifton  <nickc@redhat.com>
 261
 262         * rx-dis.c (get_size_name): New function.  Provides safe
 263         access to name array.
 264         (get_opsize_name): Likewise.
 265         (print_insn_rx): Use the accessor functions.
 266
 267 2019-10-16  Nick Clifton  <nickc@redhat.com>
 268
 269         * rx-dis.c (get_register_name): New function.  Provides safe
 270         access to name array.
 271         (get_condition_name, get_flag_name, get_double_register_name)
 272         (get_double_register_high_name, get_double_register_low_name)
 273         (get_double_control_register_name, get_double_condition_name):
 274         Likewise.
 275         (print_insn_rx): Use the accessor functions.
 276
 277 2019-10-09  Nick Clifton  <nickc@redhat.com>
 278
 279         PR 25041
 280         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
 281         instructions.
 282
 283 2019-10-07  Jan Beulich  <jbeulich@suse.com>
 284
 285         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
 286         (cmpsd): Likewise. Move EsSeg to other operand.
 287         * opcodes/i386-tbl.h: Re-generate.
 288
 289 2019-09-23  Alan Modra  <amodra@gmail.com>
 290
 291         * m68k-dis.c: Include cpu-m68k.h
 292
 293 2019-09-23  Alan Modra  <amodra@gmail.com>
 294
 295         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
 296         "elf/mips.h" earlier.
 297
 298 2018-09-20  Jan Beulich  <jbeulich@suse.com>
 299
 300         PR gas/25012
 301         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 302         with SReg operand.
 303         * i386-tbl.h: Re-generate.
 304
 305 2019-09-18  Alan Modra  <amodra@gmail.com>
 306
 307         * arc-ext.c: Update throughout for bfd section macro changes.
 308
 309 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 310
 311         * Makefile.in: Re-generate.
 312         * configure: Re-generate.
 313
 314 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 315
 316         * riscv-opc.c (riscv_opcodes): Change subset field
 317         to insn_class field for all instructions.
 318         (riscv_insn_types): Likewise.
 319
 320 2019-09-16  Phil Blundell  <pb@pbcl.net>
 321
 322         * configure: Regenerated.
 323
 324 2019-09-10  Miod Vallat  <miod@online.fr>
 325
 326         PR 24982
 327         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 328
 329 2019-09-09  Phil Blundell  <pb@pbcl.net>
 330
 331         binutils 2.33 branch created.
 332
 333 2019-09-03  Nick Clifton  <nickc@redhat.com>
 334
 335         PR 24961
 336         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 337         greater than zero before indexing via (bufcnt -1).
 338
 339 2019-09-03  Nick Clifton  <nickc@redhat.com>
 340
 341         PR 24958
 342         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 343         (MAX_SPEC_REG_NAME_LEN): Define.
 344         (struct mmix_dis_info): Use defined constants for array lengths.
 345         (get_reg_name): New function.
 346         (get_sprec_reg_name): New function.
 347         (print_insn_mmix): Use new functions.
 348
 349 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 350
 351         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 352         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 353         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 354
 355 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 356
 357         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 358         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 359         (aarch64_sys_reg_supported_p): Update checks for the above.
 360
 361 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 362
 363         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 364         cases MVE_SQRSHRL and MVE_UQRSHLL.
 365         (print_insn_mve): Add case for specifier 'k' to check
 366         specific bit of the instruction.
 367
 368 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 369
 370         PR 24854
 371         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 372         encountering an unknown machine type.
 373         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 374         cases return -1 rather than calling abort.
 375
 376 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 377
 378         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 379         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 380         IgnoreSize.
 381         * i386-tbl.h: Re-generate.
 382
 383 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 384
 385         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 386         instructions.
 387
 388 2019-07-30  Mel Chen <mel.chen@sifive.com>
 389
 390         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 391         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 392
 393         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 394         fscsr.
 395
 396 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 397
 398         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 399         and MPY class instructions.
 400         (parse_option): Add nps400 option.
 401         (print_arc_disassembler_options): Add nps400 info.
 402
 403 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 404
 405         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 406         (bspop): Likewise.
 407         (modapp): Likewise.
 408         * arc-opc.c (RAD_CHK): Add.
 409         * arc-tbl.h: Regenerate.
 410
 411 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 412
 413         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 414         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 415
 416 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 417
 418         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 419         instructions as UNPREDICTABLE.
 420
 421 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 422
 423         * bpf-desc.c: Regenerated.
 424
 425 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 426
 427         * i386-gen.c (static_assert): Define.
 428         (main): Use it.
 429         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 430         (Opcode_Modifier_Num): ... this.
 431         (Mem): Delete.
 432
 433 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 434
 435         * i386-gen.c (operand_types): Move RegMem ...
 436         (opcode_modifiers): ... here.
 437         * i386-opc.h (RegMem): Move to opcode modifer enum.
 438         (union i386_operand_type): Move regmem field ...
 439         (struct i386_opcode_modifier): ... here.
 440         * i386-opc.tbl (RegMem): Define.
 441         (mov, movq): Move RegMem on segment, control, debug, and test
 442         register flavors.
 443         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 444         to non-SSE2AVX flavor.
 445         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 446         Move RegMem on register only flavors. Drop IgnoreSize from
 447         legacy encoding flavors.
 448         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 449         flavors.
 450         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 451         register only flavors.
 452         (vmovd): Move RegMem and drop IgnoreSize on register only
 453         flavor. Change opcode and operand order to store form.
 454         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 455
 456 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 457
 458         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 459         entries.
 460         * i386-opc.h (SReg2, SReg3): Replace by ...
 461         (SReg): ... this.
 462         (union i386_operand_type): Replace sreg fields.
 463         * i386-opc.tbl (mov, ): Use SReg.
 464         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 465         register flavors.
 466         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 467         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 468
 469 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 470
 471         * bpf-desc.c: Regenerate.
 472         * bpf-opc.c: Likewise.
 473         * bpf-opc.h: Likewise.
 474
 475 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 476
 477         * bpf-desc.c: Regenerate.
 478         * bpf-opc.c: Likewise.
 479
 480 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 481
 482         * arm-dis.c (print_insn_coprocessor): Rename index to
 483         index_operand.
 484
 485 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 486
 487         * riscv-opc.c (riscv_insn_types): Add r4 type.
 488
 489         * riscv-opc.c (riscv_insn_types): Add b and j type.
 490
 491         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 492         format for sb type and correct s type.
 493
 494 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 495
 496         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 497         SVE FMOV alias of FCPY.
 498
 499 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 500
 501         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 502         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 503
 504 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 505
 506         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 507         registers in an instruction prefixed by MOVPRFX.
 508
 509 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 510
 511         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 512         sve_size_13 icode to account for variant behaviour of
 513         pmull{t,b}.
 514         * aarch64-dis-2.c: Regenerate.
 515         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 516         sve_size_13 icode to account for variant behaviour of
 517         pmull{t,b}.
 518         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 519         (OP_SVE_VVV_Q_D): Add new qualifier.
 520         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 521         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 522         AES and those not.
 523
 524 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 525
 526         * opcodes/i386-gen.c (operand_type_init): Remove
 527         OPERAND_TYPE_VEC_IMM4 entry.
 528         (operand_types): Remove Vec_Imm4.
 529         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 530         (union i386_operand_type): Remove vec_imm4.
 531         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 532         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 533
 534 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 535
 536         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 537         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 538         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 539         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 540         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 541         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 542         * i386-tbl.h: Re-generate.
 543
 544 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 545
 546         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 547         register operands.
 548         * i386-tbl.h: Re-generate.
 549
 550 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 551
 552         * i386-opc.tbl (C): New.
 553         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 554         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 555         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 556         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 557         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 558         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 559         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 560         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 561         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 562         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 563         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 564         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 565         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 566         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 567         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 568         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 569         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 570         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 571         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 572         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 573         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 574         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 575         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 576         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 577         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 578         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 579         flavors.
 580         * i386-tbl.h: Re-generate.
 581
 582 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 583
 584         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 585         register operands.
 586         * i386-tbl.h: Re-generate.
 587
 588 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 589
 590         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 591         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 592         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 593         * i386-tbl.h: Re-generate.
 594
 595 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 596
 597         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 598         Disp8MemShift from register only templates.
 599         * i386-tbl.h: Re-generate.
 600
 601 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 602
 603         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 604         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 605         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 606         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 607         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 608         EVEX_W_0F11_P_3_M_1): Delete.
 609         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 610         EVEX_W_0F11_P_3): New.
 611         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 612         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 613         MOD_EVEX_0F11_PREFIX_3 table entries.
 614         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 615         PREFIX_EVEX_0F11 table entries.
 616         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 617         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 618         EVEX_W_0F11_P_3_M_{0,1} table entries.
 619
 620 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 621
 622         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 623         Delete.
 624
 625 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 626
 627         PR binutils/24719
 628         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 629         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 630         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 631         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 632         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 633         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 634         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 635         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 636         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 637         PREFIX_EVEX_0F38C6_REG_6 entries.
 638         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 639         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 640         EVEX_W_0F38C7_R_6_P_2 entries.
 641         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 642         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 643         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 644         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 645         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 646         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 647         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 648
 649 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 650
 651         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 652         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 653         VEX_LEN_0F2D_P_3): Delete.
 654         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 655         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 656         (prefix_table): ... here.
 657
 658 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 659
 660         * i386-dis.c (Iq): Delete.
 661         (Id): New.
 662         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 663         TBM insns.
 664         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 665         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 666         (OP_E_memory): Also honor needindex when deciding whether an
 667         address size prefix needs printing.
 668         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 669
 670 2019-06-26  Jim Wilson  <jimw@sifive.com>
 671
 672         PR binutils/24739
 673         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 674         Set info->display_endian to info->endian_code.
 675
 676 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 677
 678         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 679         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 680         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 681         OPERAND_TYPE_ACC64 entries.
 682         * i386-init.h: Re-generate.
 683
 684 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 685
 686         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 687         Delete.
 688         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 689         of dqa_mode.
 690         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 691         entries here.
 692         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 693         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 694
 695 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 696
 697         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 698         variables.
 699
 700 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 701
 702         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 703         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 704         movnti.
 705         * i386-opc.tbl (movnti): Add IgnoreSize.
 706         * i386-tbl.h: Re-generate.
 707
 708 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 709
 710         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 711         * i386-tbl.h: Re-generate.
 712
 713 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 714
 715         * i386-dis-evex.h: Break into ...
 716         * i386-dis-evex-len.h: New file.
 717         * i386-dis-evex-mod.h: Likewise.
 718         * i386-dis-evex-prefix.h: Likewise.
 719         * i386-dis-evex-reg.h: Likewise.
 720         * i386-dis-evex-w.h: Likewise.
 721         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 722         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 723         i386-dis-evex-mod.h.
 724
 725 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 726
 727         PR binutils/24700
 728         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 729         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 730         EVEX_W_0F385B_P_2.
 731         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 732         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 733         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 734         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 735         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 736         EVEX_LEN_0F385B_P_2_W_1.
 737         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 738         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 739         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 740         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 741         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 742         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 743         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 744         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 745         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 746         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 747
 748 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 749
 750         PR binutils/24691
 751         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 752         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 753         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 754         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 755         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 756         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 757         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 758         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 759         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 760         EVEX_LEN_0F3A43_P_2_W_1.
 761         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 762         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 763         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 764         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 765         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 766         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 767         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 768         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 769         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 770         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 771         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 772         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 773
 774 2019-06-14  Nick Clifton  <nickc@redhat.com>
 775
 776         * po/fr.po; Updated French translation.
 777
 778 2019-06-13  Stafford Horne  <shorne@gmail.com>
 779
 780         * or1k-asm.c: Regenerated.
 781         * or1k-desc.c: Regenerated.
 782         * or1k-desc.h: Regenerated.
 783         * or1k-dis.c: Regenerated.
 784         * or1k-ibld.c: Regenerated.
 785         * or1k-opc.c: Regenerated.
 786         * or1k-opc.h: Regenerated.
 787         * or1k-opinst.c: Regenerated.
 788
 789 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 790
 791         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 792
 793 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 794
 795         PR binutils/24633
 796         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 797         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 798         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 799         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 800         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 801         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 802         EVEX_LEN_0F3A1B_P_2_W_1.
 803         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 804         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 805         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 806         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 807         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 808         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 809         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 810         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 811
 812 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 813
 814         PR binutils/24626
 815         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 816         EVEX.vvvv when disassembling VEX and EVEX instructions.
 817         (OP_VEX): Set vex.register_specifier to 0 after readding
 818         vex.register_specifier.
 819         (OP_Vex_2src_1): Likewise.
 820         (OP_Vex_2src_2): Likewise.
 821         (OP_LWP_E): Likewise.
 822         (OP_EX_Vex): Don't check vex.register_specifier.
 823         (OP_XMM_Vex): Likewise.
 824
 825 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 826             Lili Cui  <lili.cui@intel.com>
 827
 828         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 829         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 830         instructions.
 831         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 832         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 833         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 834         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 835         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 836         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 837         * i386-init.h: Regenerated.
 838         * i386-tbl.h: Likewise.
 839
 840 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 841             Lili Cui  <lili.cui@intel.com>
 842
 843         * doc/c-i386.texi: Document enqcmd.
 844         * testsuite/gas/i386/enqcmd-intel.d: New file.
 845         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 846         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 847         * testsuite/gas/i386/enqcmd.d: Likewise.
 848         * testsuite/gas/i386/enqcmd.s: Likewise.
 849         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 850         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 851         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 852         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 853         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 854         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 855         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 856         and x86-64-enqcmd.
 857
 858 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 859
 860         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 861
 862 2019-06-03  Alan Modra  <amodra@gmail.com>
 863
 864         * ppc-dis.c (prefix_opcd_indices): Correct size.
 865
 866 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 867
 868         PR gas/24625
 869         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 870         Disp8ShiftVL.
 871         * i386-tbl.h: Regenerated.
 872
 873 2019-05-24  Alan Modra  <amodra@gmail.com>
 874
 875         * po/POTFILES.in: Regenerate.
 876
 877 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 878             Alan Modra  <amodra@gmail.com>
 879
 880         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 881         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 882         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 883         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 884         XTOP>): Define and add entries.
 885         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 886         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 887         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 888         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 889
 890 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 891             Alan Modra  <amodra@gmail.com>
 892
 893         * ppc-dis.c (ppc_opts): Add "future" entry.
 894         (PREFIX_OPCD_SEGS): Define.
 895         (prefix_opcd_indices): New array.
 896         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 897         (lookup_prefix): New function.
 898         (print_insn_powerpc): Handle 64-bit prefix instructions.
 899         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 900         (PMRR, POWERXX): Define.
 901         (prefix_opcodes): New instruction table.
 902         (prefix_num_opcodes): New constant.
 903
 904 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 905
 906         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 907         * configure: Regenerated.
 908         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 909         and cpu/bpf.opc.
 910         (HFILES): Add bpf-desc.h and bpf-opc.h.
 911         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 912         bpf-ibld.c and bpf-opc.c.
 913         (BPF_DEPS): Define.
 914         * Makefile.in: Regenerated.
 915         * disassemble.c (ARCH_bpf): Define.
 916         (disassembler): Add case for bfd_arch_bpf.
 917         (disassemble_init_for_target): Likewise.
 918         (enum epbf_isa_attr): Define.
 919         * disassemble.h: extern print_insn_bpf.
 920         * bpf-asm.c: Generated.
 921         * bpf-opc.h: Likewise.
 922         * bpf-opc.c: Likewise.
 923         * bpf-ibld.c: Likewise.
 924         * bpf-dis.c: Likewise.
 925         * bpf-desc.h: Likewise.
 926         * bpf-desc.c: Likewise.
 927
 928 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 929
 930         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 931         and VMSR with the new operands.
 932
 933 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 934
 935         * arm-dis.c (enum mve_instructions): New enum
 936         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 937         and cneg.
 938         (mve_opcodes): New instructions as above.
 939         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 940         csneg and csel.
 941         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 942
 943 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 944
 945         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 946         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 947         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 948         uqshl, urshrl and urshr.
 949         (is_mve_okay_in_it): Add new instructions to TRUE list.
 950         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 951         (print_insn_mve): Updated to accept new %j,
 952         %<bitfield>m and %<bitfield>n patterns.
 953
 954 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 955
 956         * mips-opc.c (mips_builtin_opcodes): Change source register
 957         constraint for DAUI.
 958
 959 2019-05-20  Nick Clifton  <nickc@redhat.com>
 960
 961         * po/fr.po: Updated French translation.
 962
 963 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 964             Michael Collison <michael.collison@arm.com>
 965
 966         * arm-dis.c (thumb32_opcodes): Add new instructions.
 967         (enum mve_instructions): Likewise.
 968         (enum mve_undefined): Add new reasons.
 969         (is_mve_encoding_conflict): Handle new instructions.
 970         (is_mve_undefined): Likewise.
 971         (is_mve_unpredictable): Likewise.
 972         (print_mve_undefined): Likewise.
 973         (print_mve_size): Likewise.
 974
 975 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 976             Michael Collison <michael.collison@arm.com>
 977
 978         * arm-dis.c (thumb32_opcodes): Add new instructions.
 979         (enum mve_instructions): Likewise.
 980         (is_mve_encoding_conflict): Handle new instructions.
 981         (is_mve_undefined): Likewise.
 982         (is_mve_unpredictable): Likewise.
 983         (print_mve_size): Likewise.
 984
 985 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 986             Michael Collison <michael.collison@arm.com>
 987
 988         * arm-dis.c (thumb32_opcodes): Add new instructions.
 989         (enum mve_instructions): Likewise.
 990         (is_mve_encoding_conflict): Likewise.
 991         (is_mve_unpredictable): Likewise.
 992         (print_mve_size): Likewise.
 993
 994 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 995             Michael Collison <michael.collison@arm.com>
 996
 997         * arm-dis.c (thumb32_opcodes): Add new instructions.
 998         (enum mve_instructions): Likewise.
 999         (is_mve_encoding_conflict): Handle new instructions.
1000         (is_mve_undefined): Likewise.
1001         (is_mve_unpredictable): Likewise.
1002         (print_mve_size): Likewise.
1003
1004 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1005             Michael Collison <michael.collison@arm.com>
1006
1007         * arm-dis.c (thumb32_opcodes): Add new instructions.
1008         (enum mve_instructions): Likewise.
1009         (is_mve_encoding_conflict): Handle new instructions.
1010         (is_mve_undefined): Likewise.
1011         (is_mve_unpredictable): Likewise.
1012         (print_mve_size): Likewise.
1013         (print_insn_mve): Likewise.
1014
1015 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1016             Michael Collison <michael.collison@arm.com>
1017
1018         * arm-dis.c (thumb32_opcodes): Add new instructions.
1019         (print_insn_thumb32): Handle new instructions.
1020
1021 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1022             Michael Collison <michael.collison@arm.com>
1023
1024         * arm-dis.c (enum mve_instructions): Add new instructions.
1025         (enum mve_undefined): Add new reasons.
1026         (is_mve_encoding_conflict): Handle new instructions.
1027         (is_mve_undefined): Likewise.
1028         (is_mve_unpredictable): Likewise.
1029         (print_mve_undefined): Likewise.
1030         (print_mve_size): Likewise.
1031         (print_mve_shift_n): Likewise.
1032         (print_insn_mve): Likewise.
1033
1034 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1035             Michael Collison <michael.collison@arm.com>
1036
1037         * arm-dis.c (enum mve_instructions): Add new instructions.
1038         (is_mve_encoding_conflict): Handle new instructions.
1039         (is_mve_unpredictable): Likewise.
1040         (print_mve_rotate): Likewise.
1041         (print_mve_size): Likewise.
1042         (print_insn_mve): Likewise.
1043
1044 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1045             Michael Collison <michael.collison@arm.com>
1046
1047         * arm-dis.c (enum mve_instructions): Add new instructions.
1048         (is_mve_encoding_conflict): Handle new instructions.
1049         (is_mve_unpredictable): Likewise.
1050         (print_mve_size): Likewise.
1051         (print_insn_mve): Likewise.
1052
1053 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1054             Michael Collison <michael.collison@arm.com>
1055
1056         * arm-dis.c (enum mve_instructions): Add new instructions.
1057         (enum mve_undefined): Add new reasons.
1058         (is_mve_encoding_conflict): Handle new instructions.
1059         (is_mve_undefined): Likewise.
1060         (is_mve_unpredictable): Likewise.
1061         (print_mve_undefined): Likewise.
1062         (print_mve_size): Likewise.
1063         (print_insn_mve): Likewise.
1064
1065 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1066             Michael Collison <michael.collison@arm.com>
1067
1068         * arm-dis.c (enum mve_instructions): Add new instructions.
1069         (is_mve_encoding_conflict): Handle new instructions.
1070         (is_mve_undefined): Likewise.
1071         (is_mve_unpredictable): Likewise.
1072         (print_mve_size): Likewise.
1073         (print_insn_mve): Likewise.
1074
1075 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1076             Michael Collison <michael.collison@arm.com>
1077
1078         * arm-dis.c (enum mve_instructions): Add new instructions.
1079         (enum mve_unpredictable): Add new reasons.
1080         (enum mve_undefined): Likewise.
1081         (is_mve_okay_in_it): Handle new isntructions.
1082         (is_mve_encoding_conflict): Likewise.
1083         (is_mve_undefined): Likewise.
1084         (is_mve_unpredictable): Likewise.
1085         (print_mve_vmov_index): Likewise.
1086         (print_simd_imm8): Likewise.
1087         (print_mve_undefined): Likewise.
1088         (print_mve_unpredictable): Likewise.
1089         (print_mve_size): Likewise.
1090         (print_insn_mve): Likewise.
1091
1092 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1093             Michael Collison <michael.collison@arm.com>
1094
1095         * arm-dis.c (enum mve_instructions): Add new instructions.
1096         (enum mve_unpredictable): Add new reasons.
1097         (enum mve_undefined): Likewise.
1098         (is_mve_encoding_conflict): Handle new instructions.
1099         (is_mve_undefined): Likewise.
1100         (is_mve_unpredictable): Likewise.
1101         (print_mve_undefined): Likewise.
1102         (print_mve_unpredictable): Likewise.
1103         (print_mve_rounding_mode): Likewise.
1104         (print_mve_vcvt_size): Likewise.
1105         (print_mve_size): Likewise.
1106         (print_insn_mve): Likewise.
1107
1108 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1109             Michael Collison <michael.collison@arm.com>
1110
1111         * arm-dis.c (enum mve_instructions): Add new instructions.
1112         (enum mve_unpredictable): Add new reasons.
1113         (enum mve_undefined): Likewise.
1114         (is_mve_undefined): Handle new instructions.
1115         (is_mve_unpredictable): Likewise.
1116         (print_mve_undefined): Likewise.
1117         (print_mve_unpredictable): Likewise.
1118         (print_mve_size): Likewise.
1119         (print_insn_mve): Likewise.
1120
1121 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1122             Michael Collison <michael.collison@arm.com>
1123
1124         * arm-dis.c (enum mve_instructions): Add new instructions.
1125         (enum mve_undefined): Add new reasons.
1126         (insns): Add new instructions.
1127         (is_mve_encoding_conflict):
1128         (print_mve_vld_str_addr): New print function.
1129         (is_mve_undefined): Handle new instructions.
1130         (is_mve_unpredictable): Likewise.
1131         (print_mve_undefined): Likewise.
1132         (print_mve_size): Likewise.
1133         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1134         (print_insn_mve):  Handle new operands.
1135
1136 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1137             Michael Collison <michael.collison@arm.com>
1138
1139         * arm-dis.c (enum mve_instructions): Add new instructions.
1140         (enum mve_unpredictable): Add new reasons.
1141         (is_mve_encoding_conflict): Handle new instructions.
1142         (is_mve_unpredictable): Likewise.
1143         (mve_opcodes): Add new instructions.
1144         (print_mve_unpredictable): Handle new reasons.
1145         (print_mve_register_blocks): New print function.
1146         (print_mve_size): Handle new instructions.
1147         (print_insn_mve): Likewise.
1148
1149 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1150             Michael Collison <michael.collison@arm.com>
1151
1152         * arm-dis.c (enum mve_instructions): Add new instructions.
1153         (enum mve_unpredictable): Add new reasons.
1154         (enum mve_undefined): Likewise.
1155         (is_mve_encoding_conflict): Handle new instructions.
1156         (is_mve_undefined): Likewise.
1157         (is_mve_unpredictable): Likewise.
1158         (coprocessor_opcodes): Move NEON VDUP from here...
1159         (neon_opcodes): ... to here.
1160         (mve_opcodes): Add new instructions.
1161         (print_mve_undefined):  Handle new reasons.
1162         (print_mve_unpredictable): Likewise.
1163         (print_mve_size): Handle new instructions.
1164         (print_insn_neon): Handle vdup.
1165         (print_insn_mve): Handle new operands.
1166
1167 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1168             Michael Collison <michael.collison@arm.com>
1169
1170         * arm-dis.c (enum mve_instructions): Add new instructions.
1171         (enum mve_unpredictable): Add new values.
1172         (mve_opcodes): Add new instructions.
1173         (vec_condnames): New array with vector conditions.
1174         (mve_predicatenames): New array with predicate suffixes.
1175         (mve_vec_sizename): New array with vector sizes.
1176         (enum vpt_pred_state): New enum with vector predication states.
1177         (struct vpt_block): New struct type for vpt blocks.
1178         (vpt_block_state): Global struct to keep track of state.
1179         (mve_extract_pred_mask): New helper function.
1180         (num_instructions_vpt_block): Likewise.
1181         (mark_outside_vpt_block): Likewise.
1182         (mark_inside_vpt_block): Likewise.
1183         (invert_next_predicate_state): Likewise.
1184         (update_next_predicate_state): Likewise.
1185         (update_vpt_block_state): Likewise.
1186         (is_vpt_instruction): Likewise.
1187         (is_mve_encoding_conflict): Add entries for new instructions.
1188         (is_mve_unpredictable): Likewise.
1189         (print_mve_unpredictable): Handle new cases.
1190         (print_instruction_predicate): Likewise.
1191         (print_mve_size): New function.
1192         (print_vec_condition): New function.
1193         (print_insn_mve): Handle vpt blocks and new print operands.
1194
1195 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1196
1197         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1198         8, 14 and 15 for Armv8.1-M Mainline.
1199
1200 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1201             Michael Collison <michael.collison@arm.com>
1202
1203         * arm-dis.c (enum mve_instructions): New enum.
1204         (enum mve_unpredictable): Likewise.
1205         (enum mve_undefined): Likewise.
1206         (struct mopcode32): New struct.
1207         (is_mve_okay_in_it): New function.
1208         (is_mve_architecture): Likewise.
1209         (arm_decode_field): Likewise.
1210         (arm_decode_field_multiple): Likewise.
1211         (is_mve_encoding_conflict): Likewise.
1212         (is_mve_undefined): Likewise.
1213         (is_mve_unpredictable): Likewise.
1214         (print_mve_undefined): Likewise.
1215         (print_mve_unpredictable): Likewise.
1216         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1217         (print_insn_mve): New function.
1218         (print_insn_thumb32): Handle MVE architecture.
1219         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1220
1221 2019-05-10  Nick Clifton  <nickc@redhat.com>
1222
1223         PR 24538
1224         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1225         end of the table prematurely.
1226
1227 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1228
1229         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1230         macros for R6.
1231
1232 2019-05-11  Alan Modra  <amodra@gmail.com>
1233
1234         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1235         when -Mraw is in effect.
1236
1237 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1238
1239         * aarch64-dis-2.c: Regenerate.
1240         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1241         (OP_SVE_BBB): New variant set.
1242         (OP_SVE_DDDD): New variant set.
1243         (OP_SVE_HHH): New variant set.
1244         (OP_SVE_HHHU): New variant set.
1245         (OP_SVE_SSS): New variant set.
1246         (OP_SVE_SSSU): New variant set.
1247         (OP_SVE_SHH): New variant set.
1248         (OP_SVE_SBBU): New variant set.
1249         (OP_SVE_DSS): New variant set.
1250         (OP_SVE_DHHU): New variant set.
1251         (OP_SVE_VMV_HSD_BHS): New variant set.
1252         (OP_SVE_VVU_HSD_BHS): New variant set.
1253         (OP_SVE_VVVU_SD_BH): New variant set.
1254         (OP_SVE_VVVU_BHSD): New variant set.
1255         (OP_SVE_VVV_QHD_DBS): New variant set.
1256         (OP_SVE_VVV_HSD_BHS): New variant set.
1257         (OP_SVE_VVV_HSD_BHS2): New variant set.
1258         (OP_SVE_VVV_BHS_HSD): New variant set.
1259         (OP_SVE_VV_BHS_HSD): New variant set.
1260         (OP_SVE_VVV_SD): New variant set.
1261         (OP_SVE_VVU_BHS_HSD): New variant set.
1262         (OP_SVE_VZVV_SD): New variant set.
1263         (OP_SVE_VZVV_BH): New variant set.
1264         (OP_SVE_VZV_SD): New variant set.
1265         (aarch64_opcode_table): Add sve2 instructions.
1266
1267 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1268
1269         * aarch64-asm-2.c: Regenerated.
1270         * aarch64-dis-2.c: Regenerated.
1271         * aarch64-opc-2.c: Regenerated.
1272         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1273         for SVE_SHLIMM_UNPRED_22.
1274         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1275         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1276         operand.
1277
1278 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1279
1280         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1281         sve_size_tsz_bhs iclass encode.
1282         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1283         sve_size_tsz_bhs iclass decode.
1284
1285 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1286
1287         * aarch64-asm-2.c: Regenerated.
1288         * aarch64-dis-2.c: Regenerated.
1289         * aarch64-opc-2.c: Regenerated.
1290         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1291         for SVE_Zm4_11_INDEX.
1292         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1293         (fields): Handle SVE_i2h field.
1294         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1295         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1296
1297 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1298
1299         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1300         sve_shift_tsz_bhsd iclass encode.
1301         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1302         sve_shift_tsz_bhsd iclass decode.
1303
1304 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1305
1306         * aarch64-asm-2.c: Regenerated.
1307         * aarch64-dis-2.c: Regenerated.
1308         * aarch64-opc-2.c: Regenerated.
1309         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1310         (aarch64_encode_variant_using_iclass): Handle
1311         sve_shift_tsz_hsd iclass encode.
1312         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1313         sve_shift_tsz_hsd iclass decode.
1314         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1315         for SVE_SHRIMM_UNPRED_22.
1316         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1317         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1318         operand.
1319
1320 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1321
1322         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1323         sve_size_013 iclass encode.
1324         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1325         sve_size_013 iclass decode.
1326
1327 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1328
1329         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1330         sve_size_bh iclass encode.
1331         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1332         sve_size_bh iclass decode.
1333
1334 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1335
1336         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1337         sve_size_sd2 iclass encode.
1338         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1339         sve_size_sd2 iclass decode.
1340         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1341         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1342
1343 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1344
1345         * aarch64-asm-2.c: Regenerated.
1346         * aarch64-dis-2.c: Regenerated.
1347         * aarch64-opc-2.c: Regenerated.
1348         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1349         for SVE_ADDR_ZX.
1350         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1351         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1352
1353 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1354
1355         * aarch64-asm-2.c: Regenerated.
1356         * aarch64-dis-2.c: Regenerated.
1357         * aarch64-opc-2.c: Regenerated.
1358         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1359         for SVE_Zm3_11_INDEX.
1360         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1361         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1362         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1363         fields.
1364         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1365
1366 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1367
1368         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1369         sve_size_hsd2 iclass encode.
1370         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1371         sve_size_hsd2 iclass decode.
1372         * aarch64-opc.c (fields): Handle SVE_size field.
1373         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1374
1375 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1376
1377         * aarch64-asm-2.c: Regenerated.
1378         * aarch64-dis-2.c: Regenerated.
1379         * aarch64-opc-2.c: Regenerated.
1380         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1381         for SVE_IMM_ROT3.
1382         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1383         (fields): Handle SVE_rot3 field.
1384         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1385         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1386
1387 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1388
1389         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1390         instructions.
1391
1392 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1393
1394         * aarch64-tbl.h
1395         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1396         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1397         aarch64_feature_sve2bitperm): New feature sets.
1398         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1399         for feature set addresses.
1400         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1401         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1402
1403 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1404             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1405
1406         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1407         argument and set ASE_EVA_R6 appropriately.
1408         (set_default_mips_dis_options): Pass ISA to above.
1409         (parse_mips_dis_option): Likewise.
1410         * mips-opc.c (EVAR6): New macro.
1411         (mips_builtin_opcodes): Add llwpe, scwpe.
1412
1413 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1414
1415         * aarch64-asm-2.c: Regenerated.
1416         * aarch64-dis-2.c: Regenerated.
1417         * aarch64-opc-2.c: Regenerated.
1418         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1419         AARCH64_OPND_TME_UIMM16.
1420         (aarch64_print_operand): Likewise.
1421         * aarch64-tbl.h (QL_IMM_NIL): New.
1422         (TME): New.
1423         (_TME_INSN): New.
1424         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1425
1426 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1427
1428         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1429
1430 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1431             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1432
1433         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1434
1435 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1436
1437         * s12z-opc.h: Add extern "C" bracketing to help
1438         users who wish to use this interface in c++ code.
1439
1440 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1441
1442         * s12z-opc.c (bm_decode): Handle bit map operations with the
1443         "reserved0" mode.
1444
1445 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1446
1447         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1448         specifier.  Add entries for VLDR and VSTR of system registers.
1449         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1450         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1451         of %J and %K format specifier.
1452
1453 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1454
1455         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1456         Add new entries for VSCCLRM instruction.
1457         (print_insn_coprocessor): Handle new %C format control code.
1458
1459 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1460
1461         * arm-dis.c (enum isa): New enum.
1462         (struct sopcode32): New structure.
1463         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1464         set isa field of all current entries to ANY.
1465         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1466         Only match an entry if its isa field allows the current mode.
1467
1468 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1469
1470         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1471         CLRM.
1472         (print_insn_thumb32): Add logic to print %n CLRM register list.
1473
1474 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1475
1476         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1477         and %Q patterns.
1478
1479 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1480
1481         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1482         (print_insn_thumb32): Edit the switch case for %Z.
1483
1484 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1485
1486         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1487
1488 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1489
1490         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1491
1492 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1493
1494         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1495
1496 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1497
1498         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1499         Arm register with r13 and r15 unpredictable.
1500         (thumb32_opcodes): New instructions for bfx and bflx.
1501
1502 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1503
1504         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1505
1506 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1507
1508         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1509
1510 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1511
1512         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1513
1514 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1515
1516         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1517
1518 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1519
1520         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1521         "optr". ("operator" is a reserved word in c++).
1522
1523 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1524
1525         * aarch64-opc.c (aarch64_print_operand): Add case for
1526         AARCH64_OPND_Rt_SP.
1527         (verify_constraints): Likewise.
1528         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1529         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1530         to accept Rt|SP as first operand.
1531         (AARCH64_OPERANDS): Add new Rt_SP.
1532         * aarch64-asm-2.c: Regenerated.
1533         * aarch64-dis-2.c: Regenerated.
1534         * aarch64-opc-2.c: Regenerated.
1535
1536 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1537
1538         * aarch64-asm-2.c: Regenerated.
1539         * aarch64-dis-2.c: Likewise.
1540         * aarch64-opc-2.c: Likewise.
1541         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1542
1543 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1544
1545         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1546
1547 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1548
1549         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1550         * i386-init.h: Regenerated.
1551
1552 2019-04-07  Alan Modra  <amodra@gmail.com>
1553
1554         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1555         op_separator to control printing of spaces, comma and parens
1556         rather than need_comma, need_paren and spaces vars.
1557
1558 2019-04-07  Alan Modra  <amodra@gmail.com>
1559
1560         PR 24421
1561         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1562         (print_insn_neon, print_insn_arm): Likewise.
1563
1564 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1565
1566         * i386-dis-evex.h (evex_table): Updated to support BF16
1567         instructions.
1568         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1569         and EVEX_W_0F3872_P_3.
1570         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1571         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1572         * i386-opc.h (enum): Add CpuAVX512_BF16.
1573         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1574         * i386-opc.tbl: Add AVX512 BF16 instructions.
1575         * i386-init.h: Regenerated.
1576         * i386-tbl.h: Likewise.
1577
1578 2019-04-05  Alan Modra  <amodra@gmail.com>
1579
1580         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1581         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1582         to favour printing of "-" branch hint when using the "y" bit.
1583         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1584
1585 2019-04-05  Alan Modra  <amodra@gmail.com>
1586
1587         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1588         opcode until first operand is output.
1589
1590 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1591
1592         PR gas/24349
1593         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1594         (valid_bo_post_v2): Add support for 'at' branch hints.
1595         (insert_bo): Only error on branch on ctr.
1596         (get_bo_hint_mask): New function.
1597         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1598         for inserting 'at' branch hints.
1599         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1600         for extracting 'at' branch hints.
1601         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1602         (BOE): Delete operand.
1603         (BOM, BOP): New operands.
1604         (RM): Update value.
1605         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1606         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1607         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1608         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1609         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1610         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1611         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1612         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1613         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1614         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1615         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1616         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1617         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1618         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1619         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1620         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1621         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1622         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1623         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1624         bttarl+>: New extended mnemonics.
1625
1626 2019-03-28  Alan Modra  <amodra@gmail.com>
1627
1628         PR 24390
1629         * ppc-opc.c (BTF): Define.
1630         (powerpc_opcodes): Use for mtfsb*.
1631         * ppc-dis.c (print_insn_powerpc): Print fields with both
1632         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1633
1634 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1635
1636         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1637         (mapping_symbol_for_insn): Implement new algorithm.
1638         (print_insn): Remove duplicate code.
1639
1640 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1641
1642         * aarch64-dis.c (print_insn_aarch64):
1643         Implement override.
1644
1645 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1646
1647         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1648         order.
1649
1650 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1651
1652         * aarch64-dis.c (last_stop_offset): New.
1653         (print_insn_aarch64): Use stop_offset.
1654
1655 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1656
1657         PR gas/24359
1658         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1659         CPU_ANY_AVX2_FLAGS.
1660         * i386-init.h: Regenerated.
1661
1662 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1663
1664         PR gas/24348
1665         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1666         vmovdqu16, vmovdqu32 and vmovdqu64.
1667         * i386-tbl.h: Regenerated.
1668
1669 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1670
1671         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1672         from vstrszb, vstrszh, and vstrszf.
1673
1674 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1675
1676         * s390-opc.txt: Add instruction descriptions.
1677
1678 2019-02-08  Jim Wilson  <jimw@sifive.com>
1679
1680         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1681         <bne>: Likewise.
1682
1683 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1684
1685         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1686
1687 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1688
1689         PR binutils/23212
1690         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1691         * aarch64-opc.c (verify_elem_sd): New.
1692         (fields): Add FLD_sz entr.
1693         * aarch64-tbl.h (_SIMD_INSN): New.
1694         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1695         fmulx scalar and vector by element isns.
1696
1697 2019-02-07  Nick Clifton  <nickc@redhat.com>
1698
1699         * po/sv.po: Updated Swedish translation.
1700
1701 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1702
1703         * s390-mkopc.c (main): Accept arch13 as cpu string.
1704         * s390-opc.c: Add new instruction formats and instruction opcode
1705         masks.
1706         * s390-opc.txt: Add new arch13 instructions.
1707
1708 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1709
1710         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1711         (aarch64_opcode): Change encoding for stg, stzg
1712         st2g and st2zg.
1713         * aarch64-asm-2.c: Regenerated.
1714         * aarch64-dis-2.c: Regenerated.
1715         * aarch64-opc-2.c: Regenerated.
1716
1717 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1718
1719         * aarch64-asm-2.c: Regenerated.
1720         * aarch64-dis-2.c: Likewise.
1721         * aarch64-opc-2.c: Likewise.
1722         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1723
1724 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1725             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1726
1727         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1728         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1729         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1730         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1731         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1732         case for ldstgv_indexed.
1733         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1734         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1735         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1736         * aarch64-asm-2.c: Regenerated.
1737         * aarch64-dis-2.c: Regenerated.
1738         * aarch64-opc-2.c: Regenerated.
1739
1740 2019-01-23  Nick Clifton  <nickc@redhat.com>
1741
1742         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1743
1744 2019-01-21  Nick Clifton  <nickc@redhat.com>
1745
1746         * po/de.po: Updated German translation.
1747         * po/uk.po: Updated Ukranian translation.
1748
1749 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1750         * mips-dis.c (mips_arch_choices): Fix typo in
1751         gs464, gs464e and gs264e descriptors.
1752
1753 2019-01-19  Nick Clifton  <nickc@redhat.com>
1754
1755         * configure: Regenerate.
1756         * po/opcodes.pot: Regenerate.
1757
1758 2018-06-24  Nick Clifton  <nickc@redhat.com>
1759
1760         2.32 branch created.
1761
1762 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1763
1764         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1765         if it is null.
1766         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1767         zero.
1768
1769 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1770
1771         * configure: Regenerate.
1772
1773 2019-01-07  Alan Modra  <amodra@gmail.com>
1774
1775         * configure: Regenerate.
1776         * po/POTFILES.in: Regenerate.
1777
1778 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1779
1780         * s12z-opc.c: New file.
1781         * s12z-opc.h: New file.
1782         * s12z-dis.c: Removed all code not directly related to display
1783         of instructions.  Used the interface provided by the new files
1784         instead.
1785         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1786         * Makefile.in: Regenerate.
1787         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1788         * configure: Regenerate.
1789
1790 2019-01-01  Alan Modra  <amodra@gmail.com>
1791
1792         Update year range in copyright notice of all files.
1793
1794 For older changes see ChangeLog-2018
1795 \f
1796 Copyright (C) 2019 Free Software Foundation, Inc.
1797
1798 Copying and distribution of this file, with or without modification,
1799 are permitted in any medium without royalty provided the copyright
1800 notice and this notice are preserved.
1801
1802 Local Variables:
1803 mode: change-log
1804 left-margin: 8
1805 fill-column: 74
1806 version-control: never
1807 End: