opcodes/ChangeLog

   1 2018-10-19  Tamar Christina  <tamar.christina@arm.com>
   2
   3         * arm-dis.c (UNKNOWN_INSTRUCTION_32BIT): Format specifier for arm mode.
   4         (UNKNOWN_INSTRUCTION_16BIT): Format specifier for thumb mode.
   5         (print_insn_arm, print_insn_thumb16, print_insn_thumb32): Use them.
   6
   7 2018-10-16  Matthew Malcomson  <matthew.malcomson@arm.com>
   8
   9         * aarch64-opc.c (struct operand_qualifier_data): Change qualifier data
  10         corresponding to AARCH64_OPND_QLF_S_4B qualifier.
  11
  12 2018-10-10  Jan Beulich  <jbeulich@suse.com>
  13
  14         * i386-gen.c (opcode_modifiers): Drop Size16, Size32, and
  15         Size64. Add Size.
  16         * i386-opc.h (Size16, Size32, Size64): Delete.
  17         (Size): New.
  18         (SIZE16, SIZE32, SIZE64): Define.
  19         (struct i386_opcode_modifier): Drop size16, size32, and size64.
  20         Add size.
  21         * i386-opc.tbl (Size16, Size32, Size64): Define.
  22         * i386-tbl.h: Re-generate.
  23
  24 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  25
  26         * aarch64-opc.c (operand_general_constraint_met_p): Add
  27         SSBS in the check for one-bit immediate.
  28         (aarch64_sys_regs): New entry for SSBS.
  29         (aarch64_sys_reg_supported_p): New check for above.
  30         (aarch64_pstatefields): New entry for SSBS.
  31         (aarch64_pstatefield_supported_p): New check for above.
  32
  33 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  34
  35         * aarch64-opc.c (aarch64_sys_regs): New entries for
  36         scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
  37         (aarch64_sys_reg_supported_p): New checks for above.
  38
  39 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  40
  41         * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
  42         (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
  43         with the hint immediate.
  44         * aarch64-opc.c (aarch64_hint_options): New entries for
  45         c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
  46         (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
  47         while checking for HINT_OPD_F_NOPRINT flag.
  48         * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
  49         extract value.
  50         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
  51         (aarch64_opcode_table): Add entry for BTI.
  52         (AARCH64_OPERANDS): Add new description for BTI targets.
  53         * aarch64-asm-2.c: Regenerate.
  54         * aarch64-dis-2.c: Regenerate.
  55         * aarch64-opc-2.c: Regenerate.
  56
  57 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  58
  59         * aarch64-opc.c (aarch64_sys_regs): New entries for
  60         rndr and rndrrs.
  61         (aarch64_sys_reg_supported_p): New check for above.
  62
  63 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  64
  65         * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
  66         (aarch64_sys_ins_reg_supported_p): New check for above.
  67
  68 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  69
  70         * aarch64-dis.c (aarch64_ext_sysins_op): Add case for
  71         AARCH64_OPND_SYSREG_SR.
  72         * aarch64-opc.c (aarch64_print_operand): Likewise.
  73         (aarch64_sys_regs_sr): Define table.
  74         (aarch64_sys_ins_reg_supported_p): Check for RCTX with
  75         AARCH64_FEATURE_PREDRES.
  76         * aarch64-tbl.h (aarch64_feature_predres): New.
  77         (PREDRES, PREDRES_INSN): New.
  78         (aarch64_opcode_table): Add entries for cfp, dvp and cpp.
  79         (AARCH64_OPERANDS): Add new description for SYSREG_SR.
  80         * aarch64-asm-2.c: Regenerate.
  81         * aarch64-dis-2.c: Regenerate.
  82         * aarch64-opc-2.c: Regenerate.
  83
  84 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  85
  86         * aarch64-tbl.h (aarch64_feature_sb): New.
  87         (SB, SB_INSN): New.
  88         (aarch64_opcode_table): Add entry for sb.
  89         * aarch64-asm-2.c: Regenerate.
  90         * aarch64-dis-2.c: Regenerate.
  91         * aarch64-opc-2.c: Regenerate.
  92
  93 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
  94
  95         * aarch64-tbl.h (aarch64_feature_flagmanip): New.
  96         (aarch64_feature_frintts): New.
  97         (FLAGMANIP, FRINTTS): New.
  98         (aarch64_opcode_table): Add entries for xaflag, axflag
  99         and frint[32,64][x,z] instructions.
 100         * aarch64-asm-2.c: Regenerate.
 101         * aarch64-dis-2.c: Regenerate.
 102         * aarch64-opc-2.c: Regenerate.
 103
 104 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 105
 106         * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
 107         (ARMV8_5, V8_5_INSN): New.
 108
 109 2018-10-08  Tamar Christina  <tamar.christina@arm.com>
 110
 111         * aarch64-opc.c (verify_constraints): Use memset instead of {0}.
 112
 113 2018-10-05  H.J. Lu  <hongjiu.lu@intel.com>
 114
 115         * i386-dis.c (rm_table): Add enclv.
 116         * i386-opc.tbl: Add enclv.
 117         * i386-tbl.h: Regenerated.
 118
 119 2018-10-05  Sudakshina Das  <sudi.das@arm.com>
 120
 121         * arm-dis.c (arm_opcodes): Add sb.
 122         (thumb32_opcodes): Likewise.
 123
 124 2018-10-05  Richard Henderson  <rth@twiddle.net>
 125             Stafford Horne  <shorne@gmail.com>
 126
 127         * or1k-desc.c: Regenerate.
 128         * or1k-desc.h: Regenerate.
 129         * or1k-opc.c: Regenerate.
 130         * or1k-opc.h: Regenerate.
 131         * or1k-opinst.c: Regenerate.
 132
 133 2018-10-05  Richard Henderson  <rth@twiddle.net>
 134
 135         * or1k-asm.c: Regenerated.
 136         * or1k-desc.c: Regenerated.
 137         * or1k-desc.h: Regenerated.
 138         * or1k-dis.c: Regenerated.
 139         * or1k-ibld.c: Regenerated.
 140         * or1k-opc.c: Regenerated.
 141         * or1k-opc.h: Regenerated.
 142         * or1k-opinst.c: Regenerated.
 143
 144 2018-10-05  Richard Henderson  <rth@twiddle.net>
 145
 146         * or1k-asm.c: Regenerate.
 147
 148 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 149
 150         * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
 151         * aarch64-dis.c (print_operands): Refactor to take notes.
 152         (print_verifier_notes): New.
 153         (print_aarch64_insn): Apply constraint verifier.
 154         (print_insn_aarch64_word): Update call to print_aarch64_insn.
 155         * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
 156
 157 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 158
 159         * aarch64-opc.c (init_insn_block): New.
 160         (verify_constraints, aarch64_is_destructive_by_operands): New.
 161         * aarch64-opc.h (verify_constraints): New.
 162
 163 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 164
 165         * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
 166         * aarch64-opc.c (verify_ldpsw): Update arguments.
 167
 168 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 169
 170         * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
 171         (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
 172
 173 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 174
 175         * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
 176         * aarch64-dis.c (insn_sequence): New.
 177
 178 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 179
 180         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
 181         _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
 182         _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
 183         V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
 184         constraints.
 185         (_SVE_INSNC): New.
 186         (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
 187         constraints.
 188         (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
 189         F_SCAN flags.
 190         (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
 191         sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
 192         sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
 193         sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
 194         uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
 195         uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
 196         C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
 197
 198 2018-10-02  Palmer Dabbelt  <palmer@sifive.com>
 199
 200         * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
 201
 202 2018-09-23  Sandra Loosemore  <sandra@codesourcery.com>
 203
 204         * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
 205         are used when extracting signed fields and converting them to
 206         potentially 64-bit types.
 207
 208 2018-09-21  Simon Marchi  <simon.marchi@ericsson.com>
 209
 210         * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
 211         * Makefile.in: Re-generate.
 212         * aclocal.m4: Re-generate.
 213         * configure: Re-generate.
 214         * configure.ac: Remove check for -Wno-missing-field-initializers.
 215         * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
 216         (csky_v2_opcodes): Likewise.
 217
 218 2018-09-20  Maciej W. Rozycki  <macro@linux-mips.org>
 219
 220         * arc-nps400-tbl.h: Append `ull' to large constants throughout.
 221
 222 2018-09-20  Nelson Chu <nelson.chu1990@gmail.com>
 223
 224         * nds32-asm.c (operand_fields): Remove the unused fields.
 225         (nds32_opcodes): Remove the unused instructions.
 226         * nds32-dis.c (nds32_ex9_info): Removed.
 227         (nds32_parse_opcode): Updated.
 228         (print_insn_nds32): Likewise.
 229         * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
 230         (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
 231         (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
 232         build_opcode_hash_table): New functions.
 233         (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
 234         nds32_opcode_table): New.
 235         (hw_ktabs): Declare it to a pointer rather than an array.
 236         (build_hash_table): Removed.
 237         * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
 238         SYN_ROPT and upadte HW_GPR and HW_INT.
 239         * nds32-dis.c (keywords): Remove const.
 240         (match_field): New function.
 241         (nds32_parse_opcode): Updated.
 242         * disassemble.c (disassemble_init_for_target):
 243         Add disassemble_init_nds32.
 244         * nds32-dis.c (eum map_type): New.
 245         (nds32_private_data): Likewise.
 246         (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
 247         nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
 248         (print_insn_nds32): Updated.
 249         * nds32-asm.c (parse_aext_reg): Add new parameter.
 250         (parse_re, parse_re2, parse_aext_reg): Only reduced registers
 251         are allowed to use.
 252         All callers changed.
 253         * nds32-asm.c (keyword_usr, keyword_sr): Updated.
 254         (operand_fields): Add new fields.
 255         (nds32_opcodes): Add new instructions.
 256         (keyword_aridxi_mx): New keyword.
 257         * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
 258         and NASM_ATTR_ZOL.
 259         (ALU2_1, ALU2_2, ALU2_3): New macros.
 260         * nds32-dis.c (nds32_filter_unknown_insn): Updated.
 261
 262 2018-09-17  Kito Cheng  <kito@andestech.com>
 263
 264         * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
 265
 266 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 267
 268         PR gas/23670
 269         * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
 270         EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
 271         (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
 272         (EVEX_LEN_0F7E_P_1): Likewise.
 273         (EVEX_LEN_0F7E_P_2): Likewise.
 274         (EVEX_LEN_0FD6_P_2): Likewise.
 275         * i386-dis.c (USE_EVEX_LEN_TABLE): New.
 276         (EVEX_LEN_TABLE): Likewise.
 277         (EVEX_LEN_0F6E_P_2): New enum.
 278         (EVEX_LEN_0F7E_P_1): Likewise.
 279         (EVEX_LEN_0F7E_P_2): Likewise.
 280         (EVEX_LEN_0FD6_P_2): Likewise.
 281         (evex_len_table): New.
 282         (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
 283         * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
 284         * i386-tbl.h: Regenerated.
 285
 286 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 287
 288         PR gas/23665
 289         * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
 290         VEX_LEN_0F7E_P_2 entries.
 291         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
 292         * i386-tbl.h: Regenerated.
 293
 294 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 295
 296         * i386-dis.c (VZERO_Fixup): Removed.
 297         (VZERO): Likewise.
 298         (VEX_LEN_0F10_P_1): Likewise.
 299         (VEX_LEN_0F10_P_3): Likewise.
 300         (VEX_LEN_0F11_P_1): Likewise.
 301         (VEX_LEN_0F11_P_3): Likewise.
 302         (VEX_LEN_0F2E_P_0): Likewise.
 303         (VEX_LEN_0F2E_P_2): Likewise.
 304         (VEX_LEN_0F2F_P_0): Likewise.
 305         (VEX_LEN_0F2F_P_2): Likewise.
 306         (VEX_LEN_0F51_P_1): Likewise.
 307         (VEX_LEN_0F51_P_3): Likewise.
 308         (VEX_LEN_0F52_P_1): Likewise.
 309         (VEX_LEN_0F53_P_1): Likewise.
 310         (VEX_LEN_0F58_P_1): Likewise.
 311         (VEX_LEN_0F58_P_3): Likewise.
 312         (VEX_LEN_0F59_P_1): Likewise.
 313         (VEX_LEN_0F59_P_3): Likewise.
 314         (VEX_LEN_0F5A_P_1): Likewise.
 315         (VEX_LEN_0F5A_P_3): Likewise.
 316         (VEX_LEN_0F5C_P_1): Likewise.
 317         (VEX_LEN_0F5C_P_3): Likewise.
 318         (VEX_LEN_0F5D_P_1): Likewise.
 319         (VEX_LEN_0F5D_P_3): Likewise.
 320         (VEX_LEN_0F5E_P_1): Likewise.
 321         (VEX_LEN_0F5E_P_3): Likewise.
 322         (VEX_LEN_0F5F_P_1): Likewise.
 323         (VEX_LEN_0F5F_P_3): Likewise.
 324         (VEX_LEN_0FC2_P_1): Likewise.
 325         (VEX_LEN_0FC2_P_3): Likewise.
 326         (VEX_LEN_0F3A0A_P_2): Likewise.
 327         (VEX_LEN_0F3A0B_P_2): Likewise.
 328         (VEX_W_0F10_P_0): Likewise.
 329         (VEX_W_0F10_P_1): Likewise.
 330         (VEX_W_0F10_P_2): Likewise.
 331         (VEX_W_0F10_P_3): Likewise.
 332         (VEX_W_0F11_P_0): Likewise.
 333         (VEX_W_0F11_P_1): Likewise.
 334         (VEX_W_0F11_P_2): Likewise.
 335         (VEX_W_0F11_P_3): Likewise.
 336         (VEX_W_0F12_P_0_M_0): Likewise.
 337         (VEX_W_0F12_P_0_M_1): Likewise.
 338         (VEX_W_0F12_P_1): Likewise.
 339         (VEX_W_0F12_P_2): Likewise.
 340         (VEX_W_0F12_P_3): Likewise.
 341         (VEX_W_0F13_M_0): Likewise.
 342         (VEX_W_0F14): Likewise.
 343         (VEX_W_0F15): Likewise.
 344         (VEX_W_0F16_P_0_M_0): Likewise.
 345         (VEX_W_0F16_P_0_M_1): Likewise.
 346         (VEX_W_0F16_P_1): Likewise.
 347         (VEX_W_0F16_P_2): Likewise.
 348         (VEX_W_0F17_M_0): Likewise.
 349         (VEX_W_0F28): Likewise.
 350         (VEX_W_0F29): Likewise.
 351         (VEX_W_0F2B_M_0): Likewise.
 352         (VEX_W_0F2E_P_0): Likewise.
 353         (VEX_W_0F2E_P_2): Likewise.
 354         (VEX_W_0F2F_P_0): Likewise.
 355         (VEX_W_0F2F_P_2): Likewise.
 356         (VEX_W_0F50_M_0): Likewise.
 357         (VEX_W_0F51_P_0): Likewise.
 358         (VEX_W_0F51_P_1): Likewise.
 359         (VEX_W_0F51_P_2): Likewise.
 360         (VEX_W_0F51_P_3): Likewise.
 361         (VEX_W_0F52_P_0): Likewise.
 362         (VEX_W_0F52_P_1): Likewise.
 363         (VEX_W_0F53_P_0): Likewise.
 364         (VEX_W_0F53_P_1): Likewise.
 365         (VEX_W_0F58_P_0): Likewise.
 366         (VEX_W_0F58_P_1): Likewise.
 367         (VEX_W_0F58_P_2): Likewise.
 368         (VEX_W_0F58_P_3): Likewise.
 369         (VEX_W_0F59_P_0): Likewise.
 370         (VEX_W_0F59_P_1): Likewise.
 371         (VEX_W_0F59_P_2): Likewise.
 372         (VEX_W_0F59_P_3): Likewise.
 373         (VEX_W_0F5A_P_0): Likewise.
 374         (VEX_W_0F5A_P_1): Likewise.
 375         (VEX_W_0F5A_P_3): Likewise.
 376         (VEX_W_0F5B_P_0): Likewise.
 377         (VEX_W_0F5B_P_1): Likewise.
 378         (VEX_W_0F5B_P_2): Likewise.
 379         (VEX_W_0F5C_P_0): Likewise.
 380         (VEX_W_0F5C_P_1): Likewise.
 381         (VEX_W_0F5C_P_2): Likewise.
 382         (VEX_W_0F5C_P_3): Likewise.
 383         (VEX_W_0F5D_P_0): Likewise.
 384         (VEX_W_0F5D_P_1): Likewise.
 385         (VEX_W_0F5D_P_2): Likewise.
 386         (VEX_W_0F5D_P_3): Likewise.
 387         (VEX_W_0F5E_P_0): Likewise.
 388         (VEX_W_0F5E_P_1): Likewise.
 389         (VEX_W_0F5E_P_2): Likewise.
 390         (VEX_W_0F5E_P_3): Likewise.
 391         (VEX_W_0F5F_P_0): Likewise.
 392         (VEX_W_0F5F_P_1): Likewise.
 393         (VEX_W_0F5F_P_2): Likewise.
 394         (VEX_W_0F5F_P_3): Likewise.
 395         (VEX_W_0F60_P_2): Likewise.
 396         (VEX_W_0F61_P_2): Likewise.
 397         (VEX_W_0F62_P_2): Likewise.
 398         (VEX_W_0F63_P_2): Likewise.
 399         (VEX_W_0F64_P_2): Likewise.
 400         (VEX_W_0F65_P_2): Likewise.
 401         (VEX_W_0F66_P_2): Likewise.
 402         (VEX_W_0F67_P_2): Likewise.
 403         (VEX_W_0F68_P_2): Likewise.
 404         (VEX_W_0F69_P_2): Likewise.
 405         (VEX_W_0F6A_P_2): Likewise.
 406         (VEX_W_0F6B_P_2): Likewise.
 407         (VEX_W_0F6C_P_2): Likewise.
 408         (VEX_W_0F6D_P_2): Likewise.
 409         (VEX_W_0F6F_P_1): Likewise.
 410         (VEX_W_0F6F_P_2): Likewise.
 411         (VEX_W_0F70_P_1): Likewise.
 412         (VEX_W_0F70_P_2): Likewise.
 413         (VEX_W_0F70_P_3): Likewise.
 414         (VEX_W_0F71_R_2_P_2): Likewise.
 415         (VEX_W_0F71_R_4_P_2): Likewise.
 416         (VEX_W_0F71_R_6_P_2): Likewise.
 417         (VEX_W_0F72_R_2_P_2): Likewise.
 418         (VEX_W_0F72_R_4_P_2): Likewise.
 419         (VEX_W_0F72_R_6_P_2): Likewise.
 420         (VEX_W_0F73_R_2_P_2): Likewise.
 421         (VEX_W_0F73_R_3_P_2): Likewise.
 422         (VEX_W_0F73_R_6_P_2): Likewise.
 423         (VEX_W_0F73_R_7_P_2): Likewise.
 424         (VEX_W_0F74_P_2): Likewise.
 425         (VEX_W_0F75_P_2): Likewise.
 426         (VEX_W_0F76_P_2): Likewise.
 427         (VEX_W_0F77_P_0): Likewise.
 428         (VEX_W_0F7C_P_2): Likewise.
 429         (VEX_W_0F7C_P_3): Likewise.
 430         (VEX_W_0F7D_P_2): Likewise.
 431         (VEX_W_0F7D_P_3): Likewise.
 432         (VEX_W_0F7E_P_1): Likewise.
 433         (VEX_W_0F7F_P_1): Likewise.
 434         (VEX_W_0F7F_P_2): Likewise.
 435         (VEX_W_0FAE_R_2_M_0): Likewise.
 436         (VEX_W_0FAE_R_3_M_0): Likewise.
 437         (VEX_W_0FC2_P_0): Likewise.
 438         (VEX_W_0FC2_P_1): Likewise.
 439         (VEX_W_0FC2_P_2): Likewise.
 440         (VEX_W_0FC2_P_3): Likewise.
 441         (VEX_W_0FD0_P_2): Likewise.
 442         (VEX_W_0FD0_P_3): Likewise.
 443         (VEX_W_0FD1_P_2): Likewise.
 444         (VEX_W_0FD2_P_2): Likewise.
 445         (VEX_W_0FD3_P_2): Likewise.
 446         (VEX_W_0FD4_P_2): Likewise.
 447         (VEX_W_0FD5_P_2): Likewise.
 448         (VEX_W_0FD6_P_2): Likewise.
 449         (VEX_W_0FD7_P_2_M_1): Likewise.
 450         (VEX_W_0FD8_P_2): Likewise.
 451         (VEX_W_0FD9_P_2): Likewise.
 452         (VEX_W_0FDA_P_2): Likewise.
 453         (VEX_W_0FDB_P_2): Likewise.
 454         (VEX_W_0FDC_P_2): Likewise.
 455         (VEX_W_0FDD_P_2): Likewise.
 456         (VEX_W_0FDE_P_2): Likewise.
 457         (VEX_W_0FDF_P_2): Likewise.
 458         (VEX_W_0FE0_P_2): Likewise.
 459         (VEX_W_0FE1_P_2): Likewise.
 460         (VEX_W_0FE2_P_2): Likewise.
 461         (VEX_W_0FE3_P_2): Likewise.
 462         (VEX_W_0FE4_P_2): Likewise.
 463         (VEX_W_0FE5_P_2): Likewise.
 464         (VEX_W_0FE6_P_1): Likewise.
 465         (VEX_W_0FE6_P_2): Likewise.
 466         (VEX_W_0FE6_P_3): Likewise.
 467         (VEX_W_0FE7_P_2_M_0): Likewise.
 468         (VEX_W_0FE8_P_2): Likewise.
 469         (VEX_W_0FE9_P_2): Likewise.
 470         (VEX_W_0FEA_P_2): Likewise.
 471         (VEX_W_0FEB_P_2): Likewise.
 472         (VEX_W_0FEC_P_2): Likewise.
 473         (VEX_W_0FED_P_2): Likewise.
 474         (VEX_W_0FEE_P_2): Likewise.
 475         (VEX_W_0FEF_P_2): Likewise.
 476         (VEX_W_0FF0_P_3_M_0): Likewise.
 477         (VEX_W_0FF1_P_2): Likewise.
 478         (VEX_W_0FF2_P_2): Likewise.
 479         (VEX_W_0FF3_P_2): Likewise.
 480         (VEX_W_0FF4_P_2): Likewise.
 481         (VEX_W_0FF5_P_2): Likewise.
 482         (VEX_W_0FF6_P_2): Likewise.
 483         (VEX_W_0FF7_P_2): Likewise.
 484         (VEX_W_0FF8_P_2): Likewise.
 485         (VEX_W_0FF9_P_2): Likewise.
 486         (VEX_W_0FFA_P_2): Likewise.
 487         (VEX_W_0FFB_P_2): Likewise.
 488         (VEX_W_0FFC_P_2): Likewise.
 489         (VEX_W_0FFD_P_2): Likewise.
 490         (VEX_W_0FFE_P_2): Likewise.
 491         (VEX_W_0F3800_P_2): Likewise.
 492         (VEX_W_0F3801_P_2): Likewise.
 493         (VEX_W_0F3802_P_2): Likewise.
 494         (VEX_W_0F3803_P_2): Likewise.
 495         (VEX_W_0F3804_P_2): Likewise.
 496         (VEX_W_0F3805_P_2): Likewise.
 497         (VEX_W_0F3806_P_2): Likewise.
 498         (VEX_W_0F3807_P_2): Likewise.
 499         (VEX_W_0F3808_P_2): Likewise.
 500         (VEX_W_0F3809_P_2): Likewise.
 501         (VEX_W_0F380A_P_2): Likewise.
 502         (VEX_W_0F380B_P_2): Likewise.
 503         (VEX_W_0F3817_P_2): Likewise.
 504         (VEX_W_0F381C_P_2): Likewise.
 505         (VEX_W_0F381D_P_2): Likewise.
 506         (VEX_W_0F381E_P_2): Likewise.
 507         (VEX_W_0F3820_P_2): Likewise.
 508         (VEX_W_0F3821_P_2): Likewise.
 509         (VEX_W_0F3822_P_2): Likewise.
 510         (VEX_W_0F3823_P_2): Likewise.
 511         (VEX_W_0F3824_P_2): Likewise.
 512         (VEX_W_0F3825_P_2): Likewise.
 513         (VEX_W_0F3828_P_2): Likewise.
 514         (VEX_W_0F3829_P_2): Likewise.
 515         (VEX_W_0F382A_P_2_M_0): Likewise.
 516         (VEX_W_0F382B_P_2): Likewise.
 517         (VEX_W_0F3830_P_2): Likewise.
 518         (VEX_W_0F3831_P_2): Likewise.
 519         (VEX_W_0F3832_P_2): Likewise.
 520         (VEX_W_0F3833_P_2): Likewise.
 521         (VEX_W_0F3834_P_2): Likewise.
 522         (VEX_W_0F3835_P_2): Likewise.
 523         (VEX_W_0F3837_P_2): Likewise.
 524         (VEX_W_0F3838_P_2): Likewise.
 525         (VEX_W_0F3839_P_2): Likewise.
 526         (VEX_W_0F383A_P_2): Likewise.
 527         (VEX_W_0F383B_P_2): Likewise.
 528         (VEX_W_0F383C_P_2): Likewise.
 529         (VEX_W_0F383D_P_2): Likewise.
 530         (VEX_W_0F383E_P_2): Likewise.
 531         (VEX_W_0F383F_P_2): Likewise.
 532         (VEX_W_0F3840_P_2): Likewise.
 533         (VEX_W_0F3841_P_2): Likewise.
 534         (VEX_W_0F38DB_P_2): Likewise.
 535         (VEX_W_0F3A08_P_2): Likewise.
 536         (VEX_W_0F3A09_P_2): Likewise.
 537         (VEX_W_0F3A0A_P_2): Likewise.
 538         (VEX_W_0F3A0B_P_2): Likewise.
 539         (VEX_W_0F3A0C_P_2): Likewise.
 540         (VEX_W_0F3A0D_P_2): Likewise.
 541         (VEX_W_0F3A0E_P_2): Likewise.
 542         (VEX_W_0F3A0F_P_2): Likewise.
 543         (VEX_W_0F3A21_P_2): Likewise.
 544         (VEX_W_0F3A40_P_2): Likewise.
 545         (VEX_W_0F3A41_P_2): Likewise.
 546         (VEX_W_0F3A42_P_2): Likewise.
 547         (VEX_W_0F3A62_P_2): Likewise.
 548         (VEX_W_0F3A63_P_2): Likewise.
 549         (VEX_W_0F3ADF_P_2): Likewise.
 550         (VEX_LEN_0F77_P_0): New.
 551         (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
 552         PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
 553         PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
 554         PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
 555         PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
 556         PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
 557         PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
 558         PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
 559         PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
 560         PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
 561         PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
 562         PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
 563         PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
 564         PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
 565         PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
 566         PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
 567         PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
 568         PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
 569         PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
 570         PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
 571         PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
 572         PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
 573         PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
 574         PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
 575         PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
 576         PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
 577         PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
 578         PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
 579         PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
 580         PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
 581         PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
 582         PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
 583         PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
 584         PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
 585         PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
 586         PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
 587         PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
 588         PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
 589         PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
 590         PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
 591         PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
 592         PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
 593         PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
 594         PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
 595         PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
 596         PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
 597         PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
 598         PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
 599         PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
 600         (vex_table): Update VEX 0F28 and 0F29 entries.
 601         (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
 602         VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
 603         VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
 604         VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
 605         VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
 606         VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
 607         VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
 608         VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
 609         VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
 610         VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
 611         VEX_LEN_0F3A0B_P_2 entries.
 612         (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
 613         VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
 614         VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
 615         VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
 616         VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
 617         VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
 618         VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
 619         VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
 620         VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
 621         VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
 622         VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
 623         VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
 624         VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
 625         VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
 626         VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
 627         VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
 628         VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
 629         VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
 630         VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
 631         VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
 632         VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
 633         VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
 634         VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
 635         VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
 636         VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
 637         VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
 638         VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
 639         VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
 640         VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
 641         VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
 642         VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
 643         VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
 644         VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
 645         VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
 646         VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
 647         VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
 648         VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
 649         VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
 650         VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
 651         VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
 652         VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
 653         VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
 654         VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
 655         VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
 656         VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
 657         VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
 658         VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
 659         VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
 660         VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
 661         VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
 662         VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
 663         VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
 664         VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
 665         VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
 666         VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
 667         VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
 668         VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
 669         VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
 670         VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
 671         VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
 672         VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
 673         VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
 674         VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
 675         VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
 676         VEX_W_0F3ADF_P_2 entries.
 677         (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
 678         MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
 679         MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
 680
 681 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 682
 683         * i386-opc.tbl (VexWIG): New.
 684         Replace VexW=3 with VexWIG.
 685
 686 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 687
 688         * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
 689         * i386-tbl.h: Regenerated.
 690
 691 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 692
 693         PR gas/23665
 694         * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
 695         VEX_LEN_0FD6_P_2 entries.
 696         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
 697         * i386-tbl.h: Regenerated.
 698
 699 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 700
 701         PR gas/23642
 702         * i386-opc.h (VEXWIG): New.
 703         * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
 704         * i386-tbl.h: Regenerated.
 705
 706 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 707
 708         PR binutils/23655
 709         * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
 710         vcvtsi2sd%LQ and vcvtusi2sd%LQ.
 711         * i386-dis.c (EXxEVexR64): New.
 712         (evex_rounding_64_mode): Likewise.
 713         (OP_Rounding): Handle evex_rounding_64_mode.
 714
 715 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 716
 717         PR binutils/23655
 718         * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
 719         vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
 720         * i386-dis.c (Edqa): New.
 721         (dqa_mode): Likewise.
 722         (intel_operand_size): Handle dqa_mode as m_mode.
 723         (OP_E_register): Handle dqa_mode as dq_mode.
 724         (OP_E_memory): Set shift for dqa_mode based on address_mode.
 725
 726 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 727
 728         * i386-dis.c (OP_E_memory): Reformat.
 729
 730 2018-09-14  Jan Beulich  <jbeulich@suse.com>
 731
 732         * i386-opc.tbl (crc32): Fold byte and word forms.
 733         * i386-tbl.h: Re-generate.
 734
 735 2018-09-13  H.J. Lu  <hongjiu.lu@intel.com>
 736
 737         * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
 738         pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
 739         Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
 740         vpinsrq.  Remove VexW=1 from WIG VEX movq and vmovq.
 741         * i386-tbl.h: Regenerated.
 742
 743 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 744
 745         * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
 746         meaningless.
 747         (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
 748         xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
 749         rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
 750         * i386-tbl.h: Re-generate.
 751
 752 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 753
 754         * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
 755         AVX512_4VNNIW insns.
 756         * i386-tbl.h: Re-generate.
 757
 758 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 759
 760         * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
 761         meaningless.
 762         * i386-tbl.h: Re-generate.
 763
 764 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 765
 766         * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
 767         meaningless.
 768         * i386-tbl.h: Re-generate.
 769
 770 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 771
 772         * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
 773         meaningless.
 774         * i386-tbl.h: Re-generate.
 775
 776 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 777
 778         * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
 779         meaningless.
 780         * i386-tbl.h: Re-generate.
 781
 782 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 783
 784         * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
 785         meaningless.
 786         * i386-tbl.h: Re-generate.
 787
 788 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 789
 790         * i386-opc.tbl: Drop IgnoreSize from SHA insns.
 791         * i386-tbl.h: Re-generate.
 792
 793 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 794
 795         * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
 796         * i386-tbl.h: Re-generate.
 797
 798 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 799
 800         * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
 801         meaningless.
 802         * i386-tbl.h: Re-generate.
 803
 804 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 805
 806         * i386-opc.tbl: Drop IgnoreSize from AVX insns where
 807         meaningless.
 808         * i386-tbl.h: Re-generate.
 809
 810 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 811
 812         * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
 813         * i386-tbl.h: Re-generate.
 814
 815 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 816
 817         * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
 818         * i386-tbl.h: Re-generate.
 819
 820 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 821
 822         * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
 823         * i386-tbl.h: Re-generate.
 824
 825 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 826
 827         * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
 828         meaningless.
 829         * i386-tbl.h: Re-generate.
 830
 831 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 832
 833         * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
 834         meaningless.
 835         * i386-tbl.h: Re-generate.
 836
 837 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 838
 839         * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
 840         meaningless.
 841         * i386-tbl.h: Re-generate.
 842
 843 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 844
 845         * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
 846         * i386-tbl.h: Re-generate.
 847
 848 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 849
 850         * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
 851         * i386-tbl.h: Re-generate.
 852
 853 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 854
 855         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
 856         * i386-tbl.h: Re-generate.
 857
 858 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 859
 860         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
 861         (vpbroadcastw, rdpid): Drop NoRex64.
 862         * i386-tbl.h: Re-generate.
 863
 864 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 865
 866         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
 867         store templates, adding D.
 868         * i386-tbl.h: Re-generate.
 869
 870 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 871
 872         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
 873         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
 874         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
 875         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
 876         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
 877         Fold load and store templates where possible, adding D. Drop
 878         IgnoreSize where it was pointlessly present. Drop redundant
 879         *word.
 880         * i386-tbl.h: Re-generate.
 881
 882 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 883
 884         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
 885         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
 886         (intel_operand_size): Handle v_bndmk_mode.
 887         (OP_E_memory): Likewise. Produce (bad) when also riprel.
 888
 889 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
 890
 891         * disassemble.c (ARCH_s12z): Define if ARCH_all.
 892
 893 2018-08-31  Kito Cheng  <kito@andestech.com>
 894
 895         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
 896         compressed floating point instructions.
 897
 898 2018-08-30  Kito Cheng  <kito@andestech.com>
 899
 900         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
 901         riscv_opcode.xlen_requirement.
 902         * riscv-opc.c (riscv_opcodes): Update for struct change.
 903
 904 2018-08-29  Martin Aberg  <maberg@gaisler.com>
 905
 906         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
 907         psr (PWRPSR) instruction.
 908
 909 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 910
 911         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
 912
 913 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 914
 915         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
 916
 917 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 918
 919         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
 920         loongson3a as an alias of gs464 for compatibility.
 921         * mips-opc.c (mips_opcodes): Change Comments.
 922
 923 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 924
 925         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
 926         option.
 927         (print_mips_disassembler_options): Document -M loongson-ext.
 928         * mips-opc.c (LEXT2): New macro.
 929         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
 930
 931 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 932
 933          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
 934          descriptors.
 935          (parse_mips_ase_option): Handle -M loongson-ext option.
 936          (print_mips_disassembler_options): Document -M loongson-ext.
 937          * mips-opc.c (IL3A): Delete.
 938          * mips-opc.c (LEXT): New macro.
 939          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
 940          instructions.
 941
 942 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 943
 944         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
 945         descriptors.
 946         (parse_mips_ase_option): Handle -M loongson-cam option.
 947         (print_mips_disassembler_options): Document -M loongson-cam.
 948         * mips-opc.c (LCAM): New macro.
 949         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
 950         instructions.
 951
 952 2018-08-21  Alan Modra  <amodra@gmail.com>
 953
 954         * ppc-dis.c (operand_value_powerpc): Init "invalid".
 955         (skip_optional_operands): Count optional operands, and update
 956         ppc_optional_operand_value call.
 957         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
 958         (extract_vlensi): Likewise.
 959         (extract_fxm): Return default value for missing optional operand.
 960         (extract_ls, extract_raq, extract_tbr): Likewise.
 961         (insert_sxl, extract_sxl): New functions.
 962         (insert_esync, extract_esync): Remove Power9 handling and simplify.
 963         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
 964         flag and extra entry.
 965         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
 966         extract_sxl.
 967
 968 2018-08-20  Alan Modra  <amodra@gmail.com>
 969
 970         * sh-opc.h (MASK): Simplify.
 971
 972 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 973
 974         * s12z-dis.c (bm_decode): Deal with cases where the mode is
 975         BM_RESERVED0 or BM_RESERVED1
 976         (bm_rel_decode, bm_n_bytes): Ditto.
 977
 978 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 979
 980         * s12z.h: Delete.
 981
 982 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
 983
 984         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
 985         address with the addr32 prefix and without base nor index
 986         registers.
 987
 988 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
 989
 990         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
 991         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
 992         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
 993         (cpu_flags): Add CpuCMOV and CpuFXSR.
 994         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
 995         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
 996         * i386-init.h: Regenerated.
 997         * i386-tbl.h: Likewise.
 998
 999 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
1000
1001         * arc-regs.h: Update auxiliary registers.
1002
1003 2018-08-06  Jan Beulich  <jbeulich@suse.com>
1004
1005         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
1006         (RegIP, RegIZ): Define.
1007         * i386-reg.tbl: Adjust comments.
1008         (rip): Use Qword instead of BaseIndex. Use RegIP.
1009         (eip): Use Dword instead of BaseIndex. Use RegIP.
1010         (riz): Add Qword. Use RegIZ.
1011         (eiz): Add Dword. Use RegIZ.
1012         * i386-tbl.h: Re-generate.
1013
1014 2018-08-03  Jan Beulich  <jbeulich@suse.com>
1015
1016         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
1017         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
1018         vpmovzxdq, vpmovzxwd): Remove NoRex64.
1019         * i386-tbl.h: Re-generate.
1020
1021 2018-08-03  Jan Beulich  <jbeulich@suse.com>
1022
1023         * i386-gen.c (operand_types): Remove Mem field.
1024         * i386-opc.h (union i386_operand_type): Remove mem field.
1025         * i386-init.h, i386-tbl.h: Re-generate.
1026
1027 2018-08-01  Alan Modra  <amodra@gmail.com>
1028
1029         * po/POTFILES.in: Regenerate.
1030
1031 2018-07-31  Nick Clifton  <nickc@redhat.com>
1032
1033         * po/sv.po: Updated Swedish translation.
1034
1035 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1036
1037         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
1038         * i386-init.h, i386-tbl.h: Re-generate.
1039
1040 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1041
1042         * i386-opc.h (ZEROING_MASKING) Rename to ...
1043         (DYNAMIC_MASKING): ... this. Adjust comment.
1044         * i386-opc.tbl (MaskingMorZ): Define.
1045         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
1046         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
1047         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
1048         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
1049         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
1050         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
1051         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
1052         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
1053         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
1054
1055 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1056
1057         * i386-opc.tbl: Use element rather than vector size for AVX512*
1058         scatter/gather insns.
1059         * i386-tbl.h: Re-generate.
1060
1061 2018-07-31  Jan Beulich  <jbeulich@suse.com>
1062
1063         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
1064         (cpu_flags): Drop CpuVREX.
1065         * i386-opc.h (CpuVREX): Delete.
1066         (union i386_cpu_flags): Remove cpuvrex.
1067         * i386-init.h, i386-tbl.h: Re-generate.
1068
1069 2018-07-30  Jim Wilson  <jimw@sifive.com>
1070
1071         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
1072         fields.
1073         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
1074
1075 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
1076
1077         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
1078         * Makefile.in: Regenerated.
1079         * configure.ac: Add C-SKY.
1080         * configure: Regenerated.
1081         * csky-dis.c: New file.
1082         * csky-opc.h: New file.
1083         * disassemble.c (ARCH_csky): Define.
1084         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
1085         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
1086
1087 2018-07-27  Alan Modra  <amodra@gmail.com>
1088
1089         * ppc-opc.c (insert_sprbat): Correct function parameter and
1090         return type.
1091         (extract_sprbat): Likewise, variable too.
1092
1093 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
1094             Alan Modra  <amodra@gmail.com>
1095
1096         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
1097         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
1098         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
1099         support disjointed BAT.
1100         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
1101         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
1102         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
1103
1104 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
1105             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1106
1107         * i386-gen.c (adjust_broadcast_modifier): New function.
1108         (process_i386_opcode_modifier): Add an argument for operands.
1109         Adjust the Broadcast value based on operands.
1110         (output_i386_opcode): Pass operand_types to
1111         process_i386_opcode_modifier.
1112         (process_i386_opcodes): Pass NULL as operands to
1113         process_i386_opcode_modifier.
1114         * i386-opc.h (BYTE_BROADCAST): New.
1115         (WORD_BROADCAST): Likewise.
1116         (DWORD_BROADCAST): Likewise.
1117         (QWORD_BROADCAST): Likewise.
1118         (i386_opcode_modifier): Expand broadcast to 3 bits.
1119         * i386-tbl.h: Regenerated.
1120
1121 2018-07-24  Alan Modra  <amodra@gmail.com>
1122
1123         PR 23430
1124         * or1k-desc.h: Regenerate.
1125
1126 2018-07-24  Jan Beulich  <jbeulich@suse.com>
1127
1128         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1129         vcvtusi2ss, and vcvtusi2sd.
1130         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1131         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1132         * i386-tbl.h: Re-generate.
1133
1134 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1135
1136         * arc-opc.c (extract_w6): Fix extending the sign.
1137
1138 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1139
1140         * arc-tbl.h (vewt): Allow it for ARC EM family.
1141
1142 2018-07-23  Alan Modra  <amodra@gmail.com>
1143
1144         PR 23419
1145         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1146         opcode variants for mtspr/mfspr encodings.
1147
1148 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1149             Maciej W. Rozycki  <macro@mips.com>
1150
1151         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1152         loongson3a descriptors.
1153         (parse_mips_ase_option): Handle -M loongson-mmi option.
1154         (print_mips_disassembler_options): Document -M loongson-mmi.
1155         * mips-opc.c (LMMI): New macro.
1156         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1157         instructions.
1158
1159 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1160
1161         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1162         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1163         IgnoreSize and [XYZ]MMword where applicable.
1164         * i386-tbl.h: Re-generate.
1165
1166 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1167
1168         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1169         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1170         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1171         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1172         * i386-tbl.h: Re-generate.
1173
1174 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1175
1176         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1177         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1178         VPCLMULQDQ templates into their respective AVX512VL counterparts
1179         where possible, using Disp8ShiftVL and CheckRegSize instead of
1180         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1181         * i386-tbl.h: Re-generate.
1182
1183 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1184
1185         * i386-opc.tbl: Fold AVX512DQ templates into their respective
1186         AVX512VL counterparts where possible, using Disp8ShiftVL and
1187         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1188         IgnoreSize) as appropriate.
1189         * i386-tbl.h: Re-generate.
1190
1191 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1192
1193         * i386-opc.tbl: Fold AVX512BW templates into their respective
1194         AVX512VL counterparts where possible, using Disp8ShiftVL and
1195         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1196         IgnoreSize) as appropriate.
1197         * i386-tbl.h: Re-generate.
1198
1199 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1200
1201         * i386-opc.tbl: Fold AVX512CD templates into their respective
1202         AVX512VL counterparts where possible, using Disp8ShiftVL and
1203         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1204         IgnoreSize) as appropriate.
1205         * i386-tbl.h: Re-generate.
1206
1207 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1208
1209         * i386-opc.h (DISP8_SHIFT_VL): New.
1210         * i386-opc.tbl (Disp8ShiftVL):  Define.
1211         (various): Fold AVX512VL templates into their respective
1212         AVX512F counterparts where possible, using Disp8ShiftVL and
1213         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1214         IgnoreSize) as appropriate.
1215         * i386-tbl.h: Re-generate.
1216
1217 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1218
1219         * Makefile.am: Change dependencies and rule for
1220         $(srcdir)/i386-init.h.
1221         * Makefile.in: Re-generate.
1222         * i386-gen.c (process_i386_opcodes): New local variable
1223         "marker". Drop opening of input file. Recognize marker and line
1224         number directives.
1225         * i386-opc.tbl (OPCODE_I386_H): Define.
1226         (i386-opc.h): Include it.
1227         (None): Undefine.
1228
1229 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
1230
1231         PR gas/23418
1232         * i386-opc.h (Byte): Update comments.
1233         (Word): Likewise.
1234         (Dword): Likewise.
1235         (Fword): Likewise.
1236         (Qword): Likewise.
1237         (Tbyte): Likewise.
1238         (Xmmword): Likewise.
1239         (Ymmword): Likewise.
1240         (Zmmword): Likewise.
1241         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1242         vcvttps2uqq.
1243         * i386-tbl.h: Regenerated.
1244
1245 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
1246
1247         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1248         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1249         * aarch64-asm-2.c: Regenerate.
1250         * aarch64-dis-2.c: Regenerate.
1251         * aarch64-opc-2.c: Regenerate.
1252
1253 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
1254
1255         PR binutils/23192
1256         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1257         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1258         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1259         sqdmulh, sqrdmulh): Use Em16.
1260
1261 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
1262
1263         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1264         csdb together with them.
1265         (thumb32_opcodes): Likewise.
1266
1267 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1268
1269         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1270         requiring 32-bit registers as operands 2 and 3. Improve
1271         comments.
1272         (mwait, mwaitx): Fold templates. Improve comments.
1273         OPERAND_TYPE_INOUTPORTREG.
1274         * i386-tbl.h: Re-generate.
1275
1276 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1277
1278         * i386-gen.c (operand_type_init): Remove
1279         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1280         OPERAND_TYPE_INOUTPORTREG.
1281         * i386-init.h: Re-generate.
1282
1283 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1284
1285         * i386-opc.tbl (wrssd, wrussd): Add Dword.
1286         (wrssq, wrussq): Add Qword.
1287         * i386-tbl.h: Re-generate.
1288
1289 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1290
1291         * i386-opc.h: Rename OTMax to OTNum.
1292         (OTNumOfUints): Adjust calculation.
1293         (OTUnused): Directly alias to OTNum.
1294
1295 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
1296
1297         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1298         `reg_xys'.
1299         (lea_reg_xys): Likewise.
1300         (print_insn_loop_primitive): Rename `reg' local variable to
1301         `reg_dxy'.
1302
1303 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1304
1305         PR binutils/23242
1306         * aarch64-tbl.h (ldarh): Fix disassembly mask.
1307
1308 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1309
1310         PR binutils/23369
1311         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1312         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1313
1314 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
1315
1316         PR tdep/8282
1317         * mips-dis.c (mips_option_arg_t): New enumeration.
1318         (mips_options): New variable.
1319         (disassembler_options_mips): New function.
1320         (print_mips_disassembler_options): Reimplement in terms of
1321         `disassembler_options_mips'.
1322         * arm-dis.c (disassembler_options_arm): Adapt to using the
1323         `disasm_options_and_args_t' structure.
1324         * ppc-dis.c (disassembler_options_powerpc): Likewise.
1325         * s390-dis.c (disassembler_options_s390): Likewise.
1326
1327 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1328
1329         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1330         expected result.
1331         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1332         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1333         * testsuite/ld-arm/tls-longplt.d: Likewise.
1334
1335 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
1336
1337         PR binutils/23192
1338         * aarch64-asm-2.c: Regenerate.
1339         * aarch64-dis-2.c: Likewise.
1340         * aarch64-opc-2.c: Likewise.
1341         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1342         * aarch64-opc.c (operand_general_constraint_met_p,
1343         aarch64_print_operand): Likewise.
1344         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1345         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1346         fmlal2, fmlsl2.
1347         (AARCH64_OPERANDS): Add Em2.
1348
1349 2018-06-26  Nick Clifton  <nickc@redhat.com>
1350
1351         * po/uk.po: Updated Ukranian translation.
1352         * po/de.po: Updated German translation.
1353         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1354
1355 2018-06-26  Nick Clifton  <nickc@redhat.com>
1356
1357         * nfp-dis.c: Fix spelling mistake.
1358
1359 2018-06-24  Nick Clifton  <nickc@redhat.com>
1360
1361         * configure: Regenerate.
1362         * po/opcodes.pot: Regenerate.
1363
1364 2018-06-24  Nick Clifton  <nickc@redhat.com>
1365
1366         2.31 branch created.
1367
1368 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
1369
1370         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1371         * aarch64-asm-2.c: Regenerate.
1372         * aarch64-dis-2.c: Likewise.
1373
1374 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
1375
1376         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1377         `-M ginv' option description.
1378
1379 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
1380
1381         PR gas/23305
1382         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1383         la and lla.
1384
1385 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
1386
1387         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1388         * configure.ac: Remove AC_PREREQ.
1389         * Makefile.in: Re-generate.
1390         * aclocal.m4: Re-generate.
1391         * configure: Re-generate.
1392
1393 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1394
1395         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1396         mips64r6 descriptors.
1397         (parse_mips_ase_option): Handle -Mginv option.
1398         (print_mips_disassembler_options): Document -Mginv.
1399         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1400         (GINV): New macro.
1401         (mips_opcodes): Define ginvi and ginvt.
1402
1403 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
1404             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1405
1406         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1407         * mips-opc.c (CRC, CRC64): New macros.
1408         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1409         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
1410         crc32cd for CRC64.
1411
1412 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
1413
1414         PR 20319
1415         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1416         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1417
1418 2018-06-06  Alan Modra  <amodra@gmail.com>
1419
1420         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1421         setjmp.  Move init for some other vars later too.
1422
1423 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
1424
1425         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1426         (dis_private): Add new fields for property section tracking.
1427         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1428         (xtensa_instruction_fits): New functions.
1429         (fetch_data): Bump minimal fetch size to 4.
1430         (print_insn_xtensa): Make struct dis_private static.
1431         Load and prepare property table on section change.
1432         Don't disassemble literals. Don't disassemble instructions that
1433         cross property table boundaries.
1434
1435 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
1436
1437         * configure: Regenerated.
1438
1439 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1440
1441         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1442         * i386-tbl.h: Re-generate.
1443
1444 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1445
1446         * i386-opc.tbl (sldt, str): Add NoRex64.
1447         * i386-tbl.h: Re-generate.
1448
1449 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1450
1451         * i386-opc.tbl (invpcid): Add Oword.
1452         * i386-tbl.h: Re-generate.
1453
1454 2018-06-01  Alan Modra  <amodra@gmail.com>
1455
1456         * sysdep.h (_bfd_error_handler): Don't declare.
1457         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
1458         * rl78-decode.opc: Likewise.
1459         * msp430-decode.c: Regenerate.
1460         * rl78-decode.c: Regenerate.
1461
1462 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
1463
1464         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1465         * i386-init.h : Regenerated.
1466
1467 2018-05-25  Alan Modra  <amodra@gmail.com>
1468
1469         * Makefile.in: Regenerate.
1470         * po/POTFILES.in: Regenerate.
1471
1472 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
1473
1474         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1475         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1476         (insert_bab, extract_bab, insert_btab, extract_btab,
1477         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1478         (BAT, BBA VBA RBS XB6S): Delete macros.
1479         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1480         (BB, BD, RBX, XC6): Update for new macros.
1481         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1482         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1483         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1484         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1485
1486 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
1487
1488         * Makefile.am: Add support for s12z architecture.
1489         * configure.ac: Likewise.
1490         * disassemble.c: Likewise.
1491         * disassemble.h: Likewise.
1492         * Makefile.in: Regenerate.
1493         * configure: Regenerate.
1494         * s12z-dis.c: New file.
1495         * s12z.h: New file.
1496
1497 2018-05-18  Alan Modra  <amodra@gmail.com>
1498
1499         * nfp-dis.c: Don't #include libbfd.h.
1500         (init_nfp3200_priv): Use bfd_get_section_contents.
1501         (nit_nfp6000_mecsr_sec): Likewise.
1502
1503 2018-05-17  Nick Clifton  <nickc@redhat.com>
1504
1505         * po/zh_CN.po: Updated simplified Chinese translation.
1506
1507 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
1508
1509         PR binutils/23109
1510         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1511         * aarch64-dis-2.c: Regenerate.
1512
1513 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1514
1515         PR binutils/21446
1516         * aarch64-asm.c (opintl.h): Include.
1517         (aarch64_ins_sysreg): Enforce read/write constraints.
1518         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1519         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1520         (F_REG_READ, F_REG_WRITE): New.
1521         * aarch64-opc.c (aarch64_print_operand): Generate notes for
1522         AARCH64_OPND_SYSREG.
1523         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1524         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1525         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1526         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1527         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1528         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1529         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1530         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1531         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1532         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1533         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1534         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1535         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1536         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1537         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1538         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1539         msr (F_SYS_WRITE), mrs (F_SYS_READ).
1540
1541 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1542
1543         PR binutils/21446
1544         * aarch64-dis.c (no_notes: New.
1545         (parse_aarch64_dis_option): Support notes.
1546         (aarch64_decode_insn, print_operands): Likewise.
1547         (print_aarch64_disassembler_options): Document notes.
1548         * aarch64-opc.c (aarch64_print_operand): Support notes.
1549
1550 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1551
1552         PR binutils/21446
1553         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1554         and take error struct.
1555         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1556         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1557         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1558         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1559         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1560         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1561         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1562         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1563         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1564         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1565         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1566         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1567         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1568         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1569         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1570         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1571         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1572         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1573         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1574         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1575         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1576         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1577         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1578         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1579         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1580         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1581         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1582         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1583         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1584         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1585         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1586         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1587         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1588         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1589         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1590         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1591         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1592         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1593         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1594         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1595         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1596         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1597         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1598         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1599         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1600         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1601         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1602         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1603         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1604         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1605         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1606         (determine_disassembling_preference, aarch64_decode_insn,
1607         print_insn_aarch64_word, print_insn_data): Take errors struct.
1608         (print_insn_aarch64): Use errors.
1609         * aarch64-asm-2.c: Regenerate.
1610         * aarch64-dis-2.c: Regenerate.
1611         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1612         boolean in aarch64_insert_operan.
1613         (print_operand_extractor): Likewise.
1614         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1615
1616 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
1617
1618         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1619
1620 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
1621
1622         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1623
1624 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
1625
1626         * cr16-opc.c (cr16_instruction): Comment typo fix.
1627         * hppa-dis.c (print_insn_hppa): Likewise.
1628
1629 2018-05-08  Jim Wilson  <jimw@sifive.com>
1630
1631         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1632         (match_c_slli64, match_srxi_as_c_srxi): New.
1633         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1634         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1635         <c.slli, c.srli, c.srai>: Use match_s_slli.
1636         <c.slli64, c.srli64, c.srai64>: New.
1637
1638 2018-05-08  Alan Modra  <amodra@gmail.com>
1639
1640         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1641         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1642         partition opcode space for index lookup.
1643
1644 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1645
1646         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1647         <insn_length>: ...with this.  Update usage.
1648         Remove duplicate call to *info->memory_error_func.
1649
1650 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1651             H.J. Lu  <hongjiu.lu@intel.com>
1652
1653         * i386-dis.c (Gva): New.
1654         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1655         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1656         (prefix_table): New instructions (see prefix above).
1657         (mod_table): New instructions (see prefix above).
1658         (OP_G): Handle va_mode.
1659         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1660         CPU_MOVDIR64B_FLAGS.
1661         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1662         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1663         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1664         * i386-opc.tbl: Add movidir{i,64b}.
1665         * i386-init.h: Regenerated.
1666         * i386-tbl.h: Likewise.
1667
1668 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
1669
1670         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1671         AddrPrefixOpReg.
1672         * i386-opc.h (AddrPrefixOp0): Renamed to ...
1673         (AddrPrefixOpReg): This.
1674         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1675         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1676
1677 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1678
1679         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1680         (vle_num_opcodes): Likewise.
1681         (spe2_num_opcodes): Likewise.
1682         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1683         initialization loop.
1684         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1685         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
1686         only once.
1687
1688 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
1689
1690         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1691
1692 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
1693
1694         Makefile.am: Added nfp-dis.c.
1695         configure.ac: Added bfd_nfp_arch.
1696         disassemble.h: Added print_insn_nfp prototype.
1697         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1698         nfp-dis.c: New, for NFP support.
1699         po/POTFILES.in: Added nfp-dis.c to the list.
1700         Makefile.in: Regenerate.
1701         configure: Regenerate.
1702
1703 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1704
1705         * i386-opc.tbl: Fold various non-memory operand AVX512VL
1706         templates into their base ones.
1707         * i386-tlb.h: Re-generate.
1708
1709 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1710
1711         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1712         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1713         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1714         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1715         * i386-init.h: Re-generate.
1716
1717 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1718
1719         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1720         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1721         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1722         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1723         comment.
1724         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1725         and CpuRegMask.
1726         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1727         CpuRegMask: Delete.
1728         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1729         cpuregzmm, and cpuregmask.
1730         * i386-init.h: Re-generate.
1731         * i386-tbl.h: Re-generate.
1732
1733 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1734
1735         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1736         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1737         * i386-init.h: Re-generate.
1738
1739 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1740
1741         * i386-gen.c (VexImmExt): Delete.
1742         * i386-opc.h (VexImmExt, veximmext): Delete.
1743         * i386-opc.tbl: Drop all VexImmExt uses.
1744         * i386-tlb.h: Re-generate.
1745
1746 2018-04-25  Jan Beulich  <jbeulich@suse.com>
1747
1748         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1749         register-only forms.
1750         * i386-tlb.h: Re-generate.
1751
1752 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
1753
1754         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1755
1756 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1757
1758         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1759         PREFIX_0F1C.
1760         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1761         (cpu_flags): Add CpuCLDEMOTE.
1762         * i386-init.h: Regenerate.
1763         * i386-opc.h (enum): Add CpuCLDEMOTE,
1764         (i386_cpu_flags): Add cpucldemote.
1765         * i386-opc.tbl: Add cldemote.
1766         * i386-tbl.h: Regenerate.
1767
1768 2018-04-16  Alan Modra  <amodra@gmail.com>
1769
1770         * Makefile.am: Remove sh5 and sh64 support.
1771         * configure.ac: Likewise.
1772         * disassemble.c: Likewise.
1773         * disassemble.h: Likewise.
1774         * sh-dis.c: Likewise.
1775         * sh64-dis.c: Delete.
1776         * sh64-opc.c: Delete.
1777         * sh64-opc.h: Delete.
1778         * Makefile.in: Regenerate.
1779         * configure: Regenerate.
1780         * po/POTFILES.in: Regenerate.
1781
1782 2018-04-16  Alan Modra  <amodra@gmail.com>
1783
1784         * Makefile.am: Remove w65 support.
1785         * configure.ac: Likewise.
1786         * disassemble.c: Likewise.
1787         * disassemble.h: Likewise.
1788         * w65-dis.c: Delete.
1789         * w65-opc.h: Delete.
1790         * Makefile.in: Regenerate.
1791         * configure: Regenerate.
1792         * po/POTFILES.in: Regenerate.
1793
1794 2018-04-16  Alan Modra  <amodra@gmail.com>
1795
1796         * configure.ac: Remove we32k support.
1797         * configure: Regenerate.
1798
1799 2018-04-16  Alan Modra  <amodra@gmail.com>
1800
1801         * Makefile.am: Remove m88k support.
1802         * configure.ac: Likewise.
1803         * disassemble.c: Likewise.
1804         * disassemble.h: Likewise.
1805         * m88k-dis.c: Delete.
1806         * Makefile.in: Regenerate.
1807         * configure: Regenerate.
1808         * po/POTFILES.in: Regenerate.
1809
1810 2018-04-16  Alan Modra  <amodra@gmail.com>
1811
1812         * Makefile.am: Remove i370 support.
1813         * configure.ac: Likewise.
1814         * disassemble.c: Likewise.
1815         * disassemble.h: Likewise.
1816         * i370-dis.c: Delete.
1817         * i370-opc.c: Delete.
1818         * Makefile.in: Regenerate.
1819         * configure: Regenerate.
1820         * po/POTFILES.in: Regenerate.
1821
1822 2018-04-16  Alan Modra  <amodra@gmail.com>
1823
1824         * Makefile.am: Remove h8500 support.
1825         * configure.ac: Likewise.
1826         * disassemble.c: Likewise.
1827         * disassemble.h: Likewise.
1828         * h8500-dis.c: Delete.
1829         * h8500-opc.h: Delete.
1830         * Makefile.in: Regenerate.
1831         * configure: Regenerate.
1832         * po/POTFILES.in: Regenerate.
1833
1834 2018-04-16  Alan Modra  <amodra@gmail.com>
1835
1836         * configure.ac: Remove tahoe support.
1837         * configure: Regenerate.
1838
1839 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1840
1841         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1842         umwait.
1843         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1844         64-bit mode.
1845         * i386-tbl.h: Regenerated.
1846
1847 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1848
1849         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1850         PREFIX_MOD_1_0FAE_REG_6.
1851         (va_mode): New.
1852         (OP_E_register): Use va_mode.
1853         * i386-dis-evex.h (prefix_table):
1854         New instructions (see prefixes above).
1855         * i386-gen.c (cpu_flag_init): Add WAITPKG.
1856         (cpu_flags): Likewise.
1857         * i386-opc.h (enum): Likewise.
1858         (i386_cpu_flags): Likewise.
1859         * i386-opc.tbl: Add umonitor, umwait, tpause.
1860         * i386-init.h: Regenerate.
1861         * i386-tbl.h: Likewise.
1862
1863 2018-04-11  Alan Modra  <amodra@gmail.com>
1864
1865         * opcodes/i860-dis.c: Delete.
1866         * opcodes/i960-dis.c: Delete.
1867         * Makefile.am: Remove i860 and i960 support.
1868         * configure.ac: Likewise.
1869         * disassemble.c: Likewise.
1870         * disassemble.h: Likewise.
1871         * Makefile.in: Regenerate.
1872         * configure: Regenerate.
1873         * po/POTFILES.in: Regenerate.
1874
1875 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
1876
1877         PR binutils/23025
1878         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1879         to 0.
1880         (print_insn): Clear vex instead of vex.evex.
1881
1882 2018-04-04  Nick Clifton  <nickc@redhat.com>
1883
1884         * po/es.po: Updated Spanish translation.
1885
1886 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1887
1888         * i386-gen.c (opcode_modifiers): Delete VecESize.
1889         * i386-opc.h (VecESize): Delete.
1890         (struct i386_opcode_modifier): Delete vecesize.
1891         * i386-opc.tbl: Drop VecESize.
1892         * i386-tlb.h: Re-generate.
1893
1894 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1895
1896         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1897         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1898         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1899         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1900         * i386-tlb.h: Re-generate.
1901
1902 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1903
1904         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1905         Fold AVX512 forms
1906         * i386-tlb.h: Re-generate.
1907
1908 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1909
1910         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1911         (vex_len_table): Drop Y for vcvt*2si.
1912         (putop): Replace plain 'Y' handling by abort().
1913
1914 2018-03-28  Nick Clifton  <nickc@redhat.com>
1915
1916         PR 22988
1917         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1918         instructions with only a base address register.
1919         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1920         handle AARHC64_OPND_SVE_ADDR_R.
1921         (aarch64_print_operand): Likewise.
1922         * aarch64-asm-2.c: Regenerate.
1923         * aarch64_dis-2.c: Regenerate.
1924         * aarch64-opc-2.c: Regenerate.
1925
1926 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1927
1928         * i386-opc.tbl: Drop VecESize from register only insn forms and
1929         memory forms not allowing broadcast.
1930         * i386-tlb.h: Re-generate.
1931
1932 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1933
1934         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1935         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1936         sha256*): Drop Disp<N>.
1937
1938 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1939
1940         * i386-dis.c (EbndS, bnd_swap_mode): New.
1941         (prefix_table): Use EbndS.
1942         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1943         * i386-opc.tbl (bndmov): Move misplaced Load.
1944         * i386-tlb.h: Re-generate.
1945
1946 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1947
1948         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1949         templates allowing memory operands and folded ones for register
1950         only flavors.
1951         * i386-tlb.h: Re-generate.
1952
1953 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1954
1955         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1956         256-bit templates. Drop redundant leftover Disp<N>.
1957         * i386-tlb.h: Re-generate.
1958
1959 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
1960
1961         * riscv-opc.c (riscv_insn_types): New.
1962
1963 2018-03-13  Nick Clifton  <nickc@redhat.com>
1964
1965         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1966
1967 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1968
1969         * i386-opc.tbl: Add Optimize to clr.
1970         * i386-tbl.h: Regenerated.
1971
1972 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1973
1974         * i386-gen.c (opcode_modifiers): Remove OldGcc.
1975         * i386-opc.h (OldGcc): Removed.
1976         (i386_opcode_modifier): Remove oldgcc.
1977         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1978         instructions for old (<= 2.8.1) versions of gcc.
1979         * i386-tbl.h: Regenerated.
1980
1981 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1982
1983         * i386-opc.h (EVEXDYN): New.
1984         * i386-opc.tbl: Fold various AVX512VL templates.
1985         * i386-tlb.h: Re-generate.
1986
1987 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1988
1989         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1990         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1991         vpexpandd, vpexpandq): Fold AFX512VF templates.
1992         * i386-tlb.h: Re-generate.
1993
1994 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1995
1996         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1997         Fold 128- and 256-bit VEX-encoded templates.
1998         * i386-tlb.h: Re-generate.
1999
2000 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2001
2002         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2003         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2004         vpexpandd, vpexpandq): Fold AVX512F templates.
2005         * i386-tlb.h: Re-generate.
2006
2007 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2008
2009         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
2010         64-bit templates. Drop Disp<N>.
2011         * i386-tlb.h: Re-generate.
2012
2013 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2014
2015         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
2016         and 256-bit templates.
2017         * i386-tlb.h: Re-generate.
2018
2019 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2020
2021         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
2022         * i386-tlb.h: Re-generate.
2023
2024 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2025
2026         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
2027         Drop NoAVX.
2028         * i386-tlb.h: Re-generate.
2029
2030 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2031
2032         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
2033         * i386-tlb.h: Re-generate.
2034
2035 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2036
2037         * i386-gen.c (opcode_modifiers): Delete FloatD.
2038         * i386-opc.h (FloatD): Delete.
2039         (struct i386_opcode_modifier): Delete floatd.
2040         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
2041         FloatD by D.
2042         * i386-tlb.h: Re-generate.
2043
2044 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2045
2046         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
2047
2048 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2049
2050         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
2051         * i386-tlb.h: Re-generate.
2052
2053 2018-03-08  Jan Beulich  <jbeulich@suse.com>
2054
2055         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
2056         forms.
2057         * i386-tlb.h: Re-generate.
2058
2059 2018-03-07  Alan Modra  <amodra@gmail.com>
2060
2061         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
2062         bfd_arch_rs6000.
2063         * disassemble.h (print_insn_rs6000): Delete.
2064         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
2065         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
2066         (print_insn_rs6000): Delete.
2067
2068 2018-03-03  Alan Modra  <amodra@gmail.com>
2069
2070         * sysdep.h (opcodes_error_handler): Define.
2071         (_bfd_error_handler): Declare.
2072         * Makefile.am: Remove stray #.
2073         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
2074         EDIT" comment.
2075         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
2076         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
2077         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
2078         opcodes_error_handler to print errors.  Standardize error messages.
2079         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
2080         and include opintl.h.
2081         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
2082         * i386-gen.c: Standardize error messages.
2083         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
2084         * Makefile.in: Regenerate.
2085         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
2086         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
2087         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
2088         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
2089         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
2090         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
2091         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
2092         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
2093         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
2094         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
2095         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
2096         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
2097         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2098
2099 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
2100
2101         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
2102         vpsub[bwdq] instructions.
2103         * i386-tbl.h: Regenerated.
2104
2105 2018-03-01  Alan Modra  <amodra@gmail.com>
2106
2107         * configure.ac (ALL_LINGUAS): Sort.
2108         * configure: Regenerate.
2109
2110 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2111
2112         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
2113         macro by assignements.
2114
2115 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
2116
2117         PR gas/22871
2118         * i386-gen.c (opcode_modifiers): Add Optimize.
2119         * i386-opc.h (Optimize): New enum.
2120         (i386_opcode_modifier): Add optimize.
2121         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
2122         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2123         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2124         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2125         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2126         vpxord and vpxorq.
2127         * i386-tbl.h: Regenerated.
2128
2129 2018-02-26  Alan Modra  <amodra@gmail.com>
2130
2131         * crx-dis.c (getregliststring): Allocate a large enough buffer
2132         to silence false positive gcc8 warning.
2133
2134 2018-02-22  Shea Levy <shea@shealevy.com>
2135
2136         * disassemble.c (ARCH_riscv): Define if ARCH_all.
2137
2138 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
2139
2140         * i386-opc.tbl: Add {rex},
2141         * i386-tbl.h: Regenerated.
2142
2143 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
2144
2145         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2146         (mips16_opcodes): Replace `M' with `m' for "restore".
2147
2148 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2149
2150         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2151
2152 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
2153
2154         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2155         variable to `function_index'.
2156
2157 2018-02-13  Nick Clifton  <nickc@redhat.com>
2158
2159         PR 22823
2160         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2161         about truncation of printing.
2162
2163 2018-02-12  Henry Wong <henry@stuffedcow.net>
2164
2165         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2166
2167 2018-02-05  Nick Clifton  <nickc@redhat.com>
2168
2169         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2170
2171 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2172
2173         * i386-dis.c (enum): Add pconfig.
2174         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2175         (cpu_flags): Add CpuPCONFIG.
2176         * i386-opc.h (enum): Add CpuPCONFIG.
2177         (i386_cpu_flags): Add cpupconfig.
2178         * i386-opc.tbl: Add PCONFIG instruction.
2179         * i386-init.h: Regenerate.
2180         * i386-tbl.h: Likewise.
2181
2182 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2183
2184         * i386-dis.c (enum): Add PREFIX_0F09.
2185         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2186         (cpu_flags): Add CpuWBNOINVD.
2187         * i386-opc.h (enum): Add CpuWBNOINVD.
2188         (i386_cpu_flags): Add cpuwbnoinvd.
2189         * i386-opc.tbl: Add WBNOINVD instruction.
2190         * i386-init.h: Regenerate.
2191         * i386-tbl.h: Likewise.
2192
2193 2018-01-17  Jim Wilson  <jimw@sifive.com>
2194
2195         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2196
2197 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2198
2199         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2200         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2201         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2202         (cpu_flags): Add CpuIBT, CpuSHSTK.
2203         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2204         (i386_cpu_flags): Add cpuibt, cpushstk.
2205         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2206         * i386-init.h: Regenerate.
2207         * i386-tbl.h: Likewise.
2208
2209 2018-01-16  Nick Clifton  <nickc@redhat.com>
2210
2211         * po/pt_BR.po: Updated Brazilian Portugese translation.
2212         * po/de.po: Updated German translation.
2213
2214 2018-01-15  Jim Wilson  <jimw@sifive.com>
2215
2216         * riscv-opc.c (match_c_nop): New.
2217         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2218
2219 2018-01-15  Nick Clifton  <nickc@redhat.com>
2220
2221         * po/uk.po: Updated Ukranian translation.
2222
2223 2018-01-13  Nick Clifton  <nickc@redhat.com>
2224
2225         * po/opcodes.pot: Regenerated.
2226
2227 2018-01-13  Nick Clifton  <nickc@redhat.com>
2228
2229         * configure: Regenerate.
2230
2231 2018-01-13  Nick Clifton  <nickc@redhat.com>
2232
2233         2.30 branch created.
2234
2235 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2236
2237         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2238         * i386-tbl.h: Regenerate.
2239
2240 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2241
2242         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2243         * i386-tbl.h: Re-generate.
2244
2245 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2246
2247         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2248         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2249         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2250         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2251         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2252         Disp8MemShift of AVX512VL forms.
2253         * i386-tbl.h: Re-generate.
2254
2255 2018-01-09  Jim Wilson  <jimw@sifive.com>
2256
2257         * riscv-dis.c (maybe_print_address): If base_reg is zero,
2258         then the hi_addr value is zero.
2259
2260 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2261
2262         * arm-dis.c (arm_opcodes): Add csdb.
2263         (thumb32_opcodes): Add csdb.
2264
2265 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2266
2267         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2268         * aarch64-asm-2.c: Regenerate.
2269         * aarch64-dis-2.c: Regenerate.
2270         * aarch64-opc-2.c: Regenerate.
2271
2272 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
2273
2274         PR gas/22681
2275         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2276         Remove AVX512 vmovd with 64-bit operands.
2277         * i386-tbl.h: Regenerated.
2278
2279 2018-01-05  Jim Wilson  <jimw@sifive.com>
2280
2281         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2282         jalr.
2283
2284 2018-01-03  Alan Modra  <amodra@gmail.com>
2285
2286         Update year range in copyright notice of all files.
2287
2288 2018-01-02  Jan Beulich  <jbeulich@suse.com>
2289
2290         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2291         and OPERAND_TYPE_REGZMM entries.
2292
2293 For older changes see ChangeLog-2017
2294 \f
2295 Copyright (C) 2018 Free Software Foundation, Inc.
2296
2297 Copying and distribution of this file, with or without modification,
2298 are permitted in any medium without royalty provided the copyright
2299 notice and this notice are preserved.
2300
2301 Local Variables:
2302 mode: change-log
2303 left-margin: 8
2304 fill-column: 74
2305 version-control: never
2306 End: