opcodes/ChangeLog

   1 2020-05-21  Alan Modra  <amodra@gmail.com>
   2
   3         * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
   4         * sparc-dis.c: Likewise.
   5         * tic4x-dis.c: Likewise.
   6         * xtensa-dis.c: Likewise.
   7         * bpf-desc.c: Regenerate.
   8         * epiphany-desc.c: Regenerate.
   9         * fr30-desc.c: Regenerate.
  10         * frv-desc.c: Regenerate.
  11         * ip2k-desc.c: Regenerate.
  12         * iq2000-desc.c: Regenerate.
  13         * lm32-desc.c: Regenerate.
  14         * m32c-desc.c: Regenerate.
  15         * m32r-desc.c: Regenerate.
  16         * mep-asm.c: Regenerate.
  17         * mep-desc.c: Regenerate.
  18         * mt-desc.c: Regenerate.
  19         * or1k-desc.c: Regenerate.
  20         * xc16x-desc.c: Regenerate.
  21         * xstormy16-desc.c: Regenerate.
  22
  23 2020-05-20  Nelson Chu  <nelson.chu@sifive.com>
  24
  25         * riscv-opc.c (riscv_ext_version_table): The table used to store
  26         all information about the supported spec and the corresponding ISA
  27         versions.  Currently, only Zicsr is supported to verify the
  28         correctness of Z sub extension settings.  Others will be supported
  29         in the future patches.
  30         (struct isa_spec_t, isa_specs): List for all supported ISA spec
  31         classes and the corresponding strings.
  32         (riscv_get_isa_spec_class): New function.  Get the corresponding ISA
  33         spec class by giving a ISA spec string.
  34         * riscv-opc.c (struct priv_spec_t): New structure.
  35         (struct priv_spec_t priv_specs): List for all supported privilege spec
  36         classes and the corresponding strings.
  37         (riscv_get_priv_spec_class): New function.  Get the corresponding
  38         privilege spec class by giving a spec string.
  39         (riscv_get_priv_spec_name): New function.  Get the corresponding
  40         privilege spec string by giving a CSR version class.
  41         * riscv-dis.c: Updated since DECLARE_CSR is changed.
  42         * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
  43         according to the chosen version.  Build a hash table riscv_csr_hash to
  44         store the valid CSR for the chosen pirv verison.  Dump the direct
  45         CSR address rather than it's name if it is invalid.
  46         (parse_riscv_dis_option_without_args): New function.  Parse the options
  47         without arguments.
  48         (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
  49         parse the options without arguments first, and then handle the options
  50         with arguments.  Add the new option -Mpriv-spec, which has argument.
  51         * riscv-dis.c (print_riscv_disassembler_options): Add description
  52         about the new OBJDUMP option.
  53
  54 2020-05-19  Peter Bergner  <bergner@linux.ibm.com>
  55
  56         * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
  57         WC values on POWER10 sync, dcbf  and wait instructions.
  58         (insert_pl, extract_pl): New functions.
  59         (L2OPT, LS, WC): Use insert_ls and extract_ls.
  60         (LS3): New , 3-bit L for sync.
  61         (LS3, L3OPT): New, 3-bit L for sync and dcbf.
  62         (SC2, PL): New, 2-bit SC and PL for sync and wait.
  63         (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
  64         (XOPL3, XWCPL, XSYNCLS): New opcode macros.
  65         (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
  66         plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
  67         <wait>: Enable PL operand on POWER10.
  68         <dcbf>: Enable L3OPT operand on POWER10.
  69         <sync>: Enable SC2 operand on POWER10.
  70
  71 2020-05-19  Stafford Horne  <shorne@gmail.com>
  72
  73         PR 25184
  74         * or1k-asm.c: Regenerate.
  75         * or1k-desc.c: Regenerate.
  76         * or1k-desc.h: Regenerate.
  77         * or1k-dis.c: Regenerate.
  78         * or1k-ibld.c: Regenerate.
  79         * or1k-opc.c: Regenerate.
  80         * or1k-opc.h: Regenerate.
  81         * or1k-opinst.c: Regenerate.
  82
  83 2020-05-11  Alan Modra  <amodra@gmail.com>
  84
  85         * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
  86         xsmaxcqp, xsmincqp.
  87
  88 2020-05-11  Alan Modra  <amodra@gmail.com>
  89
  90         * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
  91         stxvrbx, stxvrhx, stxvrwx, stxvrdx.
  92
  93 2020-05-11  Alan Modra  <amodra@gmail.com>
  94
  95         * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
  96
  97 2020-05-11  Alan Modra  <amodra@gmail.com>
  98
  99         * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
 100         vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
 101
 102 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 103
 104         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
 105         mnemonics.
 106
 107 2020-05-11  Alan Modra  <amodra@gmail.com>
 108
 109         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
 110         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
 111         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
 112         (prefix_opcodes): Add xxeval.
 113
 114 2020-05-11  Alan Modra  <amodra@gmail.com>
 115
 116         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
 117         xxgenpcvwm, xxgenpcvdm.
 118
 119 2020-05-11  Alan Modra  <amodra@gmail.com>
 120
 121         * ppc-opc.c (MP, VXVAM_MASK): Define.
 122         (VXVAPS_MASK): Use VXVA_MASK.
 123         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
 124         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
 125         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
 126         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
 127
 128 2020-05-11  Alan Modra  <amodra@gmail.com>
 129             Peter Bergner  <bergner@linux.ibm.com>
 130
 131         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
 132         New functions.
 133         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
 134         YMSK2, XA6a, XA6ap, XB6a entries.
 135         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
 136         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
 137         (PPCVSX4): Define.
 138         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
 139         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
 140         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
 141         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
 142         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
 143         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
 144         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
 145         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
 146         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
 147         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
 148         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
 149         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
 150         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
 151         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
 152
 153 2020-05-11  Alan Modra  <amodra@gmail.com>
 154
 155         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
 156         (insert_xts, extract_xts): New functions.
 157         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
 158         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
 159         (VXRC_MASK, VXSH_MASK): Define.
 160         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
 161         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
 162         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
 163         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
 164         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
 165         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
 166         xxblendvh, xxblendvw, xxblendvd, xxpermx.
 167
 168 2020-05-11  Alan Modra  <amodra@gmail.com>
 169
 170         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
 171         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
 172         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
 173         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
 174         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
 175
 176 2020-05-11  Alan Modra  <amodra@gmail.com>
 177
 178         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
 179         (XTP, DQXP, DQXP_MASK): Define.
 180         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
 181         (prefix_opcodes): Add plxvp and pstxvp.
 182
 183 2020-05-11  Alan Modra  <amodra@gmail.com>
 184
 185         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
 186         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
 187         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
 188
 189 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 190
 191         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
 192
 193 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 194
 195         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
 196         (L1OPT): Define.
 197         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
 198
 199 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 200
 201         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
 202
 203 2020-05-11  Alan Modra  <amodra@gmail.com>
 204
 205         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
 206
 207 2020-05-11  Alan Modra  <amodra@gmail.com>
 208
 209         * ppc-dis.c (ppc_opts): Add "power10" entry.
 210         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
 211         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
 212
 213 2020-05-11  Nick Clifton  <nickc@redhat.com>
 214
 215         * po/fr.po: Updated French translation.
 216
 217 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
 218
 219         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
 220         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
 221         (operand_general_constraint_met_p): validate
 222         AARCH64_OPND_UNDEFINED.
 223         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
 224         for FLD_imm16_2.
 225         * aarch64-asm-2.c: Regenerated.
 226         * aarch64-dis-2.c: Regenerated.
 227         * aarch64-opc-2.c: Regenerated.
 228
 229 2020-04-29  Nick Clifton  <nickc@redhat.com>
 230
 231         PR 22699
 232         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
 233         and SETRC insns.
 234
 235 2020-04-29  Nick Clifton  <nickc@redhat.com>
 236
 237         * po/sv.po: Updated Swedish translation.
 238
 239 2020-04-29  Nick Clifton  <nickc@redhat.com>
 240
 241         PR 22699
 242         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
 243         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
 244         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
 245         IMM0_8U case.
 246
 247 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
 248
 249         PR 25848
 250         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
 251         cmpi only on m68020up and cpu32.
 252
 253 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 254
 255         * aarch64-asm.c (aarch64_ins_none): New.
 256         * aarch64-asm.h (ins_none): New declaration.
 257         * aarch64-dis.c (aarch64_ext_none): New.
 258         * aarch64-dis.h (ext_none): New declaration.
 259         * aarch64-opc.c (aarch64_print_operand): Update case for
 260         AARCH64_OPND_BARRIER_PSB.
 261         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
 262         (AARCH64_OPERANDS): Update inserter/extracter for
 263         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
 264         * aarch64-asm-2.c: Regenerated.
 265         * aarch64-dis-2.c: Regenerated.
 266         * aarch64-opc-2.c: Regenerated.
 267
 268 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 269
 270         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
 271         (aarch64_feature_ras, RAS): Likewise.
 272         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
 273         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
 274         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
 275         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
 276         * aarch64-asm-2.c: Regenerated.
 277         * aarch64-dis-2.c: Regenerated.
 278         * aarch64-opc-2.c: Regenerated.
 279
 280 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
 281
 282         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
 283         (print_insn_neon): Support disassembly of conditional
 284         instructions.
 285
 286 2020-02-16  David Faust  <david.faust@oracle.com>
 287
 288         * bpf-desc.c: Regenerate.
 289         * bpf-desc.h: Likewise.
 290         * bpf-opc.c: Regenerate.
 291         * bpf-opc.h: Likewise.
 292
 293 2020-04-07  Lili Cui  <lili.cui@intel.com>
 294
 295         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
 296         (prefix_table): New instructions (see prefixes above).
 297         (rm_table): Likewise
 298         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
 299         CPU_ANY_TSXLDTRK_FLAGS.
 300         (cpu_flags): Add CpuTSXLDTRK.
 301         * i386-opc.h (enum): Add CpuTSXLDTRK.
 302         (i386_cpu_flags): Add cputsxldtrk.
 303         * i386-opc.tbl: Add XSUSPLDTRK insns.
 304         * i386-init.h: Regenerate.
 305         * i386-tbl.h: Likewise.
 306
 307 2020-04-02  Lili Cui  <lili.cui@intel.com>
 308
 309         * i386-dis.c (prefix_table): New instructions serialize.
 310         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
 311         CPU_ANY_SERIALIZE_FLAGS.
 312         (cpu_flags): Add CpuSERIALIZE.
 313         * i386-opc.h (enum): Add CpuSERIALIZE.
 314         (i386_cpu_flags): Add cpuserialize.
 315         * i386-opc.tbl: Add SERIALIZE insns.
 316         * i386-init.h: Regenerate.
 317         * i386-tbl.h: Likewise.
 318
 319 2020-03-26  Alan Modra  <amodra@gmail.com>
 320
 321         * disassemble.h (opcodes_assert): Declare.
 322         (OPCODES_ASSERT): Define.
 323         * disassemble.c: Don't include assert.h.  Include opintl.h.
 324         (opcodes_assert): New function.
 325         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 326         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 327         calculate maxlen.  Omit insn decoding when insn length exceeds
 328         maxlen.  Exit from nibble loop when looking for E, before
 329         accessing next data byte.  Move processing of E outside loop.
 330         Replace tests of maxlen in loop with assertions.
 331
 332 2020-03-26  Alan Modra  <amodra@gmail.com>
 333
 334         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 335
 336 2020-03-25  Alan Modra  <amodra@gmail.com>
 337
 338         * z80-dis.c (suffix): Init mybuf.
 339
 340 2020-03-22  Alan Modra  <amodra@gmail.com>
 341
 342         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 343         successflly read from section.
 344
 345 2020-03-22  Alan Modra  <amodra@gmail.com>
 346
 347         * arc-dis.c (find_format): Use ISO C string concatenation rather
 348         than line continuation within a string.  Don't access needs_limm
 349         before testing opcode != NULL.
 350
 351 2020-03-22  Alan Modra  <amodra@gmail.com>
 352
 353         * ns32k-dis.c (print_insn_arg): Update comment.
 354         (print_insn_ns32k): Reduce size of index_offset array, and
 355         initialize, passing -1 to print_insn_arg for args that are not
 356         an index.  Don't exit arg loop early.  Abort on bad arg number.
 357
 358 2020-03-22  Alan Modra  <amodra@gmail.com>
 359
 360         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 361         * s12z-opc.c: Formatting.
 362         (operands_f): Return an int.
 363         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 364         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 365         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 366         (exg_sex_discrim): Likewise.
 367         (create_immediate_operand, create_bitfield_operand),
 368         (create_register_operand_with_size, create_register_all_operand),
 369         (create_register_all16_operand, create_simple_memory_operand),
 370         (create_memory_operand, create_memory_auto_operand): Don't
 371         segfault on malloc failure.
 372         (z_ext24_decode): Return an int status, negative on fail, zero
 373         on success.
 374         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 375         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 376         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 377         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 378         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 379         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 380         (loop_primitive_decode, shift_decode, psh_pul_decode),
 381         (bit_field_decode): Similarly.
 382         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 383         to return value, update callers.
 384         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 385         Don't segfault on NULL operand.
 386         (decode_operation): Return OP_INVALID on first fail.
 387         (decode_s12z): Check all reads, returning -1 on fail.
 388
 389 2020-03-20  Alan Modra  <amodra@gmail.com>
 390
 391         * metag-dis.c (print_insn_metag): Don't ignore status from
 392         read_memory_func.
 393
 394 2020-03-20  Alan Modra  <amodra@gmail.com>
 395
 396         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 397         Initialize parts of buffer not written when handling a possible
 398         2-byte insn at end of section.  Don't attempt decoding of such
 399         an insn by the 4-byte machinery.
 400
 401 2020-03-20  Alan Modra  <amodra@gmail.com>
 402
 403         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 404         partially filled buffer.  Prevent lookup of 4-byte insns when
 405         only VLE 2-byte insns are possible due to section size.  Print
 406         ".word" rather than ".long" for 2-byte leftovers.
 407
 408 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 409
 410         PR 25641
 411         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 412
 413 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 414
 415         * i386-dis.c (X86_64_0D): Rename to ...
 416         (X86_64_0E): ... this.
 417
 418 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 419
 420         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 421         * Makefile.in: Regenerated.
 422
 423 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 424
 425         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 426         3-operand pseudos.
 427         * i386-tbl.h: Re-generate.
 428
 429 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 430
 431         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 432         vprot*, vpsha*, and vpshl*.
 433         * i386-tbl.h: Re-generate.
 434
 435 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 436
 437         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 438         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 439         * i386-tbl.h: Re-generate.
 440
 441 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 442
 443         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 444         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 445         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 446         * i386-tbl.h: Re-generate.
 447
 448 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 449
 450         * i386-gen.c (struct template_arg, struct template_instance,
 451         struct template_param, struct template, templates,
 452         parse_template, expand_templates): New.
 453         (process_i386_opcodes): Various local variables moved to
 454         expand_templates. Call parse_template and expand_templates.
 455         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 456         * i386-tbl.h: Re-generate.
 457
 458 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 459
 460         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 461         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 462         register and memory source templates. Replace VexW= by VexW*
 463         where applicable.
 464         * i386-tbl.h: Re-generate.
 465
 466 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 467
 468         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 469         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 470         * i386-tbl.h: Re-generate.
 471
 472 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 473
 474         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 475         * i386-tbl.h: Re-generate.
 476
 477 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 478
 479         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 480         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 481         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 482         VexW0 on SSE2AVX variants.
 483         (vmovq): Drop NoRex64 from XMM/XMM variants.
 484         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 485         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 486         applicable use VexW0.
 487         * i386-tbl.h: Re-generate.
 488
 489 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 490
 491         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 492         * i386-opc.h (Rex64): Delete.
 493         (struct i386_opcode_modifier): Remove rex64 field.
 494         * i386-opc.tbl (crc32): Drop Rex64.
 495         Replace Rex64 with Size64 everywhere else.
 496         * i386-tbl.h: Re-generate.
 497
 498 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 499
 500         * i386-dis.c (OP_E_memory): Exclude recording of used address
 501         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 502         addressed memory operands for MPX insns.
 503
 504 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 505
 506         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 507         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 508         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 509         (ptwrite): Split into non-64-bit and 64-bit forms.
 510         * i386-tbl.h: Re-generate.
 511
 512 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 513
 514         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 515         template.
 516         * i386-tbl.h: Re-generate.
 517
 518 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 519
 520         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 521         (prefix_table): Move vmmcall here. Add vmgexit.
 522         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 523         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 524         (cpu_flags): Add CpuSEV_ES entry.
 525         * i386-opc.h (CpuSEV_ES): New.
 526         (union i386_cpu_flags): Add cpusev_es field.
 527         * i386-opc.tbl (vmgexit): New.
 528         * i386-init.h, i386-tbl.h: Re-generate.
 529
 530 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 531
 532         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 533         with MnemonicSize.
 534         * i386-opc.h (IGNORESIZE): New.
 535         (DEFAULTSIZE): Likewise.
 536         (IgnoreSize): Removed.
 537         (DefaultSize): Likewise.
 538         (MnemonicSize): New.
 539         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 540         mnemonicsize.
 541         * i386-opc.tbl (IgnoreSize): New.
 542         (DefaultSize): Likewise.
 543         * i386-tbl.h: Regenerated.
 544
 545 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 546
 547         PR 25627
 548         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 549         instructions.
 550
 551 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 552
 553         PR gas/25622
 554         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 555         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 556         * i386-tbl.h: Regenerated.
 557
 558 2020-02-26  Alan Modra  <amodra@gmail.com>
 559
 560         * aarch64-asm.c: Indent labels correctly.
 561         * aarch64-dis.c: Likewise.
 562         * aarch64-gen.c: Likewise.
 563         * aarch64-opc.c: Likewise.
 564         * alpha-dis.c: Likewise.
 565         * i386-dis.c: Likewise.
 566         * nds32-asm.c: Likewise.
 567         * nfp-dis.c: Likewise.
 568         * visium-dis.c: Likewise.
 569
 570 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 571
 572         * arc-regs.h (int_vector_base): Make it available for all ARC
 573         CPUs.
 574
 575 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 576
 577         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 578         changed.
 579
 580 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 581
 582         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 583         c.mv/c.li if rs1 is zero.
 584
 585 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 586
 587         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 588         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 589         CPU_POPCNT_FLAGS.
 590         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 591         * i386-opc.h (CpuABM): Removed.
 592         (CpuPOPCNT): New.
 593         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 594         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 595         popcnt.  Remove CpuABM from lzcnt.
 596         * i386-init.h: Regenerated.
 597         * i386-tbl.h: Likewise.
 598
 599 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 600
 601         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 602         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 603         VexW1 instead of open-coding them.
 604         * i386-tbl.h: Re-generate.
 605
 606 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 607
 608         * i386-opc.tbl (AddrPrefixOpReg): Define.
 609         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 610         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 611         templates. Drop NoRex64.
 612         * i386-tbl.h: Re-generate.
 613
 614 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 615
 616         PR gas/6518
 617         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 618         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 619         into Intel syntax instance (with Unpsecified) and AT&T one
 620         (without).
 621         (vcvtneps2bf16): Likewise, along with folding the two so far
 622         separate ones.
 623         * i386-tbl.h: Re-generate.
 624
 625 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 626
 627         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 628         CPU_ANY_SSE4A_FLAGS.
 629
 630 2020-02-17  Alan Modra  <amodra@gmail.com>
 631
 632         * i386-gen.c (cpu_flag_init): Correct last change.
 633
 634 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 635
 636         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 637         CPU_ANY_SSE4_FLAGS.
 638
 639 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 640
 641         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 642         (movzx): Likewise.
 643
 644 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 645
 646         PR gas/25438
 647         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 648         destination for Cpu64-only variant.
 649         (movzx): Fold patterns.
 650         * i386-tbl.h: Re-generate.
 651
 652 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 653
 654         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 655         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 656         CPU_ANY_SSE4_FLAGS entry.
 657         * i386-init.h: Re-generate.
 658
 659 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 660
 661         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 662         with Unspecified, making the present one AT&T syntax only.
 663         * i386-tbl.h: Re-generate.
 664
 665 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 666
 667         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 668         * i386-tbl.h: Re-generate.
 669
 670 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 671
 672         PR gas/24546
 673         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 674         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 675         Amd64 and Intel64 templates.
 676         (call, jmp): Likewise for far indirect variants. Dro
 677         Unspecified.
 678         * i386-tbl.h: Re-generate.
 679
 680 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 681
 682         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 683         * i386-opc.h (ShortForm): Delete.
 684         (struct i386_opcode_modifier): Remove shortform field.
 685         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 686         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 687         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 688         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 689         Drop ShortForm.
 690         * i386-tbl.h: Re-generate.
 691
 692 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 693
 694         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 695         fucompi): Drop ShortForm from operand-less templates.
 696         * i386-tbl.h: Re-generate.
 697
 698 2020-02-11  Alan Modra  <amodra@gmail.com>
 699
 700         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 701         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 702         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 703         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 704         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 705
 706 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 707
 708         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 709         (cde_opcodes): Add VCX* instructions.
 710
 711 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 712             Matthew Malcomson  <matthew.malcomson@arm.com>
 713
 714         * arm-dis.c (struct cdeopcode32): New.
 715         (CDE_OPCODE): New macro.
 716         (cde_opcodes): New disassembly table.
 717         (regnames): New option to table.
 718         (cde_coprocs): New global variable.
 719         (print_insn_cde): New
 720         (print_insn_thumb32): Use print_insn_cde.
 721         (parse_arm_disassembler_options): Parse coprocN args.
 722
 723 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 724
 725         PR gas/25516
 726         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 727         with ISA64.
 728         * i386-opc.h (AMD64): Removed.
 729         (Intel64): Likewose.
 730         (AMD64): New.
 731         (INTEL64): Likewise.
 732         (INTEL64ONLY): Likewise.
 733         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 734         * i386-opc.tbl (Amd64): New.
 735         (Intel64): Likewise.
 736         (Intel64Only): Likewise.
 737         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 738         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 739         * i386-tbl.h: Regenerated.
 740
 741 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 742
 743         PR 25469
 744         * z80-dis.c: Add support for GBZ80 opcodes.
 745
 746 2020-02-04  Alan Modra  <amodra@gmail.com>
 747
 748         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 749
 750 2020-02-03  Alan Modra  <amodra@gmail.com>
 751
 752         * m32c-ibld.c: Regenerate.
 753
 754 2020-02-01  Alan Modra  <amodra@gmail.com>
 755
 756         * frv-ibld.c: Regenerate.
 757
 758 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 759
 760         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 761         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 762         (OP_E_memory): Replace xmm_mdq_mode case label by
 763         vex_scalar_w_dq_mode one.
 764         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 765
 766 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 767
 768         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 769         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 770         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 771         (intel_operand_size): Drop vex_w_dq_mode case label.
 772
 773 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 774
 775         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 776         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 777
 778 2020-01-30  Alan Modra  <amodra@gmail.com>
 779
 780         * m32c-ibld.c: Regenerate.
 781
 782 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 783
 784         * bpf-opc.c: Regenerate.
 785
 786 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 787
 788         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 789         (dis386): Use them to replace C2/C3 table entries.
 790         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 791         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 792         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 793         * i386-tbl.h: Re-generate.
 794
 795 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 796
 797         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 798         forms.
 799         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 800         DefaultSize.
 801         * i386-tbl.h: Re-generate.
 802
 803 2020-01-30  Alan Modra  <amodra@gmail.com>
 804
 805         * tic4x-dis.c (tic4x_dp): Make unsigned.
 806
 807 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 808             Jan Beulich  <jbeulich@suse.com>
 809
 810         PR binutils/25445
 811         * i386-dis.c (MOVSXD_Fixup): New function.
 812         (movsxd_mode): New enum.
 813         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 814         (intel_operand_size): Handle movsxd_mode.
 815         (OP_E_register): Likewise.
 816         (OP_G): Likewise.
 817         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 818         register on movsxd.  Add movsxd with 16-bit destination register
 819         for AMD64 and Intel64 ISAs.
 820         * i386-tbl.h: Regenerated.
 821
 822 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 823
 824         PR 25403
 825         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 826         * aarch64-asm-2.c: Regenerate
 827         * aarch64-dis-2.c: Likewise.
 828         * aarch64-opc-2.c: Likewise.
 829
 830 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 831
 832         * i386-opc.tbl (sysret): Drop DefaultSize.
 833         * i386-tbl.h: Re-generate.
 834
 835 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 836
 837         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 838         Dword.
 839         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 840         * i386-tbl.h: Re-generate.
 841
 842 2020-01-20  Nick Clifton  <nickc@redhat.com>
 843
 844         * po/de.po: Updated German translation.
 845         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 846         * po/uk.po: Updated Ukranian translation.
 847
 848 2020-01-20  Alan Modra  <amodra@gmail.com>
 849
 850         * hppa-dis.c (fput_const): Remove useless cast.
 851
 852 2020-01-20  Alan Modra  <amodra@gmail.com>
 853
 854         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 855
 856 2020-01-18  Nick Clifton  <nickc@redhat.com>
 857
 858         * configure: Regenerate.
 859         * po/opcodes.pot: Regenerate.
 860
 861 2020-01-18  Nick Clifton  <nickc@redhat.com>
 862
 863         Binutils 2.34 branch created.
 864
 865 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 866
 867         * opintl.h: Fix spelling error (seperate).
 868
 869 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 870
 871         * i386-opc.tbl: Add {vex} pseudo prefix.
 872         * i386-tbl.h: Regenerated.
 873
 874 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 875
 876         PR 25376
 877         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 878         (neon_opcodes): Likewise.
 879         (select_arm_features): Make sure we enable MVE bits when selecting
 880         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 881         any architecture.
 882
 883 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 884
 885         * i386-opc.tbl: Drop stale comment from XOP section.
 886
 887 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 888
 889         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 890         (extractps): Add VexWIG to SSE2AVX forms.
 891         * i386-tbl.h: Re-generate.
 892
 893 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 894
 895         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 896         Size64 from and use VexW1 on SSE2AVX forms.
 897         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 898         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 899         * i386-tbl.h: Re-generate.
 900
 901 2020-01-15  Alan Modra  <amodra@gmail.com>
 902
 903         * tic4x-dis.c (tic4x_version): Make unsigned long.
 904         (optab, optab_special, registernames): New file scope vars.
 905         (tic4x_print_register): Set up registernames rather than
 906         malloc'd registertable.
 907         (tic4x_disassemble): Delete optable and optable_special.  Use
 908         optab and optab_special instead.  Throw away old optab,
 909         optab_special and registernames when info->mach changes.
 910
 911 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 912
 913         PR 25377
 914         * z80-dis.c (suffix): Use .db instruction to generate double
 915         prefix.
 916
 917 2020-01-14  Alan Modra  <amodra@gmail.com>
 918
 919         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 920         values to unsigned before shifting.
 921
 922 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 923
 924         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 925         flow instructions.
 926         (print_insn_thumb16, print_insn_thumb32): Likewise.
 927         (print_insn): Initialize the insn info.
 928         * i386-dis.c (print_insn): Initialize the insn info fields, and
 929         detect jumps.
 930
 931 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 932
 933         * arc-opc.c (C_NE): Make it required.
 934
 935 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 936
 937         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 938         reserved register name.
 939
 940 2020-01-13  Alan Modra  <amodra@gmail.com>
 941
 942         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 943         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 944
 945 2020-01-13  Alan Modra  <amodra@gmail.com>
 946
 947         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 948         result of wasm_read_leb128 in a uint64_t and check that bits
 949         are not lost when copying to other locals.  Use uint32_t for
 950         most locals.  Use PRId64 when printing int64_t.
 951
 952 2020-01-13  Alan Modra  <amodra@gmail.com>
 953
 954         * score-dis.c: Formatting.
 955         * score7-dis.c: Formatting.
 956
 957 2020-01-13  Alan Modra  <amodra@gmail.com>
 958
 959         * score-dis.c (print_insn_score48): Use unsigned variables for
 960         unsigned values.  Don't left shift negative values.
 961         (print_insn_score32): Likewise.
 962         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 963
 964 2020-01-13  Alan Modra  <amodra@gmail.com>
 965
 966         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 967
 968 2020-01-13  Alan Modra  <amodra@gmail.com>
 969
 970         * fr30-ibld.c: Regenerate.
 971
 972 2020-01-13  Alan Modra  <amodra@gmail.com>
 973
 974         * xgate-dis.c (print_insn): Don't left shift signed value.
 975         (ripBits): Formatting, use 1u.
 976
 977 2020-01-10  Alan Modra  <amodra@gmail.com>
 978
 979         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 980         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 981
 982 2020-01-10  Alan Modra  <amodra@gmail.com>
 983
 984         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 985         and XRREG value earlier to avoid a shift with negative exponent.
 986         * m10200-dis.c (disassemble): Similarly.
 987
 988 2020-01-09  Nick Clifton  <nickc@redhat.com>
 989
 990         PR 25224
 991         * z80-dis.c (ld_ii_ii): Use correct cast.
 992
 993 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 994
 995         PR 25224
 996         * z80-dis.c (ld_ii_ii): Use character constant when checking
 997         opcode byte value.
 998
 999 2020-01-09  Jan Beulich  <jbeulich@suse.com>
1000
1001         * i386-dis.c (SEP_Fixup): New.
1002         (SEP): Define.
1003         (dis386_twobyte): Use it for sysenter/sysexit.
1004         (enum x86_64_isa): Change amd64 enumerator to value 1.
1005         (OP_J): Compare isa64 against intel64 instead of amd64.
1006         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1007         forms.
1008         * i386-tbl.h: Re-generate.
1009
1010 2020-01-08  Alan Modra  <amodra@gmail.com>
1011
1012         * z8k-dis.c: Include libiberty.h
1013         (instr_data_s): Make max_fetched unsigned.
1014         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1015         Don't exceed byte_info bounds.
1016         (output_instr): Make num_bytes unsigned.
1017         (unpack_instr): Likewise for nibl_count and loop.
1018         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1019         idx unsigned.
1020         * z8k-opc.h: Regenerate.
1021
1022 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
1023
1024         * arc-tbl.h (llock): Use 'LLOCK' as class.
1025         (llockd): Likewise.
1026         (scond): Use 'SCOND' as class.
1027         (scondd): Likewise.
1028         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1029         (scondd): Likewise.
1030
1031 2020-01-06  Alan Modra  <amodra@gmail.com>
1032
1033         * m32c-ibld.c: Regenerate.
1034
1035 2020-01-06  Alan Modra  <amodra@gmail.com>
1036
1037         PR 25344
1038         * z80-dis.c (suffix): Don't use a local struct buffer copy.
1039         Peek at next byte to prevent recursion on repeated prefix bytes.
1040         Ensure uninitialised "mybuf" is not accessed.
1041         (print_insn_z80): Don't zero n_fetch and n_used here,..
1042         (print_insn_z80_buf): ..do it here instead.
1043
1044 2020-01-04  Alan Modra  <amodra@gmail.com>
1045
1046         * m32r-ibld.c: Regenerate.
1047
1048 2020-01-04  Alan Modra  <amodra@gmail.com>
1049
1050         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1051
1052 2020-01-04  Alan Modra  <amodra@gmail.com>
1053
1054         * crx-dis.c (match_opcode): Avoid shift left of signed value.
1055
1056 2020-01-04  Alan Modra  <amodra@gmail.com>
1057
1058         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1059
1060 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1061
1062         * aarch64-tbl.h (aarch64_opcode_table): Use
1063         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1064
1065 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1066
1067         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1068         forms of SUDOT and USDOT.
1069
1070 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1071
1072         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1073         uzip{1,2}.
1074         * opcodes/aarch64-dis-2.c: Re-generate.
1075
1076 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1077
1078         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1079         FMMLA encoding.
1080         * opcodes/aarch64-dis-2.c: Re-generate.
1081
1082 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
1083
1084         * z80-dis.c: Add support for eZ80 and Z80 instructions.
1085
1086 2020-01-01  Alan Modra  <amodra@gmail.com>
1087
1088         Update year range in copyright notice of all files.
1089
1090 For older changes see ChangeLog-2019
1091 \f
1092 Copyright (C) 2020 Free Software Foundation, Inc.
1093
1094 Copying and distribution of this file, with or without modification,
1095 are permitted in any medium without royalty provided the copyright
1096 notice and this notice are preserved.
1097
1098 Local Variables:
1099 mode: change-log
1100 left-margin: 8
1101 fill-column: 74
1102 version-control: never
1103 End: