opcodes/ChangeLog

   1 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
   2
   3         PR 25641
   4         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
   5
   6 2020-03-13  Jan Beulich  <jbeulich@suse.com>
   7
   8         * i386-dis.c (X86_64_0D): Rename to ...
   9         (X86_64_0E): ... this.
  10
  11 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
  12
  13         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
  14         * Makefile.in: Regenerated.
  15
  16 2020-03-09  Jan Beulich  <jbeulich@suse.com>
  17
  18         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
  19         3-operand pseudos.
  20         * i386-tbl.h: Re-generate.
  21
  22 2020-03-09  Jan Beulich  <jbeulich@suse.com>
  23
  24         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
  25         vprot*, vpsha*, and vpshl*.
  26         * i386-tbl.h: Re-generate.
  27
  28 2020-03-09  Jan Beulich  <jbeulich@suse.com>
  29
  30         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
  31         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
  32         * i386-tbl.h: Re-generate.
  33
  34 2020-03-09  Jan Beulich  <jbeulich@suse.com>
  35
  36         * i386-gen.c (set_bitfield): Ignore zero-length field names.
  37         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
  38         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
  39         * i386-tbl.h: Re-generate.
  40
  41 2020-03-09  Jan Beulich  <jbeulich@suse.com>
  42
  43         * i386-gen.c (struct template_arg, struct template_instance,
  44         struct template_param, struct template, templates,
  45         parse_template, expand_templates): New.
  46         (process_i386_opcodes): Various local variables moved to
  47         expand_templates. Call parse_template and expand_templates.
  48         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
  49         * i386-tbl.h: Re-generate.
  50
  51 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  52
  53         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
  54         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
  55         register and memory source templates. Replace VexW= by VexW*
  56         where applicable.
  57         * i386-tbl.h: Re-generate.
  58
  59 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  60
  61         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
  62         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
  63         * i386-tbl.h: Re-generate.
  64
  65 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  66
  67         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
  68         * i386-tbl.h: Re-generate.
  69
  70 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  71
  72         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
  73         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
  74         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
  75         VexW0 on SSE2AVX variants.
  76         (vmovq): Drop NoRex64 from XMM/XMM variants.
  77         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
  78         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
  79         applicable use VexW0.
  80         * i386-tbl.h: Re-generate.
  81
  82 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  83
  84         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
  85         * i386-opc.h (Rex64): Delete.
  86         (struct i386_opcode_modifier): Remove rex64 field.
  87         * i386-opc.tbl (crc32): Drop Rex64.
  88         Replace Rex64 with Size64 everywhere else.
  89         * i386-tbl.h: Re-generate.
  90
  91 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  92
  93         * i386-dis.c (OP_E_memory): Exclude recording of used address
  94         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
  95         addressed memory operands for MPX insns.
  96
  97 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  98
  99         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 100         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 101         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 102         (ptwrite): Split into non-64-bit and 64-bit forms.
 103         * i386-tbl.h: Re-generate.
 104
 105 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 106
 107         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 108         template.
 109         * i386-tbl.h: Re-generate.
 110
 111 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 112
 113         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 114         (prefix_table): Move vmmcall here. Add vmgexit.
 115         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 116         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 117         (cpu_flags): Add CpuSEV_ES entry.
 118         * i386-opc.h (CpuSEV_ES): New.
 119         (union i386_cpu_flags): Add cpusev_es field.
 120         * i386-opc.tbl (vmgexit): New.
 121         * i386-init.h, i386-tbl.h: Re-generate.
 122
 123 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 124
 125         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 126         with MnemonicSize.
 127         * i386-opc.h (IGNORESIZE): New.
 128         (DEFAULTSIZE): Likewise.
 129         (IgnoreSize): Removed.
 130         (DefaultSize): Likewise.
 131         (MnemonicSize): New.
 132         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 133         mnemonicsize.
 134         * i386-opc.tbl (IgnoreSize): New.
 135         (DefaultSize): Likewise.
 136         * i386-tbl.h: Regenerated.
 137
 138 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 139
 140         PR 25627
 141         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 142         instructions.
 143
 144 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 145
 146         PR gas/25622
 147         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 148         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 149         * i386-tbl.h: Regenerated.
 150
 151 2020-02-26  Alan Modra  <amodra@gmail.com>
 152
 153         * aarch64-asm.c: Indent labels correctly.
 154         * aarch64-dis.c: Likewise.
 155         * aarch64-gen.c: Likewise.
 156         * aarch64-opc.c: Likewise.
 157         * alpha-dis.c: Likewise.
 158         * i386-dis.c: Likewise.
 159         * nds32-asm.c: Likewise.
 160         * nfp-dis.c: Likewise.
 161         * visium-dis.c: Likewise.
 162
 163 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 164
 165         * arc-regs.h (int_vector_base): Make it available for all ARC
 166         CPUs.
 167
 168 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 169
 170         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 171         changed.
 172
 173 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 174
 175         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 176         c.mv/c.li if rs1 is zero.
 177
 178 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 179
 180         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 181         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 182         CPU_POPCNT_FLAGS.
 183         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 184         * i386-opc.h (CpuABM): Removed.
 185         (CpuPOPCNT): New.
 186         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 187         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 188         popcnt.  Remove CpuABM from lzcnt.
 189         * i386-init.h: Regenerated.
 190         * i386-tbl.h: Likewise.
 191
 192 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 193
 194         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 195         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 196         VexW1 instead of open-coding them.
 197         * i386-tbl.h: Re-generate.
 198
 199 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 200
 201         * i386-opc.tbl (AddrPrefixOpReg): Define.
 202         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 203         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 204         templates. Drop NoRex64.
 205         * i386-tbl.h: Re-generate.
 206
 207 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 208
 209         PR gas/6518
 210         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 211         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 212         into Intel syntax instance (with Unpsecified) and AT&T one
 213         (without).
 214         (vcvtneps2bf16): Likewise, along with folding the two so far
 215         separate ones.
 216         * i386-tbl.h: Re-generate.
 217
 218 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 219
 220         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 221         CPU_ANY_SSE4A_FLAGS.
 222
 223 2020-02-17  Alan Modra  <amodra@gmail.com>
 224
 225         * i386-gen.c (cpu_flag_init): Correct last change.
 226
 227 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 228
 229         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 230         CPU_ANY_SSE4_FLAGS.
 231
 232 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 233
 234         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 235         (movzx): Likewise.
 236
 237 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 238
 239         PR gas/25438
 240         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 241         destination for Cpu64-only variant.
 242         (movzx): Fold patterns.
 243         * i386-tbl.h: Re-generate.
 244
 245 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 246
 247         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 248         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 249         CPU_ANY_SSE4_FLAGS entry.
 250         * i386-init.h: Re-generate.
 251
 252 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 253
 254         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 255         with Unspecified, making the present one AT&T syntax only.
 256         * i386-tbl.h: Re-generate.
 257
 258 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 259
 260         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 261         * i386-tbl.h: Re-generate.
 262
 263 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 264
 265         PR gas/24546
 266         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 267         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 268         Amd64 and Intel64 templates.
 269         (call, jmp): Likewise for far indirect variants. Dro
 270         Unspecified.
 271         * i386-tbl.h: Re-generate.
 272
 273 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 274
 275         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 276         * i386-opc.h (ShortForm): Delete.
 277         (struct i386_opcode_modifier): Remove shortform field.
 278         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 279         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 280         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 281         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 282         Drop ShortForm.
 283         * i386-tbl.h: Re-generate.
 284
 285 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 286
 287         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 288         fucompi): Drop ShortForm from operand-less templates.
 289         * i386-tbl.h: Re-generate.
 290
 291 2020-02-11  Alan Modra  <amodra@gmail.com>
 292
 293         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 294         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 295         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 296         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 297         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 298
 299 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 300
 301         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 302         (cde_opcodes): Add VCX* instructions.
 303
 304 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 305             Matthew Malcomson  <matthew.malcomson@arm.com>
 306
 307         * arm-dis.c (struct cdeopcode32): New.
 308         (CDE_OPCODE): New macro.
 309         (cde_opcodes): New disassembly table.
 310         (regnames): New option to table.
 311         (cde_coprocs): New global variable.
 312         (print_insn_cde): New
 313         (print_insn_thumb32): Use print_insn_cde.
 314         (parse_arm_disassembler_options): Parse coprocN args.
 315
 316 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 317
 318         PR gas/25516
 319         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 320         with ISA64.
 321         * i386-opc.h (AMD64): Removed.
 322         (Intel64): Likewose.
 323         (AMD64): New.
 324         (INTEL64): Likewise.
 325         (INTEL64ONLY): Likewise.
 326         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 327         * i386-opc.tbl (Amd64): New.
 328         (Intel64): Likewise.
 329         (Intel64Only): Likewise.
 330         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 331         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 332         * i386-tbl.h: Regenerated.
 333
 334 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 335
 336         PR 25469
 337         * z80-dis.c: Add support for GBZ80 opcodes.
 338
 339 2020-02-04  Alan Modra  <amodra@gmail.com>
 340
 341         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 342
 343 2020-02-03  Alan Modra  <amodra@gmail.com>
 344
 345         * m32c-ibld.c: Regenerate.
 346
 347 2020-02-01  Alan Modra  <amodra@gmail.com>
 348
 349         * frv-ibld.c: Regenerate.
 350
 351 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 352
 353         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 354         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 355         (OP_E_memory): Replace xmm_mdq_mode case label by
 356         vex_scalar_w_dq_mode one.
 357         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 358
 359 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 360
 361         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 362         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 363         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 364         (intel_operand_size): Drop vex_w_dq_mode case label.
 365
 366 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 367
 368         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 369         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 370
 371 2020-01-30  Alan Modra  <amodra@gmail.com>
 372
 373         * m32c-ibld.c: Regenerate.
 374
 375 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 376
 377         * bpf-opc.c: Regenerate.
 378
 379 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 380
 381         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 382         (dis386): Use them to replace C2/C3 table entries.
 383         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 384         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 385         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 386         * i386-tbl.h: Re-generate.
 387
 388 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 389
 390         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 391         forms.
 392         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 393         DefaultSize.
 394         * i386-tbl.h: Re-generate.
 395
 396 2020-01-30  Alan Modra  <amodra@gmail.com>
 397
 398         * tic4x-dis.c (tic4x_dp): Make unsigned.
 399
 400 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 401             Jan Beulich  <jbeulich@suse.com>
 402
 403         PR binutils/25445
 404         * i386-dis.c (MOVSXD_Fixup): New function.
 405         (movsxd_mode): New enum.
 406         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 407         (intel_operand_size): Handle movsxd_mode.
 408         (OP_E_register): Likewise.
 409         (OP_G): Likewise.
 410         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 411         register on movsxd.  Add movsxd with 16-bit destination register
 412         for AMD64 and Intel64 ISAs.
 413         * i386-tbl.h: Regenerated.
 414
 415 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 416
 417         PR 25403
 418         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 419         * aarch64-asm-2.c: Regenerate
 420         * aarch64-dis-2.c: Likewise.
 421         * aarch64-opc-2.c: Likewise.
 422
 423 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 424
 425         * i386-opc.tbl (sysret): Drop DefaultSize.
 426         * i386-tbl.h: Re-generate.
 427
 428 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 429
 430         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 431         Dword.
 432         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 433         * i386-tbl.h: Re-generate.
 434
 435 2020-01-20  Nick Clifton  <nickc@redhat.com>
 436
 437         * po/de.po: Updated German translation.
 438         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 439         * po/uk.po: Updated Ukranian translation.
 440
 441 2020-01-20  Alan Modra  <amodra@gmail.com>
 442
 443         * hppa-dis.c (fput_const): Remove useless cast.
 444
 445 2020-01-20  Alan Modra  <amodra@gmail.com>
 446
 447         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 448
 449 2020-01-18  Nick Clifton  <nickc@redhat.com>
 450
 451         * configure: Regenerate.
 452         * po/opcodes.pot: Regenerate.
 453
 454 2020-01-18  Nick Clifton  <nickc@redhat.com>
 455
 456         Binutils 2.34 branch created.
 457
 458 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 459
 460         * opintl.h: Fix spelling error (seperate).
 461
 462 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 463
 464         * i386-opc.tbl: Add {vex} pseudo prefix.
 465         * i386-tbl.h: Regenerated.
 466
 467 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 468
 469         PR 25376
 470         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 471         (neon_opcodes): Likewise.
 472         (select_arm_features): Make sure we enable MVE bits when selecting
 473         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 474         any architecture.
 475
 476 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 477
 478         * i386-opc.tbl: Drop stale comment from XOP section.
 479
 480 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 481
 482         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 483         (extractps): Add VexWIG to SSE2AVX forms.
 484         * i386-tbl.h: Re-generate.
 485
 486 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 487
 488         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 489         Size64 from and use VexW1 on SSE2AVX forms.
 490         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 491         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 492         * i386-tbl.h: Re-generate.
 493
 494 2020-01-15  Alan Modra  <amodra@gmail.com>
 495
 496         * tic4x-dis.c (tic4x_version): Make unsigned long.
 497         (optab, optab_special, registernames): New file scope vars.
 498         (tic4x_print_register): Set up registernames rather than
 499         malloc'd registertable.
 500         (tic4x_disassemble): Delete optable and optable_special.  Use
 501         optab and optab_special instead.  Throw away old optab,
 502         optab_special and registernames when info->mach changes.
 503
 504 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 505
 506         PR 25377
 507         * z80-dis.c (suffix): Use .db instruction to generate double
 508         prefix.
 509
 510 2020-01-14  Alan Modra  <amodra@gmail.com>
 511
 512         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 513         values to unsigned before shifting.
 514
 515 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 516
 517         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 518         flow instructions.
 519         (print_insn_thumb16, print_insn_thumb32): Likewise.
 520         (print_insn): Initialize the insn info.
 521         * i386-dis.c (print_insn): Initialize the insn info fields, and
 522         detect jumps.
 523
 524 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 525
 526         * arc-opc.c (C_NE): Make it required.
 527
 528 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 529
 530         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 531         reserved register name.
 532
 533 2020-01-13  Alan Modra  <amodra@gmail.com>
 534
 535         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 536         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 537
 538 2020-01-13  Alan Modra  <amodra@gmail.com>
 539
 540         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 541         result of wasm_read_leb128 in a uint64_t and check that bits
 542         are not lost when copying to other locals.  Use uint32_t for
 543         most locals.  Use PRId64 when printing int64_t.
 544
 545 2020-01-13  Alan Modra  <amodra@gmail.com>
 546
 547         * score-dis.c: Formatting.
 548         * score7-dis.c: Formatting.
 549
 550 2020-01-13  Alan Modra  <amodra@gmail.com>
 551
 552         * score-dis.c (print_insn_score48): Use unsigned variables for
 553         unsigned values.  Don't left shift negative values.
 554         (print_insn_score32): Likewise.
 555         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 556
 557 2020-01-13  Alan Modra  <amodra@gmail.com>
 558
 559         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 560
 561 2020-01-13  Alan Modra  <amodra@gmail.com>
 562
 563         * fr30-ibld.c: Regenerate.
 564
 565 2020-01-13  Alan Modra  <amodra@gmail.com>
 566
 567         * xgate-dis.c (print_insn): Don't left shift signed value.
 568         (ripBits): Formatting, use 1u.
 569
 570 2020-01-10  Alan Modra  <amodra@gmail.com>
 571
 572         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 573         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 574
 575 2020-01-10  Alan Modra  <amodra@gmail.com>
 576
 577         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 578         and XRREG value earlier to avoid a shift with negative exponent.
 579         * m10200-dis.c (disassemble): Similarly.
 580
 581 2020-01-09  Nick Clifton  <nickc@redhat.com>
 582
 583         PR 25224
 584         * z80-dis.c (ld_ii_ii): Use correct cast.
 585
 586 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 587
 588         PR 25224
 589         * z80-dis.c (ld_ii_ii): Use character constant when checking
 590         opcode byte value.
 591
 592 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 593
 594         * i386-dis.c (SEP_Fixup): New.
 595         (SEP): Define.
 596         (dis386_twobyte): Use it for sysenter/sysexit.
 597         (enum x86_64_isa): Change amd64 enumerator to value 1.
 598         (OP_J): Compare isa64 against intel64 instead of amd64.
 599         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 600         forms.
 601         * i386-tbl.h: Re-generate.
 602
 603 2020-01-08  Alan Modra  <amodra@gmail.com>
 604
 605         * z8k-dis.c: Include libiberty.h
 606         (instr_data_s): Make max_fetched unsigned.
 607         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 608         Don't exceed byte_info bounds.
 609         (output_instr): Make num_bytes unsigned.
 610         (unpack_instr): Likewise for nibl_count and loop.
 611         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 612         idx unsigned.
 613         * z8k-opc.h: Regenerate.
 614
 615 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 616
 617         * arc-tbl.h (llock): Use 'LLOCK' as class.
 618         (llockd): Likewise.
 619         (scond): Use 'SCOND' as class.
 620         (scondd): Likewise.
 621         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 622         (scondd): Likewise.
 623
 624 2020-01-06  Alan Modra  <amodra@gmail.com>
 625
 626         * m32c-ibld.c: Regenerate.
 627
 628 2020-01-06  Alan Modra  <amodra@gmail.com>
 629
 630         PR 25344
 631         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 632         Peek at next byte to prevent recursion on repeated prefix bytes.
 633         Ensure uninitialised "mybuf" is not accessed.
 634         (print_insn_z80): Don't zero n_fetch and n_used here,..
 635         (print_insn_z80_buf): ..do it here instead.
 636
 637 2020-01-04  Alan Modra  <amodra@gmail.com>
 638
 639         * m32r-ibld.c: Regenerate.
 640
 641 2020-01-04  Alan Modra  <amodra@gmail.com>
 642
 643         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 644
 645 2020-01-04  Alan Modra  <amodra@gmail.com>
 646
 647         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 648
 649 2020-01-04  Alan Modra  <amodra@gmail.com>
 650
 651         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 652
 653 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 654
 655         * aarch64-tbl.h (aarch64_opcode_table): Use
 656         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 657
 658 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 659
 660         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 661         forms of SUDOT and USDOT.
 662
 663 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 664
 665         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 666         uzip{1,2}.
 667         * opcodes/aarch64-dis-2.c: Re-generate.
 668
 669 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 670
 671         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 672         FMMLA encoding.
 673         * opcodes/aarch64-dis-2.c: Re-generate.
 674
 675 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 676
 677         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 678
 679 2020-01-01  Alan Modra  <amodra@gmail.com>
 680
 681         Update year range in copyright notice of all files.
 682
 683 For older changes see ChangeLog-2019
 684 \f
 685 Copyright (C) 2020 Free Software Foundation, Inc.
 686
 687 Copying and distribution of this file, with or without modification,
 688 are permitted in any medium without royalty provided the copyright
 689 notice and this notice are preserved.
 690
 691 Local Variables:
 692 mode: change-log
 693 left-margin: 8
 694 fill-column: 74
 695 version-control: never
 696 End: