opcodes/ChangeLog

   1 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
   2
   3         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
   4
   5 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
   6
   7         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
   8         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
   9         xor3>: Delete mnemonics.
  10         <cp_abort>: Rename mnemonic from ...
  11         <cpabort>: ...to this.
  12         <setb>: Change to a X form instruction.
  13         <sync>: Change to 1 operand form.
  14         <copy>: Delete mnemonic.
  15         <copy_first>: Rename mnemonic from ...
  16         <copy>: ...to this.
  17         <paste, paste.>: Delete mnemonics.
  18         <paste_last>: Rename mnemonic from ...
  19         <paste.>: ...to this.
  20
  21 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
  22
  23         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
  24
  25 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
  26
  27         * s390-mkopc.c (main): Support alternate arch strings.
  28
  29 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
  30
  31         * s390-opc.txt: Fix kmctr instruction type.
  32
  33 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
  34
  35         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
  36         * i386-init.h: Regenerated.
  37
  38 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
  39
  40         * opcodes/arc-dis.c (print_insn_arc): Changed.
  41
  42 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
  43
  44         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
  45         camellia_fl.
  46
  47 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
  48
  49         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
  50         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
  51         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
  52
  53 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
  54
  55         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
  56         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
  57         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
  58         PREFIX_MOD_3_0FAE_REG_4.
  59         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
  60         PREFIX_MOD_3_0FAE_REG_4.
  61         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
  62         (cpu_flags): Add CpuPTWRITE.
  63         * i386-opc.h (CpuPTWRITE): New.
  64         (i386_cpu_flags): Add cpuptwrite.
  65         * i386-opc.tbl: Add ptwrite instruction.
  66         * i386-init.h: Regenerated.
  67         * i386-tbl.h: Likewise.
  68
  69 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
  70
  71         * arc-dis.h: Wrap around in extern "C".
  72
  73 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
  74
  75         * aarch64-tbl.h (V8_2_INSN): New macro.
  76         (aarch64_opcode_table): Use it.
  77
  78 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
  79
  80         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
  81         CORE_INSN, __FP_INSN and SIMD_INSN.
  82
  83 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
  84
  85         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
  86         (aarch64_opcode_table): Update uses accordingly.
  87
  88 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
  89         Kwok Cheung Yeung  <kcy@codesourcery.com>
  90
  91         opcodes/
  92         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
  93         'e_cmplwi' to 'e_cmpli' instead.
  94         (OPVUPRT, OPVUPRT_MASK): Define.
  95         (powerpc_opcodes): Add E200Z4 insns.
  96         (vle_opcodes): Add context save/restore insns.
  97
  98 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
  99
 100         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
 101         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
 102         "j".
 103
 104 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 105
 106         * arc-nps400-tbl.h: Change block comments to GNU format.
 107         * arc-dis.c: Add new globals addrtypenames,
 108         addrtypenames_max, and addtypeunknown.
 109         (get_addrtype): New function.
 110         (print_insn_arc): Print colons and address types when
 111         required.
 112         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
 113         define insert and extract functions for all address types.
 114         (arc_operands): Add operands for colon and all address
 115         types.
 116         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
 117         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
 118         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
 119         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
 120         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
 121         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
 122
 123 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
 124
 125         * configure: Regenerated.
 126
 127 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
 128
 129         * arc-dis.c (skipclass): New structure.
 130         (decodelist): New variable.
 131         (is_compatible_p): New function.
 132         (new_element): Likewise.
 133         (skip_class_p): Likewise.
 134         (find_format_from_table): Use skip_class_p function.
 135         (find_format): Decode first the extension instructions.
 136         (print_insn_arc): Select either ARCEM or ARCHS based on elf
 137         e_flags.
 138         (parse_option): New function.
 139         (parse_disassembler_options): Likewise.
 140         (print_arc_disassembler_options): Likewise.
 141         (print_insn_arc): Use parse_disassembler_options function.  Proper
 142         select ARCv2 cpu variant.
 143         * disassemble.c (disassembler_usage): Add ARC disassembler
 144         options.
 145
 146 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
 147
 148         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
 149         annotation from the "nal" entry and reorder it beyond "bltzal".
 150
 151 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
 152
 153         * sparc-opc.c (ldtxa): New macro.
 154         (sparc_opcodes): Use the macro defined above to add entries for
 155         the LDTXA instructions.
 156         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
 157         instruction.
 158
 159 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
 160
 161         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
 162         and "jmpc".
 163
 164 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 165
 166         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
 167         (movzb): Adjust to cover all permitted suffixes.
 168         (movzw): New.
 169         * i386-tbl.h: Re-generate.
 170
 171 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 172
 173         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
 174         (lgdt): Remove Tbyte from non-64-bit variant.
 175         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
 176         xsaves64, xsavec64): Remove Disp16.
 177         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
 178         Remove Disp32S from non-64-bit variants. Remove Disp16 from
 179         64-bit variants.
 180         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
 181         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
 182         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
 183         64-bit variants.
 184         * i386-tbl.h: Re-generate.
 185
 186 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 187
 188         * i386-opc.tbl (xlat): Remove RepPrefixOk.
 189         * i386-tbl.h: Re-generate.
 190
 191 2016-06-30  Yao Qi  <yao.qi@linaro.org>
 192
 193         * arm-dis.c (print_insn): Fix typo in comment.
 194
 195 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
 196
 197         * aarch64-opc.c (operand_general_constraint_met_p): Check the
 198         range of ldst_elemlist operands.
 199         (print_register_list): Use PRIi64 to print the index.
 200         (aarch64_print_operand): Likewise.
 201
 202 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 203
 204         * mcore-opc.h: Remove sentinal.
 205         * mcore-dis.c (print_insn_mcore): Adjust.
 206
 207 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
 208
 209         * arc-opc.c: Correct description of availability of NPS400
 210         features.
 211
 212 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
 213
 214         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
 215         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
 216         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
 217         xor3>: New mnemonics.
 218         <setb>: Change to a VX form instruction.
 219         (insert_sh6): Add support for rldixor.
 220         (extract_sh6): Likewise.
 221
 222 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 223
 224         * arc-ext.h: Wrap in extern C.
 225
 226 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
 227
 228         * arc-dis.c (arc_insn_length): Add comment on instruction length.
 229         Use same method for determining instruction length on ARC700 and
 230         NPS-400.
 231         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
 232         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
 233         with the NPS400 subclass.
 234         * arc-opc.c: Likewise.
 235
 236 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 237
 238         * sparc-opc.c (rdasr): New macro.
 239         (wrasr): Likewise.
 240         (rdpr): Likewise.
 241         (wrpr): Likewise.
 242         (rdhpr): Likewise.
 243         (wrhpr): Likewise.
 244         (sparc_opcodes): Use the macros above to fix and expand the
 245         definition of read/write instructions from/to
 246         asr/privileged/hyperprivileged instructions.
 247         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
 248         %hva_mask_nz.  Prefer softint_set and softint_clear over
 249         set_softint and clear_softint.
 250         (print_insn_sparc): Support %ver in Rd.
 251
 252 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 253
 254         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
 255         architecture according to the hardware capabilities they require.
 256
 257 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 258
 259         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
 260         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
 261         bfd_mach_sparc_v9{c,d,e,v,m}.
 262         * sparc-opc.c (MASK_V9C): Define.
 263         (MASK_V9D): Likewise.
 264         (MASK_V9E): Likewise.
 265         (MASK_V9V): Likewise.
 266         (MASK_V9M): Likewise.
 267         (v6): Add MASK_V9{C,D,E,V,M}.
 268         (v6notlet): Likewise.
 269         (v7): Likewise.
 270         (v8): Likewise.
 271         (v9): Likewise.
 272         (v9andleon): Likewise.
 273         (v9a): Likewise.
 274         (v9b): Likewise.
 275         (v9c): Define.
 276         (v9d): Likewise.
 277         (v9e): Likewise.
 278         (v9v): Likewise.
 279         (v9m): Likewise.
 280         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
 281
 282 2016-06-15  Nick Clifton  <nickc@redhat.com>
 283
 284         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
 285         constants to match expected behaviour.
 286         (nds32_parse_opcode): Likewise.  Also for whitespace.
 287
 288 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
 289
 290         * arc-opc.c (extract_rhv1): Extract value from insn.
 291
 292 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 293
 294         * arc-nps400-tbl.h: Add ldbit instruction.
 295         * arc-opc.c: Add flag classes required for ldbit.
 296
 297 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 298
 299         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
 300         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 301         support the above instructions.
 302
 303 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 304
 305         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
 306         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
 307         csma, cbba, zncv, and hofs.
 308         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 309         support the above instructions.
 310
 311 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 312
 313         * arc-nps400-tbl.h: Add andab and orab instructions.
 314
 315 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 316
 317         * arc-nps400-tbl.h: Add addl-like instructions.
 318
 319 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 320
 321         * arc-nps400-tbl.h: Add mxb and imxb instructions.
 322
 323 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 324
 325         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
 326         instructions.
 327
 328 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 329
 330         * s390-dis.c (option_use_insn_len_bits_p): New file scope
 331         variable.
 332         (init_disasm): Handle new command line option "insnlength".
 333         (print_s390_disassembler_options): Mention new option in help
 334         output.
 335         (print_insn_s390): Use the encoded insn length when dumping
 336         unknown instructions.
 337
 338 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 339
 340         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
 341          to the address and set as symbol address for LDS/ STS immediate operands.
 342
 343 2016-06-07  Alan Modra  <amodra@gmail.com>
 344
 345         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
 346         cpu for "vle" to e500.
 347         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
 348         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
 349         (PPCNONE): Delete, substitute throughout.
 350         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
 351         except for major opcode 4 and 31.
 352         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
 353
 354 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
 355
 356         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
 357         ARM_EXT_RAS in relevant entries.
 358
 359 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
 360
 361         PR binutils/20196
 362         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
 363         opcodes for E6500.
 364
 365 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
 366
 367         PR binutis/18386
 368         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
 369         (indir_v_mode): New.
 370         Add comments for '&'.
 371         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
 372         (putop): Handle '&'.
 373         (intel_operand_size): Handle indir_v_mode.
 374         (OP_E_register): Likewise.
 375         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
 376         64-bit indirect call/jmp for AMD64.
 377         * i386-tbl.h: Regenerated
 378
 379 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 380
 381         * arc-dis.c (struct arc_operand_iterator): New structure.
 382         (find_format_from_table): All the old content from find_format,
 383         with some minor adjustments, and parameter renaming.
 384         (find_format_long_instructions): New function.
 385         (find_format): Rewritten.
 386         (arc_insn_length): Add LSB parameter.
 387         (extract_operand_value): New function.
 388         (operand_iterator_next): New function.
 389         (print_insn_arc): Use new functions to find opcode, and iterator
 390         over operands.
 391         * arc-opc.c (insert_nps_3bit_dst_short): New function.
 392         (extract_nps_3bit_dst_short): New function.
 393         (insert_nps_3bit_src2_short): New function.
 394         (extract_nps_3bit_src2_short): New function.
 395         (insert_nps_bitop1_size): New function.
 396         (extract_nps_bitop1_size): New function.
 397         (insert_nps_bitop2_size): New function.
 398         (extract_nps_bitop2_size): New function.
 399         (insert_nps_bitop_mod4_msb): New function.
 400         (extract_nps_bitop_mod4_msb): New function.
 401         (insert_nps_bitop_mod4_lsb): New function.
 402         (extract_nps_bitop_mod4_lsb): New function.
 403         (insert_nps_bitop_dst_pos3_pos4): New function.
 404         (extract_nps_bitop_dst_pos3_pos4): New function.
 405         (insert_nps_bitop_ins_ext): New function.
 406         (extract_nps_bitop_ins_ext): New function.
 407         (arc_operands): Add new operands.
 408         (arc_long_opcodes): New global array.
 409         (arc_num_long_opcodes): New global.
 410         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
 411
 412 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 413
 414         * nds32-asm.h: Add extern "C".
 415         * sh-opc.h: Likewise.
 416
 417 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
 418
 419         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
 420         0,b,limm to the rflt instruction.
 421
 422 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 423
 424         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
 425         constant.
 426
 427 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
 428
 429         PR gas/20145
 430         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
 431         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
 432         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
 433         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
 434         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
 435         * i386-init.h: Regenerated.
 436
 437 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 438
 439         PR gas/20145
 440         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
 441         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
 442         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
 443         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
 444         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
 445         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
 446         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
 447         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
 448         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
 449         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
 450         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
 451         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
 452         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
 453         CpuRegMask for AVX512.
 454         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
 455         and CpuRegMask.
 456         (set_bitfield_from_cpu_flag_init): New function.
 457         (set_bitfield): Remove const on f.  Call
 458         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
 459         * i386-opc.h (CpuRegMMX): New.
 460         (CpuRegXMM): Likewise.
 461         (CpuRegYMM): Likewise.
 462         (CpuRegZMM): Likewise.
 463         (CpuRegMask): Likewise.
 464         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
 465         and cpuregmask.
 466         * i386-init.h: Regenerated.
 467         * i386-tbl.h: Likewise.
 468
 469 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 470
 471         PR gas/20154
 472         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
 473         (opcode_modifiers): Add AMD64 and Intel64.
 474         (main): Properly verify CpuMax.
 475         * i386-opc.h (CpuAMD64): Removed.
 476         (CpuIntel64): Likewise.
 477         (CpuMax): Set to CpuNo64.
 478         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
 479         (AMD64): New.
 480         (Intel64): Likewise.
 481         (i386_opcode_modifier): Add amd64 and intel64.
 482         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
 483         on call and jmp.
 484         * i386-init.h: Regenerated.
 485         * i386-tbl.h: Likewise.
 486
 487 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 488
 489         PR gas/20154
 490         * i386-gen.c (main): Fail if CpuMax is incorrect.
 491         * i386-opc.h (CpuMax): Set to CpuIntel64.
 492         * i386-tbl.h: Regenerated.
 493
 494 2016-05-27  Nick Clifton  <nickc@redhat.com>
 495
 496         PR target/20150
 497         * msp430-dis.c (msp430dis_read_two_bytes): New function.
 498         (msp430dis_opcode_unsigned): New function.
 499         (msp430dis_opcode_signed): New function.
 500         (msp430_singleoperand): Use the new opcode reading functions.
 501         Only disassenmble bytes if they were successfully read.
 502         (msp430_doubleoperand): Likewise.
 503         (msp430_branchinstr): Likewise.
 504         (msp430x_callx_instr): Likewise.
 505         (print_insn_msp430): Check that it is safe to read bytes before
 506         attempting disassembly.  Use the new opcode reading functions.
 507
 508 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
 509
 510         * ppc-opc.c (CY): New define.  Document it.
 511         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
 512
 513 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 514
 515         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
 516         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
 517         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
 518         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
 519         CPU_ANY_AVX_FLAGS.
 520         * i386-init.h: Regenerated.
 521
 522 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 523
 524         PR gas/20141
 525         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
 526         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 527         * i386-init.h: Regenerated.
 528
 529 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 530
 531         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
 532         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
 533         * i386-init.h: Regenerated.
 534
 535 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 536
 537         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
 538         information.
 539         (print_insn_arc): Set insn_type information.
 540         * arc-opc.c (C_CC): Add F_CLASS_COND.
 541         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
 542         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
 543         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
 544         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
 545         (brne, brne_s, jeq_s, jne_s): Likewise.
 546
 547 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 548
 549         * arc-tbl.h (neg): New instruction variant.
 550
 551 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
 552
 553         * arc-dis.c (find_format, find_format, get_auxreg)
 554         (print_insn_arc): Changed.
 555         * arc-ext.h (INSERT_XOP): Likewise.
 556
 557 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 558
 559         * tic54x-dis.c (sprint_mmr): Adjust.
 560         * tic54x-opc.c: Likewise.
 561
 562 2016-05-19  Alan Modra  <amodra@gmail.com>
 563
 564         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
 565
 566 2016-05-19  Alan Modra  <amodra@gmail.com>
 567
 568         * ppc-opc.c: Formatting.
 569         (NSISIGNOPT): Define.
 570         (powerpc_opcodes <subis>): Use NSISIGNOPT.
 571
 572 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
 573
 574         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
 575         replacing references to `micromips_ase' throughout.
 576         (_print_insn_mips): Don't use file-level microMIPS annotation to
 577         determine the disassembly mode with the symbol table.
 578
 579 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
 580
 581         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
 582
 583 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
 584
 585         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
 586         mips64r6.
 587         * mips-opc.c (D34): New macro.
 588         (mips_builtin_opcodes): Define bposge32c for DSPr3.
 589
 590 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
 591
 592         * i386-dis.c (prefix_table): Add RDPID instruction.
 593         * i386-gen.c (cpu_flag_init): Add RDPID flag.
 594         (cpu_flags): Add RDPID bitfield.
 595         * i386-opc.h (enum): Add RDPID element.
 596         (i386_cpu_flags): Add RDPID field.
 597         * i386-opc.tbl: Add RDPID instruction.
 598         * i386-init.h: Regenerate.
 599         * i386-tbl.h: Regenerate.
 600
 601 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 602
 603         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
 604         branch type of a symbol.
 605         (print_insn): Likewise.
 606
 607 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 608
 609         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
 610         Mainline Security Extensions instructions.
 611         (thumb_opcodes): Add entries for narrow ARMv8-M Security
 612         Extensions instructions.
 613         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
 614         instructions.
 615         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
 616         special registers.
 617
 618 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
 619
 620         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
 621
 622 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
 623
 624         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
 625         (arcExtMap_genOpcode): Likewise.
 626         * arc-opc.c (arg_32bit_rc): Define new variable.
 627         (arg_32bit_u6): Likewise.
 628         (arg_32bit_limm): Likewise.
 629
 630 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 631
 632         * aarch64-gen.c (VERIFIER): Define.
 633         * aarch64-opc.c (VERIFIER): Define.
 634         (verify_ldpsw): Use static linkage.
 635         * aarch64-opc.h (verify_ldpsw): Remove.
 636         * aarch64-tbl.h: Use VERIFIER for verifiers.
 637
 638 2016-04-28  Nick Clifton  <nickc@redhat.com>
 639
 640         PR target/19722
 641         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
 642         * aarch64-opc.c (verify_ldpsw): New function.
 643         * aarch64-opc.h (verify_ldpsw): New prototype.
 644         * aarch64-tbl.h: Add initialiser for verifier field.
 645         (LDPSW): Set verifier to verify_ldpsw.
 646
 647 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
 648
 649         PR binutils/19983
 650         PR binutils/19984
 651         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
 652         smaller than address size.
 653
 654 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 655
 656         * alpha-dis.c: Regenerate.
 657         * crx-dis.c: Likewise.
 658         * disassemble.c: Likewise.
 659         * epiphany-opc.c: Likewise.
 660         * fr30-opc.c: Likewise.
 661         * frv-opc.c: Likewise.
 662         * ip2k-opc.c: Likewise.
 663         * iq2000-opc.c: Likewise.
 664         * lm32-opc.c: Likewise.
 665         * lm32-opinst.c: Likewise.
 666         * m32c-opc.c: Likewise.
 667         * m32r-opc.c: Likewise.
 668         * m32r-opinst.c: Likewise.
 669         * mep-opc.c: Likewise.
 670         * mt-opc.c: Likewise.
 671         * or1k-opc.c: Likewise.
 672         * or1k-opinst.c: Likewise.
 673         * tic80-opc.c: Likewise.
 674         * xc16x-opc.c: Likewise.
 675         * xstormy16-opc.c: Likewise.
 676
 677 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 678
 679         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
 680         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
 681         calcsd, and calcxd instructions.
 682         * arc-opc.c (insert_nps_bitop_size): Delete.
 683         (extract_nps_bitop_size): Delete.
 684         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
 685         (extract_nps_qcmp_m3): Define.
 686         (extract_nps_qcmp_m2): Define.
 687         (extract_nps_qcmp_m1): Define.
 688         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
 689         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
 690         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
 691         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
 692         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
 693         NPS_QCMP_M3.
 694
 695 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 696
 697         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
 698
 699 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 700
 701         * Makefile.in: Regenerated with automake 1.11.6.
 702         * aclocal.m4: Likewise.
 703
 704 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 705
 706         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
 707         instructions.
 708         * arc-opc.c (insert_nps_cmem_uimm16): New function.
 709         (extract_nps_cmem_uimm16): New function.
 710         (arc_operands): Add NPS_XLDST_UIMM16 operand.
 711
 712 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 713
 714         * arc-dis.c (arc_insn_length): New function.
 715         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
 716         (find_format): Change insnLen parameter to unsigned.
 717
 718 2016-04-13  Nick Clifton  <nickc@redhat.com>
 719
 720         PR target/19937
 721         * v850-opc.c (v850_opcodes): Correct masks for long versions of
 722         the LD.B and LD.BU instructions.
 723
 724 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 725
 726         * arc-dis.c (find_format): Check for extension flags.
 727         (print_flags): New function.
 728         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
 729         .extAuxRegister.
 730         * arc-ext.c (arcExtMap_coreRegName): Use
 731         LAST_EXTENSION_CORE_REGISTER.
 732         (arcExtMap_coreReadWrite): Likewise.
 733         (dump_ARC_extmap): Update printing.
 734         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
 735         (arc_aux_regs): Add cpu field.
 736         * arc-regs.h: Add cpu field, lower case name aux registers.
 737
 738 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 739
 740         * arc-tbl.h: Add rtsc, sleep with no arguments.
 741
 742 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 743
 744         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
 745         Initialize.
 746         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
 747         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
 748         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
 749         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
 750         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
 751         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
 752         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
 753         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
 754         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
 755         (arc_opcode arc_opcodes): Null terminate the array.
 756         (arc_num_opcodes): Remove.
 757         * arc-ext.h (INSERT_XOP): Define.
 758         (extInstruction_t): Likewise.
 759         (arcExtMap_instName): Delete.
 760         (arcExtMap_insn): New function.
 761         (arcExtMap_genOpcode): Likewise.
 762         * arc-ext.c (ExtInstruction): Remove.
 763         (create_map): Zero initialize instruction fields.
 764         (arcExtMap_instName): Remove.
 765         (arcExtMap_insn): New function.
 766         (dump_ARC_extmap): More info while debuging.
 767         (arcExtMap_genOpcode): New function.
 768         * arc-dis.c (find_format): New function.
 769         (print_insn_arc): Use find_format.
 770         (arc_get_disassembler): Enable dump_ARC_extmap only when
 771         debugging.
 772
 773 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
 774
 775         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
 776         instruction bits out.
 777
 778 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 779
 780         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
 781         * arc-opc.c (arc_flag_operands): Add new flags.
 782         (arc_flag_classes): Add new classes.
 783
 784 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 785
 786         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
 787
 788 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
 789
 790         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
 791         encode1, rflt, crc16, and crc32 instructions.
 792         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
 793         (arc_flag_classes): Add C_NPS_R.
 794         (insert_nps_bitop_size_2b): New function.
 795         (extract_nps_bitop_size_2b): Likewise.
 796         (insert_nps_bitop_uimm8): Likewise.
 797         (extract_nps_bitop_uimm8): Likewise.
 798         (arc_operands): Add new operand entries.
 799
 800 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
 801
 802         * arc-regs.h: Add a new subclass field.  Add double assist
 803         accumulator register values.
 804         * arc-tbl.h: Use DPA subclass to mark the double assist
 805         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
 806         * arc-opc.c (RSP): Define instead of SP.
 807         (arc_aux_regs): Add the subclass field.
 808
 809 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
 810
 811         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
 812
 813 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
 814
 815         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
 816         NPS_R_SRC1.
 817
 818 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
 819
 820         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
 821         issues.  No functional changes.
 822
 823 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
 824
 825         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
 826         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
 827         (RTT): Remove duplicate.
 828         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
 829         (PCT_CONFIG*): Remove.
 830         (D1L, D1H, D2H, D2L): Define.
 831
 832 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 833
 834         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
 835
 836 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 837
 838         * arc-tbl.h (invld07): Remove.
 839         * arc-ext-tbl.h: New file.
 840         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
 841         * arc-opc.c (arc_opcodes): Add ext-tbl include.
 842
 843 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
 844
 845         Fix -Wstack-usage warnings.
 846         * aarch64-dis.c (print_operands): Substitute size.
 847         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
 848
 849 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
 850
 851         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
 852         to get a proper diagnostic when an invalid ASR register is used.
 853
 854 2016-03-22  Nick Clifton  <nickc@redhat.com>
 855
 856         * configure: Regenerate.
 857
 858 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 859
 860         * arc-nps400-tbl.h: New file.
 861         * arc-opc.c: Add top level comment.
 862         (insert_nps_3bit_dst): New function.
 863         (extract_nps_3bit_dst): New function.
 864         (insert_nps_3bit_src2): New function.
 865         (extract_nps_3bit_src2): New function.
 866         (insert_nps_bitop_size): New function.
 867         (extract_nps_bitop_size): New function.
 868         (arc_flag_operands): Add nps400 entries.
 869         (arc_flag_classes): Add nps400 entries.
 870         (arc_operands): Add nps400 entries.
 871         (arc_opcodes): Add nps400 include.
 872
 873 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 874
 875         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
 876         the new class enum values.
 877
 878 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 879
 880         * arc-dis.c (print_insn_arc): Handle nps400.
 881
 882 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 883
 884         * arc-opc.c (BASE): Delete.
 885
 886 2016-03-18  Nick Clifton  <nickc@redhat.com>
 887
 888         PR target/19721
 889         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
 890         of MOV insn that aliases an ORR insn.
 891
 892 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
 893
 894         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
 895
 896 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 897
 898         * mcore-opc.h: Add const qualifiers.
 899         * microblaze-opc.h (struct op_code_struct): Likewise.
 900         * sh-opc.h: Likewise.
 901         * tic4x-dis.c (tic4x_print_indirect): Likewise.
 902         (tic4x_print_op): Likewise.
 903
 904 2016-03-02  Alan Modra  <amodra@gmail.com>
 905
 906         * or1k-desc.h: Regenerate.
 907         * fr30-ibld.c: Regenerate.
 908         * rl78-decode.c: Regenerate.
 909
 910 2016-03-01  Nick Clifton  <nickc@redhat.com>
 911
 912         PR target/19747
 913         * rl78-dis.c (print_insn_rl78_common): Fix typo.
 914
 915 2016-02-24  Renlin Li  <renlin.li@arm.com>
 916
 917         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
 918         (print_insn_coprocessor): Support fp16 instructions.
 919
 920 2016-02-24  Renlin Li  <renlin.li@arm.com>
 921
 922         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
 923         vminnm, vrint(mpna).
 924
 925 2016-02-24  Renlin Li  <renlin.li@arm.com>
 926
 927         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
 928         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
 929
 930 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
 931
 932         * i386-dis.c (print_insn): Parenthesize expression to prevent
 933         truncated addresses.
 934         (OP_J): Likewise.
 935
 936 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
 937             Janek van Oirschot  <jvanoirs@synopsys.com>
 938
 939         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
 940         variable.
 941
 942 2016-02-04  Nick Clifton  <nickc@redhat.com>
 943
 944         PR target/19561
 945         * msp430-dis.c (print_insn_msp430): Add a special case for
 946         decoding an RRC instruction with the ZC bit set in the extension
 947         word.
 948
 949 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 950
 951         * cgen-ibld.in (insert_normal): Rework calculation of shift.
 952         * epiphany-ibld.c: Regenerate.
 953         * fr30-ibld.c: Regenerate.
 954         * frv-ibld.c: Regenerate.
 955         * ip2k-ibld.c: Regenerate.
 956         * iq2000-ibld.c: Regenerate.
 957         * lm32-ibld.c: Regenerate.
 958         * m32c-ibld.c: Regenerate.
 959         * m32r-ibld.c: Regenerate.
 960         * mep-ibld.c: Regenerate.
 961         * mt-ibld.c: Regenerate.
 962         * or1k-ibld.c: Regenerate.
 963         * xc16x-ibld.c: Regenerate.
 964         * xstormy16-ibld.c: Regenerate.
 965
 966 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 967
 968         * epiphany-dis.c: Regenerated from latest cpu files.
 969
 970 2016-02-01  Michael McConville  <mmcco@mykolab.com>
 971
 972         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
 973         test bit.
 974
 975 2016-01-25  Renlin Li  <renlin.li@arm.com>
 976
 977         * arm-dis.c (mapping_symbol_for_insn): New function.
 978         (find_ifthen_state): Call mapping_symbol_for_insn().
 979
 980 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
 981
 982         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
 983         of MSR UAO immediate operand.
 984
 985 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
 986
 987         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
 988         instruction support.
 989
 990 2016-01-17  Alan Modra  <amodra@gmail.com>
 991
 992         * configure: Regenerate.
 993
 994 2016-01-14  Nick Clifton  <nickc@redhat.com>
 995
 996         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
 997         instructions that can support stack pointer operations.
 998         * rl78-decode.c: Regenerate.
 999         * rl78-dis.c: Fix display of stack pointer in MOVW based
1000         instructions.
1001
1002 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1003
1004         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1005         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1006         erxtatus_el1 and erxaddr_el1.
1007
1008 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1009
1010         * arm-dis.c (arm_opcodes): Add "esb".
1011         (thumb_opcodes): Likewise.
1012
1013 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1014
1015         * ppc-opc.c <xscmpnedp>: Delete.
1016         <xvcmpnedp>: Likewise.
1017         <xvcmpnedp.>: Likewise.
1018         <xvcmpnesp>: Likewise.
1019         <xvcmpnesp.>: Likewise.
1020
1021 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1022
1023         PR gas/13050
1024         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1025         addition to ISA_A.
1026
1027 2016-01-01  Alan Modra  <amodra@gmail.com>
1028
1029         Update year range in copyright notice of all files.
1030
1031 For older changes see ChangeLog-2015
1032 \f
1033 Copyright (C) 2016 Free Software Foundation, Inc.
1034
1035 Copying and distribution of this file, with or without modification,
1036 are permitted in any medium without royalty provided the copyright
1037 notice and this notice are preserved.
1038
1039 Local Variables:
1040 mode: change-log
1041 left-margin: 8
1042 fill-column: 74
1043 version-control: never
1044 End: