opcodes/ChangeLog

   1 2020-05-11  Alan Modra  <amodra@gmail.com>
   2
   3         * ppc-opc.c (MP, VXVAM_MASK): Define.
   4         (VXVAPS_MASK): Use VXVA_MASK.
   5         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
   6         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
   7         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
   8         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
   9
  10 2020-05-11  Alan Modra  <amodra@gmail.com>
  11             Peter Bergner  <bergner@linux.ibm.com>
  12
  13         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
  14         New functions.
  15         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
  16         YMSK2, XA6a, XA6ap, XB6a entries.
  17         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
  18         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
  19         (PPCVSX4): Define.
  20         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
  21         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
  22         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
  23         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
  24         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
  25         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
  26         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
  27         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
  28         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
  29         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
  30         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
  31         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
  32         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
  33         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
  34
  35 2020-05-11  Alan Modra  <amodra@gmail.com>
  36
  37         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
  38         (insert_xts, extract_xts): New functions.
  39         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
  40         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
  41         (VXRC_MASK, VXSH_MASK): Define.
  42         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
  43         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
  44         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
  45         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
  46         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
  47         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
  48         xxblendvh, xxblendvw, xxblendvd, xxpermx.
  49
  50 2020-05-11  Alan Modra  <amodra@gmail.com>
  51
  52         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
  53         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
  54         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
  55         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
  56         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
  57
  58 2020-05-11  Alan Modra  <amodra@gmail.com>
  59
  60         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
  61         (XTP, DQXP, DQXP_MASK): Define.
  62         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
  63         (prefix_opcodes): Add plxvp and pstxvp.
  64
  65 2020-05-11  Alan Modra  <amodra@gmail.com>
  66
  67         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
  68         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
  69         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
  70
  71 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
  72
  73         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
  74
  75 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
  76
  77         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
  78         (L1OPT): Define.
  79         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
  80
  81 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
  82
  83         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
  84
  85 2020-05-11  Alan Modra  <amodra@gmail.com>
  86
  87         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
  88
  89 2020-05-11  Alan Modra  <amodra@gmail.com>
  90
  91         * ppc-dis.c (ppc_opts): Add "power10" entry.
  92         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
  93         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
  94
  95 2020-05-11  Nick Clifton  <nickc@redhat.com>
  96
  97         * po/fr.po: Updated French translation.
  98
  99 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
 100
 101         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
 102         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
 103         (operand_general_constraint_met_p): validate
 104         AARCH64_OPND_UNDEFINED.
 105         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
 106         for FLD_imm16_2.
 107         * aarch64-asm-2.c: Regenerated.
 108         * aarch64-dis-2.c: Regenerated.
 109         * aarch64-opc-2.c: Regenerated.
 110
 111 2020-04-29  Nick Clifton  <nickc@redhat.com>
 112
 113         PR 22699
 114         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
 115         and SETRC insns.
 116
 117 2020-04-29  Nick Clifton  <nickc@redhat.com>
 118
 119         * po/sv.po: Updated Swedish translation.
 120
 121 2020-04-29  Nick Clifton  <nickc@redhat.com>
 122
 123         PR 22699
 124         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
 125         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
 126         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
 127         IMM0_8U case.
 128
 129 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
 130
 131         PR 25848
 132         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
 133         cmpi only on m68020up and cpu32.
 134
 135 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 136
 137         * aarch64-asm.c (aarch64_ins_none): New.
 138         * aarch64-asm.h (ins_none): New declaration.
 139         * aarch64-dis.c (aarch64_ext_none): New.
 140         * aarch64-dis.h (ext_none): New declaration.
 141         * aarch64-opc.c (aarch64_print_operand): Update case for
 142         AARCH64_OPND_BARRIER_PSB.
 143         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
 144         (AARCH64_OPERANDS): Update inserter/extracter for
 145         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
 146         * aarch64-asm-2.c: Regenerated.
 147         * aarch64-dis-2.c: Regenerated.
 148         * aarch64-opc-2.c: Regenerated.
 149
 150 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 151
 152         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
 153         (aarch64_feature_ras, RAS): Likewise.
 154         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
 155         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
 156         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
 157         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
 158         * aarch64-asm-2.c: Regenerated.
 159         * aarch64-dis-2.c: Regenerated.
 160         * aarch64-opc-2.c: Regenerated.
 161
 162 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
 163
 164         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
 165         (print_insn_neon): Support disassembly of conditional
 166         instructions.
 167
 168 2020-02-16  David Faust  <david.faust@oracle.com>
 169
 170         * bpf-desc.c: Regenerate.
 171         * bpf-desc.h: Likewise.
 172         * bpf-opc.c: Regenerate.
 173         * bpf-opc.h: Likewise.
 174
 175 2020-04-07  Lili Cui  <lili.cui@intel.com>
 176
 177         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
 178         (prefix_table): New instructions (see prefixes above).
 179         (rm_table): Likewise
 180         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
 181         CPU_ANY_TSXLDTRK_FLAGS.
 182         (cpu_flags): Add CpuTSXLDTRK.
 183         * i386-opc.h (enum): Add CpuTSXLDTRK.
 184         (i386_cpu_flags): Add cputsxldtrk.
 185         * i386-opc.tbl: Add XSUSPLDTRK insns.
 186         * i386-init.h: Regenerate.
 187         * i386-tbl.h: Likewise.
 188
 189 2020-04-02  Lili Cui  <lili.cui@intel.com>
 190
 191         * i386-dis.c (prefix_table): New instructions serialize.
 192         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
 193         CPU_ANY_SERIALIZE_FLAGS.
 194         (cpu_flags): Add CpuSERIALIZE.
 195         * i386-opc.h (enum): Add CpuSERIALIZE.
 196         (i386_cpu_flags): Add cpuserialize.
 197         * i386-opc.tbl: Add SERIALIZE insns.
 198         * i386-init.h: Regenerate.
 199         * i386-tbl.h: Likewise.
 200
 201 2020-03-26  Alan Modra  <amodra@gmail.com>
 202
 203         * disassemble.h (opcodes_assert): Declare.
 204         (OPCODES_ASSERT): Define.
 205         * disassemble.c: Don't include assert.h.  Include opintl.h.
 206         (opcodes_assert): New function.
 207         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 208         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 209         calculate maxlen.  Omit insn decoding when insn length exceeds
 210         maxlen.  Exit from nibble loop when looking for E, before
 211         accessing next data byte.  Move processing of E outside loop.
 212         Replace tests of maxlen in loop with assertions.
 213
 214 2020-03-26  Alan Modra  <amodra@gmail.com>
 215
 216         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 217
 218 2020-03-25  Alan Modra  <amodra@gmail.com>
 219
 220         * z80-dis.c (suffix): Init mybuf.
 221
 222 2020-03-22  Alan Modra  <amodra@gmail.com>
 223
 224         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 225         successflly read from section.
 226
 227 2020-03-22  Alan Modra  <amodra@gmail.com>
 228
 229         * arc-dis.c (find_format): Use ISO C string concatenation rather
 230         than line continuation within a string.  Don't access needs_limm
 231         before testing opcode != NULL.
 232
 233 2020-03-22  Alan Modra  <amodra@gmail.com>
 234
 235         * ns32k-dis.c (print_insn_arg): Update comment.
 236         (print_insn_ns32k): Reduce size of index_offset array, and
 237         initialize, passing -1 to print_insn_arg for args that are not
 238         an index.  Don't exit arg loop early.  Abort on bad arg number.
 239
 240 2020-03-22  Alan Modra  <amodra@gmail.com>
 241
 242         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 243         * s12z-opc.c: Formatting.
 244         (operands_f): Return an int.
 245         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 246         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 247         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 248         (exg_sex_discrim): Likewise.
 249         (create_immediate_operand, create_bitfield_operand),
 250         (create_register_operand_with_size, create_register_all_operand),
 251         (create_register_all16_operand, create_simple_memory_operand),
 252         (create_memory_operand, create_memory_auto_operand): Don't
 253         segfault on malloc failure.
 254         (z_ext24_decode): Return an int status, negative on fail, zero
 255         on success.
 256         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 257         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 258         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 259         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 260         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 261         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 262         (loop_primitive_decode, shift_decode, psh_pul_decode),
 263         (bit_field_decode): Similarly.
 264         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 265         to return value, update callers.
 266         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 267         Don't segfault on NULL operand.
 268         (decode_operation): Return OP_INVALID on first fail.
 269         (decode_s12z): Check all reads, returning -1 on fail.
 270
 271 2020-03-20  Alan Modra  <amodra@gmail.com>
 272
 273         * metag-dis.c (print_insn_metag): Don't ignore status from
 274         read_memory_func.
 275
 276 2020-03-20  Alan Modra  <amodra@gmail.com>
 277
 278         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 279         Initialize parts of buffer not written when handling a possible
 280         2-byte insn at end of section.  Don't attempt decoding of such
 281         an insn by the 4-byte machinery.
 282
 283 2020-03-20  Alan Modra  <amodra@gmail.com>
 284
 285         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 286         partially filled buffer.  Prevent lookup of 4-byte insns when
 287         only VLE 2-byte insns are possible due to section size.  Print
 288         ".word" rather than ".long" for 2-byte leftovers.
 289
 290 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 291
 292         PR 25641
 293         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 294
 295 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 296
 297         * i386-dis.c (X86_64_0D): Rename to ...
 298         (X86_64_0E): ... this.
 299
 300 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 301
 302         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 303         * Makefile.in: Regenerated.
 304
 305 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 306
 307         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 308         3-operand pseudos.
 309         * i386-tbl.h: Re-generate.
 310
 311 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 312
 313         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 314         vprot*, vpsha*, and vpshl*.
 315         * i386-tbl.h: Re-generate.
 316
 317 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 318
 319         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 320         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 321         * i386-tbl.h: Re-generate.
 322
 323 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 324
 325         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 326         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 327         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 328         * i386-tbl.h: Re-generate.
 329
 330 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 331
 332         * i386-gen.c (struct template_arg, struct template_instance,
 333         struct template_param, struct template, templates,
 334         parse_template, expand_templates): New.
 335         (process_i386_opcodes): Various local variables moved to
 336         expand_templates. Call parse_template and expand_templates.
 337         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 338         * i386-tbl.h: Re-generate.
 339
 340 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 341
 342         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 343         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 344         register and memory source templates. Replace VexW= by VexW*
 345         where applicable.
 346         * i386-tbl.h: Re-generate.
 347
 348 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 349
 350         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 351         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 352         * i386-tbl.h: Re-generate.
 353
 354 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 355
 356         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 357         * i386-tbl.h: Re-generate.
 358
 359 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 360
 361         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 362         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 363         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 364         VexW0 on SSE2AVX variants.
 365         (vmovq): Drop NoRex64 from XMM/XMM variants.
 366         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 367         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 368         applicable use VexW0.
 369         * i386-tbl.h: Re-generate.
 370
 371 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 372
 373         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 374         * i386-opc.h (Rex64): Delete.
 375         (struct i386_opcode_modifier): Remove rex64 field.
 376         * i386-opc.tbl (crc32): Drop Rex64.
 377         Replace Rex64 with Size64 everywhere else.
 378         * i386-tbl.h: Re-generate.
 379
 380 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 381
 382         * i386-dis.c (OP_E_memory): Exclude recording of used address
 383         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 384         addressed memory operands for MPX insns.
 385
 386 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 387
 388         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 389         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 390         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 391         (ptwrite): Split into non-64-bit and 64-bit forms.
 392         * i386-tbl.h: Re-generate.
 393
 394 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 395
 396         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 397         template.
 398         * i386-tbl.h: Re-generate.
 399
 400 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 401
 402         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 403         (prefix_table): Move vmmcall here. Add vmgexit.
 404         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 405         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 406         (cpu_flags): Add CpuSEV_ES entry.
 407         * i386-opc.h (CpuSEV_ES): New.
 408         (union i386_cpu_flags): Add cpusev_es field.
 409         * i386-opc.tbl (vmgexit): New.
 410         * i386-init.h, i386-tbl.h: Re-generate.
 411
 412 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 413
 414         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 415         with MnemonicSize.
 416         * i386-opc.h (IGNORESIZE): New.
 417         (DEFAULTSIZE): Likewise.
 418         (IgnoreSize): Removed.
 419         (DefaultSize): Likewise.
 420         (MnemonicSize): New.
 421         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 422         mnemonicsize.
 423         * i386-opc.tbl (IgnoreSize): New.
 424         (DefaultSize): Likewise.
 425         * i386-tbl.h: Regenerated.
 426
 427 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 428
 429         PR 25627
 430         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 431         instructions.
 432
 433 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 434
 435         PR gas/25622
 436         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 437         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 438         * i386-tbl.h: Regenerated.
 439
 440 2020-02-26  Alan Modra  <amodra@gmail.com>
 441
 442         * aarch64-asm.c: Indent labels correctly.
 443         * aarch64-dis.c: Likewise.
 444         * aarch64-gen.c: Likewise.
 445         * aarch64-opc.c: Likewise.
 446         * alpha-dis.c: Likewise.
 447         * i386-dis.c: Likewise.
 448         * nds32-asm.c: Likewise.
 449         * nfp-dis.c: Likewise.
 450         * visium-dis.c: Likewise.
 451
 452 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 453
 454         * arc-regs.h (int_vector_base): Make it available for all ARC
 455         CPUs.
 456
 457 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 458
 459         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 460         changed.
 461
 462 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 463
 464         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 465         c.mv/c.li if rs1 is zero.
 466
 467 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 468
 469         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 470         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 471         CPU_POPCNT_FLAGS.
 472         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 473         * i386-opc.h (CpuABM): Removed.
 474         (CpuPOPCNT): New.
 475         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 476         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 477         popcnt.  Remove CpuABM from lzcnt.
 478         * i386-init.h: Regenerated.
 479         * i386-tbl.h: Likewise.
 480
 481 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 482
 483         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 484         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 485         VexW1 instead of open-coding them.
 486         * i386-tbl.h: Re-generate.
 487
 488 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 489
 490         * i386-opc.tbl (AddrPrefixOpReg): Define.
 491         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 492         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 493         templates. Drop NoRex64.
 494         * i386-tbl.h: Re-generate.
 495
 496 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 497
 498         PR gas/6518
 499         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 500         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 501         into Intel syntax instance (with Unpsecified) and AT&T one
 502         (without).
 503         (vcvtneps2bf16): Likewise, along with folding the two so far
 504         separate ones.
 505         * i386-tbl.h: Re-generate.
 506
 507 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 508
 509         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 510         CPU_ANY_SSE4A_FLAGS.
 511
 512 2020-02-17  Alan Modra  <amodra@gmail.com>
 513
 514         * i386-gen.c (cpu_flag_init): Correct last change.
 515
 516 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 517
 518         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 519         CPU_ANY_SSE4_FLAGS.
 520
 521 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 522
 523         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 524         (movzx): Likewise.
 525
 526 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 527
 528         PR gas/25438
 529         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 530         destination for Cpu64-only variant.
 531         (movzx): Fold patterns.
 532         * i386-tbl.h: Re-generate.
 533
 534 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 535
 536         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 537         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 538         CPU_ANY_SSE4_FLAGS entry.
 539         * i386-init.h: Re-generate.
 540
 541 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 542
 543         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 544         with Unspecified, making the present one AT&T syntax only.
 545         * i386-tbl.h: Re-generate.
 546
 547 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 548
 549         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 550         * i386-tbl.h: Re-generate.
 551
 552 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 553
 554         PR gas/24546
 555         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 556         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 557         Amd64 and Intel64 templates.
 558         (call, jmp): Likewise for far indirect variants. Dro
 559         Unspecified.
 560         * i386-tbl.h: Re-generate.
 561
 562 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 563
 564         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 565         * i386-opc.h (ShortForm): Delete.
 566         (struct i386_opcode_modifier): Remove shortform field.
 567         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 568         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 569         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 570         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 571         Drop ShortForm.
 572         * i386-tbl.h: Re-generate.
 573
 574 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 575
 576         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 577         fucompi): Drop ShortForm from operand-less templates.
 578         * i386-tbl.h: Re-generate.
 579
 580 2020-02-11  Alan Modra  <amodra@gmail.com>
 581
 582         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 583         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 584         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 585         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 586         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 587
 588 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 589
 590         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 591         (cde_opcodes): Add VCX* instructions.
 592
 593 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 594             Matthew Malcomson  <matthew.malcomson@arm.com>
 595
 596         * arm-dis.c (struct cdeopcode32): New.
 597         (CDE_OPCODE): New macro.
 598         (cde_opcodes): New disassembly table.
 599         (regnames): New option to table.
 600         (cde_coprocs): New global variable.
 601         (print_insn_cde): New
 602         (print_insn_thumb32): Use print_insn_cde.
 603         (parse_arm_disassembler_options): Parse coprocN args.
 604
 605 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 606
 607         PR gas/25516
 608         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 609         with ISA64.
 610         * i386-opc.h (AMD64): Removed.
 611         (Intel64): Likewose.
 612         (AMD64): New.
 613         (INTEL64): Likewise.
 614         (INTEL64ONLY): Likewise.
 615         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 616         * i386-opc.tbl (Amd64): New.
 617         (Intel64): Likewise.
 618         (Intel64Only): Likewise.
 619         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 620         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 621         * i386-tbl.h: Regenerated.
 622
 623 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 624
 625         PR 25469
 626         * z80-dis.c: Add support for GBZ80 opcodes.
 627
 628 2020-02-04  Alan Modra  <amodra@gmail.com>
 629
 630         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 631
 632 2020-02-03  Alan Modra  <amodra@gmail.com>
 633
 634         * m32c-ibld.c: Regenerate.
 635
 636 2020-02-01  Alan Modra  <amodra@gmail.com>
 637
 638         * frv-ibld.c: Regenerate.
 639
 640 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 641
 642         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 643         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 644         (OP_E_memory): Replace xmm_mdq_mode case label by
 645         vex_scalar_w_dq_mode one.
 646         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 647
 648 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 649
 650         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 651         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 652         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 653         (intel_operand_size): Drop vex_w_dq_mode case label.
 654
 655 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 656
 657         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 658         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 659
 660 2020-01-30  Alan Modra  <amodra@gmail.com>
 661
 662         * m32c-ibld.c: Regenerate.
 663
 664 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 665
 666         * bpf-opc.c: Regenerate.
 667
 668 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 669
 670         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 671         (dis386): Use them to replace C2/C3 table entries.
 672         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 673         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 674         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 675         * i386-tbl.h: Re-generate.
 676
 677 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 678
 679         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 680         forms.
 681         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 682         DefaultSize.
 683         * i386-tbl.h: Re-generate.
 684
 685 2020-01-30  Alan Modra  <amodra@gmail.com>
 686
 687         * tic4x-dis.c (tic4x_dp): Make unsigned.
 688
 689 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 690             Jan Beulich  <jbeulich@suse.com>
 691
 692         PR binutils/25445
 693         * i386-dis.c (MOVSXD_Fixup): New function.
 694         (movsxd_mode): New enum.
 695         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 696         (intel_operand_size): Handle movsxd_mode.
 697         (OP_E_register): Likewise.
 698         (OP_G): Likewise.
 699         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 700         register on movsxd.  Add movsxd with 16-bit destination register
 701         for AMD64 and Intel64 ISAs.
 702         * i386-tbl.h: Regenerated.
 703
 704 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 705
 706         PR 25403
 707         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 708         * aarch64-asm-2.c: Regenerate
 709         * aarch64-dis-2.c: Likewise.
 710         * aarch64-opc-2.c: Likewise.
 711
 712 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 713
 714         * i386-opc.tbl (sysret): Drop DefaultSize.
 715         * i386-tbl.h: Re-generate.
 716
 717 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 718
 719         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 720         Dword.
 721         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 722         * i386-tbl.h: Re-generate.
 723
 724 2020-01-20  Nick Clifton  <nickc@redhat.com>
 725
 726         * po/de.po: Updated German translation.
 727         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 728         * po/uk.po: Updated Ukranian translation.
 729
 730 2020-01-20  Alan Modra  <amodra@gmail.com>
 731
 732         * hppa-dis.c (fput_const): Remove useless cast.
 733
 734 2020-01-20  Alan Modra  <amodra@gmail.com>
 735
 736         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 737
 738 2020-01-18  Nick Clifton  <nickc@redhat.com>
 739
 740         * configure: Regenerate.
 741         * po/opcodes.pot: Regenerate.
 742
 743 2020-01-18  Nick Clifton  <nickc@redhat.com>
 744
 745         Binutils 2.34 branch created.
 746
 747 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 748
 749         * opintl.h: Fix spelling error (seperate).
 750
 751 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 752
 753         * i386-opc.tbl: Add {vex} pseudo prefix.
 754         * i386-tbl.h: Regenerated.
 755
 756 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 757
 758         PR 25376
 759         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 760         (neon_opcodes): Likewise.
 761         (select_arm_features): Make sure we enable MVE bits when selecting
 762         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 763         any architecture.
 764
 765 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 766
 767         * i386-opc.tbl: Drop stale comment from XOP section.
 768
 769 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 770
 771         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 772         (extractps): Add VexWIG to SSE2AVX forms.
 773         * i386-tbl.h: Re-generate.
 774
 775 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 776
 777         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 778         Size64 from and use VexW1 on SSE2AVX forms.
 779         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 780         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 781         * i386-tbl.h: Re-generate.
 782
 783 2020-01-15  Alan Modra  <amodra@gmail.com>
 784
 785         * tic4x-dis.c (tic4x_version): Make unsigned long.
 786         (optab, optab_special, registernames): New file scope vars.
 787         (tic4x_print_register): Set up registernames rather than
 788         malloc'd registertable.
 789         (tic4x_disassemble): Delete optable and optable_special.  Use
 790         optab and optab_special instead.  Throw away old optab,
 791         optab_special and registernames when info->mach changes.
 792
 793 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 794
 795         PR 25377
 796         * z80-dis.c (suffix): Use .db instruction to generate double
 797         prefix.
 798
 799 2020-01-14  Alan Modra  <amodra@gmail.com>
 800
 801         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 802         values to unsigned before shifting.
 803
 804 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 805
 806         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 807         flow instructions.
 808         (print_insn_thumb16, print_insn_thumb32): Likewise.
 809         (print_insn): Initialize the insn info.
 810         * i386-dis.c (print_insn): Initialize the insn info fields, and
 811         detect jumps.
 812
 813 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 814
 815         * arc-opc.c (C_NE): Make it required.
 816
 817 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 818
 819         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 820         reserved register name.
 821
 822 2020-01-13  Alan Modra  <amodra@gmail.com>
 823
 824         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 825         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 826
 827 2020-01-13  Alan Modra  <amodra@gmail.com>
 828
 829         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 830         result of wasm_read_leb128 in a uint64_t and check that bits
 831         are not lost when copying to other locals.  Use uint32_t for
 832         most locals.  Use PRId64 when printing int64_t.
 833
 834 2020-01-13  Alan Modra  <amodra@gmail.com>
 835
 836         * score-dis.c: Formatting.
 837         * score7-dis.c: Formatting.
 838
 839 2020-01-13  Alan Modra  <amodra@gmail.com>
 840
 841         * score-dis.c (print_insn_score48): Use unsigned variables for
 842         unsigned values.  Don't left shift negative values.
 843         (print_insn_score32): Likewise.
 844         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 845
 846 2020-01-13  Alan Modra  <amodra@gmail.com>
 847
 848         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 849
 850 2020-01-13  Alan Modra  <amodra@gmail.com>
 851
 852         * fr30-ibld.c: Regenerate.
 853
 854 2020-01-13  Alan Modra  <amodra@gmail.com>
 855
 856         * xgate-dis.c (print_insn): Don't left shift signed value.
 857         (ripBits): Formatting, use 1u.
 858
 859 2020-01-10  Alan Modra  <amodra@gmail.com>
 860
 861         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 862         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 863
 864 2020-01-10  Alan Modra  <amodra@gmail.com>
 865
 866         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 867         and XRREG value earlier to avoid a shift with negative exponent.
 868         * m10200-dis.c (disassemble): Similarly.
 869
 870 2020-01-09  Nick Clifton  <nickc@redhat.com>
 871
 872         PR 25224
 873         * z80-dis.c (ld_ii_ii): Use correct cast.
 874
 875 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 876
 877         PR 25224
 878         * z80-dis.c (ld_ii_ii): Use character constant when checking
 879         opcode byte value.
 880
 881 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 882
 883         * i386-dis.c (SEP_Fixup): New.
 884         (SEP): Define.
 885         (dis386_twobyte): Use it for sysenter/sysexit.
 886         (enum x86_64_isa): Change amd64 enumerator to value 1.
 887         (OP_J): Compare isa64 against intel64 instead of amd64.
 888         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 889         forms.
 890         * i386-tbl.h: Re-generate.
 891
 892 2020-01-08  Alan Modra  <amodra@gmail.com>
 893
 894         * z8k-dis.c: Include libiberty.h
 895         (instr_data_s): Make max_fetched unsigned.
 896         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 897         Don't exceed byte_info bounds.
 898         (output_instr): Make num_bytes unsigned.
 899         (unpack_instr): Likewise for nibl_count and loop.
 900         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 901         idx unsigned.
 902         * z8k-opc.h: Regenerate.
 903
 904 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 905
 906         * arc-tbl.h (llock): Use 'LLOCK' as class.
 907         (llockd): Likewise.
 908         (scond): Use 'SCOND' as class.
 909         (scondd): Likewise.
 910         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 911         (scondd): Likewise.
 912
 913 2020-01-06  Alan Modra  <amodra@gmail.com>
 914
 915         * m32c-ibld.c: Regenerate.
 916
 917 2020-01-06  Alan Modra  <amodra@gmail.com>
 918
 919         PR 25344
 920         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 921         Peek at next byte to prevent recursion on repeated prefix bytes.
 922         Ensure uninitialised "mybuf" is not accessed.
 923         (print_insn_z80): Don't zero n_fetch and n_used here,..
 924         (print_insn_z80_buf): ..do it here instead.
 925
 926 2020-01-04  Alan Modra  <amodra@gmail.com>
 927
 928         * m32r-ibld.c: Regenerate.
 929
 930 2020-01-04  Alan Modra  <amodra@gmail.com>
 931
 932         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 933
 934 2020-01-04  Alan Modra  <amodra@gmail.com>
 935
 936         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 937
 938 2020-01-04  Alan Modra  <amodra@gmail.com>
 939
 940         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 941
 942 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 943
 944         * aarch64-tbl.h (aarch64_opcode_table): Use
 945         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 946
 947 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 948
 949         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 950         forms of SUDOT and USDOT.
 951
 952 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 953
 954         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 955         uzip{1,2}.
 956         * opcodes/aarch64-dis-2.c: Re-generate.
 957
 958 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 959
 960         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 961         FMMLA encoding.
 962         * opcodes/aarch64-dis-2.c: Re-generate.
 963
 964 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 965
 966         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 967
 968 2020-01-01  Alan Modra  <amodra@gmail.com>
 969
 970         Update year range in copyright notice of all files.
 971
 972 For older changes see ChangeLog-2019
 973 \f
 974 Copyright (C) 2020 Free Software Foundation, Inc.
 975
 976 Copying and distribution of this file, with or without modification,
 977 are permitted in any medium without royalty provided the copyright
 978 notice and this notice are preserved.
 979
 980 Local Variables:
 981 mode: change-log
 982 left-margin: 8
 983 fill-column: 74
 984 version-control: never
 985 End: