opcodes/ChangeLog

   1 2020-03-09  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
   4         3-operand pseudos.
   5         * i386-tbl.h: Re-generate.
   6
   7 2020-03-09  Jan Beulich  <jbeulich@suse.com>
   8
   9         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
  10         vprot*, vpsha*, and vpshl*.
  11         * i386-tbl.h: Re-generate.
  12
  13 2020-03-09  Jan Beulich  <jbeulich@suse.com>
  14
  15         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
  16         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
  17         * i386-tbl.h: Re-generate.
  18
  19 2020-03-09  Jan Beulich  <jbeulich@suse.com>
  20
  21         * i386-gen.c (set_bitfield): Ignore zero-length field names.
  22         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
  23         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
  24         * i386-tbl.h: Re-generate.
  25
  26 2020-03-09  Jan Beulich  <jbeulich@suse.com>
  27
  28         * i386-gen.c (struct template_arg, struct template_instance,
  29         struct template_param, struct template, templates,
  30         parse_template, expand_templates): New.
  31         (process_i386_opcodes): Various local variables moved to
  32         expand_templates. Call parse_template and expand_templates.
  33         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
  34         * i386-tbl.h: Re-generate.
  35
  36 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  37
  38         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
  39         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
  40         register and memory source templates. Replace VexW= by VexW*
  41         where applicable.
  42         * i386-tbl.h: Re-generate.
  43
  44 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  45
  46         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
  47         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
  48         * i386-tbl.h: Re-generate.
  49
  50 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  51
  52         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
  53         * i386-tbl.h: Re-generate.
  54
  55 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  56
  57         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
  58         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
  59         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
  60         VexW0 on SSE2AVX variants.
  61         (vmovq): Drop NoRex64 from XMM/XMM variants.
  62         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
  63         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
  64         applicable use VexW0.
  65         * i386-tbl.h: Re-generate.
  66
  67 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  68
  69         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
  70         * i386-opc.h (Rex64): Delete.
  71         (struct i386_opcode_modifier): Remove rex64 field.
  72         * i386-opc.tbl (crc32): Drop Rex64.
  73         Replace Rex64 with Size64 everywhere else.
  74         * i386-tbl.h: Re-generate.
  75
  76 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  77
  78         * i386-dis.c (OP_E_memory): Exclude recording of used address
  79         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
  80         addressed memory operands for MPX insns.
  81
  82 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  83
  84         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
  85         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
  86         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
  87         (ptwrite): Split into non-64-bit and 64-bit forms.
  88         * i386-tbl.h: Re-generate.
  89
  90 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  91
  92         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
  93         template.
  94         * i386-tbl.h: Re-generate.
  95
  96 2020-03-04  Jan Beulich  <jbeulich@suse.com>
  97
  98         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
  99         (prefix_table): Move vmmcall here. Add vmgexit.
 100         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 101         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 102         (cpu_flags): Add CpuSEV_ES entry.
 103         * i386-opc.h (CpuSEV_ES): New.
 104         (union i386_cpu_flags): Add cpusev_es field.
 105         * i386-opc.tbl (vmgexit): New.
 106         * i386-init.h, i386-tbl.h: Re-generate.
 107
 108 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 109
 110         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 111         with MnemonicSize.
 112         * i386-opc.h (IGNORESIZE): New.
 113         (DEFAULTSIZE): Likewise.
 114         (IgnoreSize): Removed.
 115         (DefaultSize): Likewise.
 116         (MnemonicSize): New.
 117         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 118         mnemonicsize.
 119         * i386-opc.tbl (IgnoreSize): New.
 120         (DefaultSize): Likewise.
 121         * i386-tbl.h: Regenerated.
 122
 123 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 124
 125         PR 25627
 126         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 127         instructions.
 128
 129 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 130
 131         PR gas/25622
 132         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 133         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 134         * i386-tbl.h: Regenerated.
 135
 136 2020-02-26  Alan Modra  <amodra@gmail.com>
 137
 138         * aarch64-asm.c: Indent labels correctly.
 139         * aarch64-dis.c: Likewise.
 140         * aarch64-gen.c: Likewise.
 141         * aarch64-opc.c: Likewise.
 142         * alpha-dis.c: Likewise.
 143         * i386-dis.c: Likewise.
 144         * nds32-asm.c: Likewise.
 145         * nfp-dis.c: Likewise.
 146         * visium-dis.c: Likewise.
 147
 148 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 149
 150         * arc-regs.h (int_vector_base): Make it available for all ARC
 151         CPUs.
 152
 153 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 154
 155         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 156         changed.
 157
 158 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 159
 160         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 161         c.mv/c.li if rs1 is zero.
 162
 163 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 164
 165         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 166         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 167         CPU_POPCNT_FLAGS.
 168         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 169         * i386-opc.h (CpuABM): Removed.
 170         (CpuPOPCNT): New.
 171         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 172         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 173         popcnt.  Remove CpuABM from lzcnt.
 174         * i386-init.h: Regenerated.
 175         * i386-tbl.h: Likewise.
 176
 177 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 178
 179         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 180         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 181         VexW1 instead of open-coding them.
 182         * i386-tbl.h: Re-generate.
 183
 184 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 185
 186         * i386-opc.tbl (AddrPrefixOpReg): Define.
 187         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 188         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 189         templates. Drop NoRex64.
 190         * i386-tbl.h: Re-generate.
 191
 192 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 193
 194         PR gas/6518
 195         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 196         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 197         into Intel syntax instance (with Unpsecified) and AT&T one
 198         (without).
 199         (vcvtneps2bf16): Likewise, along with folding the two so far
 200         separate ones.
 201         * i386-tbl.h: Re-generate.
 202
 203 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 204
 205         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 206         CPU_ANY_SSE4A_FLAGS.
 207
 208 2020-02-17  Alan Modra  <amodra@gmail.com>
 209
 210         * i386-gen.c (cpu_flag_init): Correct last change.
 211
 212 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 213
 214         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 215         CPU_ANY_SSE4_FLAGS.
 216
 217 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 218
 219         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 220         (movzx): Likewise.
 221
 222 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 223
 224         PR gas/25438
 225         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 226         destination for Cpu64-only variant.
 227         (movzx): Fold patterns.
 228         * i386-tbl.h: Re-generate.
 229
 230 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 231
 232         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 233         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 234         CPU_ANY_SSE4_FLAGS entry.
 235         * i386-init.h: Re-generate.
 236
 237 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 238
 239         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 240         with Unspecified, making the present one AT&T syntax only.
 241         * i386-tbl.h: Re-generate.
 242
 243 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 244
 245         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 246         * i386-tbl.h: Re-generate.
 247
 248 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 249
 250         PR gas/24546
 251         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 252         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 253         Amd64 and Intel64 templates.
 254         (call, jmp): Likewise for far indirect variants. Dro
 255         Unspecified.
 256         * i386-tbl.h: Re-generate.
 257
 258 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 259
 260         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 261         * i386-opc.h (ShortForm): Delete.
 262         (struct i386_opcode_modifier): Remove shortform field.
 263         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 264         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 265         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 266         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 267         Drop ShortForm.
 268         * i386-tbl.h: Re-generate.
 269
 270 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 271
 272         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 273         fucompi): Drop ShortForm from operand-less templates.
 274         * i386-tbl.h: Re-generate.
 275
 276 2020-02-11  Alan Modra  <amodra@gmail.com>
 277
 278         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 279         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 280         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 281         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 282         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 283
 284 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 285
 286         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 287         (cde_opcodes): Add VCX* instructions.
 288
 289 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 290             Matthew Malcomson  <matthew.malcomson@arm.com>
 291
 292         * arm-dis.c (struct cdeopcode32): New.
 293         (CDE_OPCODE): New macro.
 294         (cde_opcodes): New disassembly table.
 295         (regnames): New option to table.
 296         (cde_coprocs): New global variable.
 297         (print_insn_cde): New
 298         (print_insn_thumb32): Use print_insn_cde.
 299         (parse_arm_disassembler_options): Parse coprocN args.
 300
 301 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 302
 303         PR gas/25516
 304         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 305         with ISA64.
 306         * i386-opc.h (AMD64): Removed.
 307         (Intel64): Likewose.
 308         (AMD64): New.
 309         (INTEL64): Likewise.
 310         (INTEL64ONLY): Likewise.
 311         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 312         * i386-opc.tbl (Amd64): New.
 313         (Intel64): Likewise.
 314         (Intel64Only): Likewise.
 315         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 316         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 317         * i386-tbl.h: Regenerated.
 318
 319 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 320
 321         PR 25469
 322         * z80-dis.c: Add support for GBZ80 opcodes.
 323
 324 2020-02-04  Alan Modra  <amodra@gmail.com>
 325
 326         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 327
 328 2020-02-03  Alan Modra  <amodra@gmail.com>
 329
 330         * m32c-ibld.c: Regenerate.
 331
 332 2020-02-01  Alan Modra  <amodra@gmail.com>
 333
 334         * frv-ibld.c: Regenerate.
 335
 336 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 337
 338         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 339         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 340         (OP_E_memory): Replace xmm_mdq_mode case label by
 341         vex_scalar_w_dq_mode one.
 342         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 343
 344 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 345
 346         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 347         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 348         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 349         (intel_operand_size): Drop vex_w_dq_mode case label.
 350
 351 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 352
 353         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 354         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 355
 356 2020-01-30  Alan Modra  <amodra@gmail.com>
 357
 358         * m32c-ibld.c: Regenerate.
 359
 360 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 361
 362         * bpf-opc.c: Regenerate.
 363
 364 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 365
 366         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 367         (dis386): Use them to replace C2/C3 table entries.
 368         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 369         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 370         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 371         * i386-tbl.h: Re-generate.
 372
 373 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 374
 375         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 376         forms.
 377         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 378         DefaultSize.
 379         * i386-tbl.h: Re-generate.
 380
 381 2020-01-30  Alan Modra  <amodra@gmail.com>
 382
 383         * tic4x-dis.c (tic4x_dp): Make unsigned.
 384
 385 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 386             Jan Beulich  <jbeulich@suse.com>
 387
 388         PR binutils/25445
 389         * i386-dis.c (MOVSXD_Fixup): New function.
 390         (movsxd_mode): New enum.
 391         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 392         (intel_operand_size): Handle movsxd_mode.
 393         (OP_E_register): Likewise.
 394         (OP_G): Likewise.
 395         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 396         register on movsxd.  Add movsxd with 16-bit destination register
 397         for AMD64 and Intel64 ISAs.
 398         * i386-tbl.h: Regenerated.
 399
 400 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 401
 402         PR 25403
 403         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 404         * aarch64-asm-2.c: Regenerate
 405         * aarch64-dis-2.c: Likewise.
 406         * aarch64-opc-2.c: Likewise.
 407
 408 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 409
 410         * i386-opc.tbl (sysret): Drop DefaultSize.
 411         * i386-tbl.h: Re-generate.
 412
 413 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 414
 415         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 416         Dword.
 417         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 418         * i386-tbl.h: Re-generate.
 419
 420 2020-01-20  Nick Clifton  <nickc@redhat.com>
 421
 422         * po/de.po: Updated German translation.
 423         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 424         * po/uk.po: Updated Ukranian translation.
 425
 426 2020-01-20  Alan Modra  <amodra@gmail.com>
 427
 428         * hppa-dis.c (fput_const): Remove useless cast.
 429
 430 2020-01-20  Alan Modra  <amodra@gmail.com>
 431
 432         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 433
 434 2020-01-18  Nick Clifton  <nickc@redhat.com>
 435
 436         * configure: Regenerate.
 437         * po/opcodes.pot: Regenerate.
 438
 439 2020-01-18  Nick Clifton  <nickc@redhat.com>
 440
 441         Binutils 2.34 branch created.
 442
 443 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 444
 445         * opintl.h: Fix spelling error (seperate).
 446
 447 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 448
 449         * i386-opc.tbl: Add {vex} pseudo prefix.
 450         * i386-tbl.h: Regenerated.
 451
 452 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 453
 454         PR 25376
 455         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 456         (neon_opcodes): Likewise.
 457         (select_arm_features): Make sure we enable MVE bits when selecting
 458         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 459         any architecture.
 460
 461 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 462
 463         * i386-opc.tbl: Drop stale comment from XOP section.
 464
 465 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 466
 467         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 468         (extractps): Add VexWIG to SSE2AVX forms.
 469         * i386-tbl.h: Re-generate.
 470
 471 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 472
 473         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 474         Size64 from and use VexW1 on SSE2AVX forms.
 475         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 476         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 477         * i386-tbl.h: Re-generate.
 478
 479 2020-01-15  Alan Modra  <amodra@gmail.com>
 480
 481         * tic4x-dis.c (tic4x_version): Make unsigned long.
 482         (optab, optab_special, registernames): New file scope vars.
 483         (tic4x_print_register): Set up registernames rather than
 484         malloc'd registertable.
 485         (tic4x_disassemble): Delete optable and optable_special.  Use
 486         optab and optab_special instead.  Throw away old optab,
 487         optab_special and registernames when info->mach changes.
 488
 489 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 490
 491         PR 25377
 492         * z80-dis.c (suffix): Use .db instruction to generate double
 493         prefix.
 494
 495 2020-01-14  Alan Modra  <amodra@gmail.com>
 496
 497         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 498         values to unsigned before shifting.
 499
 500 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 501
 502         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 503         flow instructions.
 504         (print_insn_thumb16, print_insn_thumb32): Likewise.
 505         (print_insn): Initialize the insn info.
 506         * i386-dis.c (print_insn): Initialize the insn info fields, and
 507         detect jumps.
 508
 509 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 510
 511         * arc-opc.c (C_NE): Make it required.
 512
 513 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 514
 515         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 516         reserved register name.
 517
 518 2020-01-13  Alan Modra  <amodra@gmail.com>
 519
 520         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 521         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 522
 523 2020-01-13  Alan Modra  <amodra@gmail.com>
 524
 525         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 526         result of wasm_read_leb128 in a uint64_t and check that bits
 527         are not lost when copying to other locals.  Use uint32_t for
 528         most locals.  Use PRId64 when printing int64_t.
 529
 530 2020-01-13  Alan Modra  <amodra@gmail.com>
 531
 532         * score-dis.c: Formatting.
 533         * score7-dis.c: Formatting.
 534
 535 2020-01-13  Alan Modra  <amodra@gmail.com>
 536
 537         * score-dis.c (print_insn_score48): Use unsigned variables for
 538         unsigned values.  Don't left shift negative values.
 539         (print_insn_score32): Likewise.
 540         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 541
 542 2020-01-13  Alan Modra  <amodra@gmail.com>
 543
 544         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 545
 546 2020-01-13  Alan Modra  <amodra@gmail.com>
 547
 548         * fr30-ibld.c: Regenerate.
 549
 550 2020-01-13  Alan Modra  <amodra@gmail.com>
 551
 552         * xgate-dis.c (print_insn): Don't left shift signed value.
 553         (ripBits): Formatting, use 1u.
 554
 555 2020-01-10  Alan Modra  <amodra@gmail.com>
 556
 557         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 558         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 559
 560 2020-01-10  Alan Modra  <amodra@gmail.com>
 561
 562         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 563         and XRREG value earlier to avoid a shift with negative exponent.
 564         * m10200-dis.c (disassemble): Similarly.
 565
 566 2020-01-09  Nick Clifton  <nickc@redhat.com>
 567
 568         PR 25224
 569         * z80-dis.c (ld_ii_ii): Use correct cast.
 570
 571 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 572
 573         PR 25224
 574         * z80-dis.c (ld_ii_ii): Use character constant when checking
 575         opcode byte value.
 576
 577 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 578
 579         * i386-dis.c (SEP_Fixup): New.
 580         (SEP): Define.
 581         (dis386_twobyte): Use it for sysenter/sysexit.
 582         (enum x86_64_isa): Change amd64 enumerator to value 1.
 583         (OP_J): Compare isa64 against intel64 instead of amd64.
 584         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 585         forms.
 586         * i386-tbl.h: Re-generate.
 587
 588 2020-01-08  Alan Modra  <amodra@gmail.com>
 589
 590         * z8k-dis.c: Include libiberty.h
 591         (instr_data_s): Make max_fetched unsigned.
 592         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 593         Don't exceed byte_info bounds.
 594         (output_instr): Make num_bytes unsigned.
 595         (unpack_instr): Likewise for nibl_count and loop.
 596         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 597         idx unsigned.
 598         * z8k-opc.h: Regenerate.
 599
 600 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 601
 602         * arc-tbl.h (llock): Use 'LLOCK' as class.
 603         (llockd): Likewise.
 604         (scond): Use 'SCOND' as class.
 605         (scondd): Likewise.
 606         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 607         (scondd): Likewise.
 608
 609 2020-01-06  Alan Modra  <amodra@gmail.com>
 610
 611         * m32c-ibld.c: Regenerate.
 612
 613 2020-01-06  Alan Modra  <amodra@gmail.com>
 614
 615         PR 25344
 616         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 617         Peek at next byte to prevent recursion on repeated prefix bytes.
 618         Ensure uninitialised "mybuf" is not accessed.
 619         (print_insn_z80): Don't zero n_fetch and n_used here,..
 620         (print_insn_z80_buf): ..do it here instead.
 621
 622 2020-01-04  Alan Modra  <amodra@gmail.com>
 623
 624         * m32r-ibld.c: Regenerate.
 625
 626 2020-01-04  Alan Modra  <amodra@gmail.com>
 627
 628         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 629
 630 2020-01-04  Alan Modra  <amodra@gmail.com>
 631
 632         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 633
 634 2020-01-04  Alan Modra  <amodra@gmail.com>
 635
 636         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 637
 638 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 639
 640         * aarch64-tbl.h (aarch64_opcode_table): Use
 641         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 642
 643 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 644
 645         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 646         forms of SUDOT and USDOT.
 647
 648 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 649
 650         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 651         uzip{1,2}.
 652         * opcodes/aarch64-dis-2.c: Re-generate.
 653
 654 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 655
 656         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 657         FMMLA encoding.
 658         * opcodes/aarch64-dis-2.c: Re-generate.
 659
 660 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 661
 662         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 663
 664 2020-01-01  Alan Modra  <amodra@gmail.com>
 665
 666         Update year range in copyright notice of all files.
 667
 668 For older changes see ChangeLog-2019
 669 \f
 670 Copyright (C) 2020 Free Software Foundation, Inc.
 671
 672 Copying and distribution of this file, with or without modification,
 673 are permitted in any medium without royalty provided the copyright
 674 notice and this notice are preserved.
 675
 676 Local Variables:
 677 mode: change-log
 678 left-margin: 8
 679 fill-column: 74
 680 version-control: never
 681 End: