opcodes/ChangeLog

   1 2020-03-06  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
   4         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
   5         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
   6         VexW0 on SSE2AVX variants.
   7         (vmovq): Drop NoRex64 from XMM/XMM variants.
   8         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
   9         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
  10         applicable use VexW0.
  11         * i386-tbl.h: Re-generate.
  12
  13 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  14
  15         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
  16         * i386-opc.h (Rex64): Delete.
  17         (struct i386_opcode_modifier): Remove rex64 field.
  18         * i386-opc.tbl (crc32): Drop Rex64.
  19         Replace Rex64 with Size64 everywhere else.
  20         * i386-tbl.h: Re-generate.
  21
  22 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  23
  24         * i386-dis.c (OP_E_memory): Exclude recording of used address
  25         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
  26         addressed memory operands for MPX insns.
  27
  28 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  29
  30         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
  31         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
  32         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
  33         (ptwrite): Split into non-64-bit and 64-bit forms.
  34         * i386-tbl.h: Re-generate.
  35
  36 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  37
  38         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
  39         template.
  40         * i386-tbl.h: Re-generate.
  41
  42 2020-03-04  Jan Beulich  <jbeulich@suse.com>
  43
  44         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
  45         (prefix_table): Move vmmcall here. Add vmgexit.
  46         (rm_table): Replace vmmcall entry by prefix_table[] escape.
  47         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
  48         (cpu_flags): Add CpuSEV_ES entry.
  49         * i386-opc.h (CpuSEV_ES): New.
  50         (union i386_cpu_flags): Add cpusev_es field.
  51         * i386-opc.tbl (vmgexit): New.
  52         * i386-init.h, i386-tbl.h: Re-generate.
  53
  54 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
  55
  56         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
  57         with MnemonicSize.
  58         * i386-opc.h (IGNORESIZE): New.
  59         (DEFAULTSIZE): Likewise.
  60         (IgnoreSize): Removed.
  61         (DefaultSize): Likewise.
  62         (MnemonicSize): New.
  63         (i386_opcode_modifier): Replace ignoresize/defaultsize with
  64         mnemonicsize.
  65         * i386-opc.tbl (IgnoreSize): New.
  66         (DefaultSize): Likewise.
  67         * i386-tbl.h: Regenerated.
  68
  69 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
  70
  71         PR 25627
  72         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
  73         instructions.
  74
  75 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
  76
  77         PR gas/25622
  78         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
  79         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
  80         * i386-tbl.h: Regenerated.
  81
  82 2020-02-26  Alan Modra  <amodra@gmail.com>
  83
  84         * aarch64-asm.c: Indent labels correctly.
  85         * aarch64-dis.c: Likewise.
  86         * aarch64-gen.c: Likewise.
  87         * aarch64-opc.c: Likewise.
  88         * alpha-dis.c: Likewise.
  89         * i386-dis.c: Likewise.
  90         * nds32-asm.c: Likewise.
  91         * nfp-dis.c: Likewise.
  92         * visium-dis.c: Likewise.
  93
  94 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
  95
  96         * arc-regs.h (int_vector_base): Make it available for all ARC
  97         CPUs.
  98
  99 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 100
 101         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 102         changed.
 103
 104 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 105
 106         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 107         c.mv/c.li if rs1 is zero.
 108
 109 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 110
 111         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 112         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 113         CPU_POPCNT_FLAGS.
 114         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 115         * i386-opc.h (CpuABM): Removed.
 116         (CpuPOPCNT): New.
 117         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 118         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 119         popcnt.  Remove CpuABM from lzcnt.
 120         * i386-init.h: Regenerated.
 121         * i386-tbl.h: Likewise.
 122
 123 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 124
 125         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 126         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 127         VexW1 instead of open-coding them.
 128         * i386-tbl.h: Re-generate.
 129
 130 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 131
 132         * i386-opc.tbl (AddrPrefixOpReg): Define.
 133         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 134         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 135         templates. Drop NoRex64.
 136         * i386-tbl.h: Re-generate.
 137
 138 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 139
 140         PR gas/6518
 141         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 142         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 143         into Intel syntax instance (with Unpsecified) and AT&T one
 144         (without).
 145         (vcvtneps2bf16): Likewise, along with folding the two so far
 146         separate ones.
 147         * i386-tbl.h: Re-generate.
 148
 149 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 150
 151         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 152         CPU_ANY_SSE4A_FLAGS.
 153
 154 2020-02-17  Alan Modra  <amodra@gmail.com>
 155
 156         * i386-gen.c (cpu_flag_init): Correct last change.
 157
 158 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 159
 160         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 161         CPU_ANY_SSE4_FLAGS.
 162
 163 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 164
 165         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 166         (movzx): Likewise.
 167
 168 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 169
 170         PR gas/25438
 171         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 172         destination for Cpu64-only variant.
 173         (movzx): Fold patterns.
 174         * i386-tbl.h: Re-generate.
 175
 176 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 177
 178         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 179         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 180         CPU_ANY_SSE4_FLAGS entry.
 181         * i386-init.h: Re-generate.
 182
 183 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 184
 185         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 186         with Unspecified, making the present one AT&T syntax only.
 187         * i386-tbl.h: Re-generate.
 188
 189 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 190
 191         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 192         * i386-tbl.h: Re-generate.
 193
 194 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 195
 196         PR gas/24546
 197         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 198         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 199         Amd64 and Intel64 templates.
 200         (call, jmp): Likewise for far indirect variants. Dro
 201         Unspecified.
 202         * i386-tbl.h: Re-generate.
 203
 204 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 205
 206         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 207         * i386-opc.h (ShortForm): Delete.
 208         (struct i386_opcode_modifier): Remove shortform field.
 209         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 210         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 211         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 212         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 213         Drop ShortForm.
 214         * i386-tbl.h: Re-generate.
 215
 216 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 217
 218         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 219         fucompi): Drop ShortForm from operand-less templates.
 220         * i386-tbl.h: Re-generate.
 221
 222 2020-02-11  Alan Modra  <amodra@gmail.com>
 223
 224         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 225         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 226         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 227         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 228         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 229
 230 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 231
 232         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 233         (cde_opcodes): Add VCX* instructions.
 234
 235 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 236             Matthew Malcomson  <matthew.malcomson@arm.com>
 237
 238         * arm-dis.c (struct cdeopcode32): New.
 239         (CDE_OPCODE): New macro.
 240         (cde_opcodes): New disassembly table.
 241         (regnames): New option to table.
 242         (cde_coprocs): New global variable.
 243         (print_insn_cde): New
 244         (print_insn_thumb32): Use print_insn_cde.
 245         (parse_arm_disassembler_options): Parse coprocN args.
 246
 247 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 248
 249         PR gas/25516
 250         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 251         with ISA64.
 252         * i386-opc.h (AMD64): Removed.
 253         (Intel64): Likewose.
 254         (AMD64): New.
 255         (INTEL64): Likewise.
 256         (INTEL64ONLY): Likewise.
 257         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 258         * i386-opc.tbl (Amd64): New.
 259         (Intel64): Likewise.
 260         (Intel64Only): Likewise.
 261         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 262         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 263         * i386-tbl.h: Regenerated.
 264
 265 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 266
 267         PR 25469
 268         * z80-dis.c: Add support for GBZ80 opcodes.
 269
 270 2020-02-04  Alan Modra  <amodra@gmail.com>
 271
 272         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 273
 274 2020-02-03  Alan Modra  <amodra@gmail.com>
 275
 276         * m32c-ibld.c: Regenerate.
 277
 278 2020-02-01  Alan Modra  <amodra@gmail.com>
 279
 280         * frv-ibld.c: Regenerate.
 281
 282 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 283
 284         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 285         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 286         (OP_E_memory): Replace xmm_mdq_mode case label by
 287         vex_scalar_w_dq_mode one.
 288         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 289
 290 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 291
 292         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 293         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 294         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 295         (intel_operand_size): Drop vex_w_dq_mode case label.
 296
 297 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 298
 299         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 300         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 301
 302 2020-01-30  Alan Modra  <amodra@gmail.com>
 303
 304         * m32c-ibld.c: Regenerate.
 305
 306 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 307
 308         * bpf-opc.c: Regenerate.
 309
 310 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 311
 312         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 313         (dis386): Use them to replace C2/C3 table entries.
 314         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 315         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 316         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 317         * i386-tbl.h: Re-generate.
 318
 319 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 320
 321         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 322         forms.
 323         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 324         DefaultSize.
 325         * i386-tbl.h: Re-generate.
 326
 327 2020-01-30  Alan Modra  <amodra@gmail.com>
 328
 329         * tic4x-dis.c (tic4x_dp): Make unsigned.
 330
 331 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 332             Jan Beulich  <jbeulich@suse.com>
 333
 334         PR binutils/25445
 335         * i386-dis.c (MOVSXD_Fixup): New function.
 336         (movsxd_mode): New enum.
 337         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 338         (intel_operand_size): Handle movsxd_mode.
 339         (OP_E_register): Likewise.
 340         (OP_G): Likewise.
 341         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 342         register on movsxd.  Add movsxd with 16-bit destination register
 343         for AMD64 and Intel64 ISAs.
 344         * i386-tbl.h: Regenerated.
 345
 346 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 347
 348         PR 25403
 349         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 350         * aarch64-asm-2.c: Regenerate
 351         * aarch64-dis-2.c: Likewise.
 352         * aarch64-opc-2.c: Likewise.
 353
 354 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 355
 356         * i386-opc.tbl (sysret): Drop DefaultSize.
 357         * i386-tbl.h: Re-generate.
 358
 359 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 360
 361         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 362         Dword.
 363         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 364         * i386-tbl.h: Re-generate.
 365
 366 2020-01-20  Nick Clifton  <nickc@redhat.com>
 367
 368         * po/de.po: Updated German translation.
 369         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 370         * po/uk.po: Updated Ukranian translation.
 371
 372 2020-01-20  Alan Modra  <amodra@gmail.com>
 373
 374         * hppa-dis.c (fput_const): Remove useless cast.
 375
 376 2020-01-20  Alan Modra  <amodra@gmail.com>
 377
 378         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 379
 380 2020-01-18  Nick Clifton  <nickc@redhat.com>
 381
 382         * configure: Regenerate.
 383         * po/opcodes.pot: Regenerate.
 384
 385 2020-01-18  Nick Clifton  <nickc@redhat.com>
 386
 387         Binutils 2.34 branch created.
 388
 389 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 390
 391         * opintl.h: Fix spelling error (seperate).
 392
 393 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 394
 395         * i386-opc.tbl: Add {vex} pseudo prefix.
 396         * i386-tbl.h: Regenerated.
 397
 398 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 399
 400         PR 25376
 401         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 402         (neon_opcodes): Likewise.
 403         (select_arm_features): Make sure we enable MVE bits when selecting
 404         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 405         any architecture.
 406
 407 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 408
 409         * i386-opc.tbl: Drop stale comment from XOP section.
 410
 411 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 412
 413         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 414         (extractps): Add VexWIG to SSE2AVX forms.
 415         * i386-tbl.h: Re-generate.
 416
 417 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 418
 419         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 420         Size64 from and use VexW1 on SSE2AVX forms.
 421         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 422         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 423         * i386-tbl.h: Re-generate.
 424
 425 2020-01-15  Alan Modra  <amodra@gmail.com>
 426
 427         * tic4x-dis.c (tic4x_version): Make unsigned long.
 428         (optab, optab_special, registernames): New file scope vars.
 429         (tic4x_print_register): Set up registernames rather than
 430         malloc'd registertable.
 431         (tic4x_disassemble): Delete optable and optable_special.  Use
 432         optab and optab_special instead.  Throw away old optab,
 433         optab_special and registernames when info->mach changes.
 434
 435 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 436
 437         PR 25377
 438         * z80-dis.c (suffix): Use .db instruction to generate double
 439         prefix.
 440
 441 2020-01-14  Alan Modra  <amodra@gmail.com>
 442
 443         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 444         values to unsigned before shifting.
 445
 446 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 447
 448         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 449         flow instructions.
 450         (print_insn_thumb16, print_insn_thumb32): Likewise.
 451         (print_insn): Initialize the insn info.
 452         * i386-dis.c (print_insn): Initialize the insn info fields, and
 453         detect jumps.
 454
 455 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 456
 457         * arc-opc.c (C_NE): Make it required.
 458
 459 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 460
 461         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 462         reserved register name.
 463
 464 2020-01-13  Alan Modra  <amodra@gmail.com>
 465
 466         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 467         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 468
 469 2020-01-13  Alan Modra  <amodra@gmail.com>
 470
 471         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 472         result of wasm_read_leb128 in a uint64_t and check that bits
 473         are not lost when copying to other locals.  Use uint32_t for
 474         most locals.  Use PRId64 when printing int64_t.
 475
 476 2020-01-13  Alan Modra  <amodra@gmail.com>
 477
 478         * score-dis.c: Formatting.
 479         * score7-dis.c: Formatting.
 480
 481 2020-01-13  Alan Modra  <amodra@gmail.com>
 482
 483         * score-dis.c (print_insn_score48): Use unsigned variables for
 484         unsigned values.  Don't left shift negative values.
 485         (print_insn_score32): Likewise.
 486         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 487
 488 2020-01-13  Alan Modra  <amodra@gmail.com>
 489
 490         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 491
 492 2020-01-13  Alan Modra  <amodra@gmail.com>
 493
 494         * fr30-ibld.c: Regenerate.
 495
 496 2020-01-13  Alan Modra  <amodra@gmail.com>
 497
 498         * xgate-dis.c (print_insn): Don't left shift signed value.
 499         (ripBits): Formatting, use 1u.
 500
 501 2020-01-10  Alan Modra  <amodra@gmail.com>
 502
 503         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 504         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 505
 506 2020-01-10  Alan Modra  <amodra@gmail.com>
 507
 508         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 509         and XRREG value earlier to avoid a shift with negative exponent.
 510         * m10200-dis.c (disassemble): Similarly.
 511
 512 2020-01-09  Nick Clifton  <nickc@redhat.com>
 513
 514         PR 25224
 515         * z80-dis.c (ld_ii_ii): Use correct cast.
 516
 517 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 518
 519         PR 25224
 520         * z80-dis.c (ld_ii_ii): Use character constant when checking
 521         opcode byte value.
 522
 523 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 524
 525         * i386-dis.c (SEP_Fixup): New.
 526         (SEP): Define.
 527         (dis386_twobyte): Use it for sysenter/sysexit.
 528         (enum x86_64_isa): Change amd64 enumerator to value 1.
 529         (OP_J): Compare isa64 against intel64 instead of amd64.
 530         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 531         forms.
 532         * i386-tbl.h: Re-generate.
 533
 534 2020-01-08  Alan Modra  <amodra@gmail.com>
 535
 536         * z8k-dis.c: Include libiberty.h
 537         (instr_data_s): Make max_fetched unsigned.
 538         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 539         Don't exceed byte_info bounds.
 540         (output_instr): Make num_bytes unsigned.
 541         (unpack_instr): Likewise for nibl_count and loop.
 542         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 543         idx unsigned.
 544         * z8k-opc.h: Regenerate.
 545
 546 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 547
 548         * arc-tbl.h (llock): Use 'LLOCK' as class.
 549         (llockd): Likewise.
 550         (scond): Use 'SCOND' as class.
 551         (scondd): Likewise.
 552         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 553         (scondd): Likewise.
 554
 555 2020-01-06  Alan Modra  <amodra@gmail.com>
 556
 557         * m32c-ibld.c: Regenerate.
 558
 559 2020-01-06  Alan Modra  <amodra@gmail.com>
 560
 561         PR 25344
 562         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 563         Peek at next byte to prevent recursion on repeated prefix bytes.
 564         Ensure uninitialised "mybuf" is not accessed.
 565         (print_insn_z80): Don't zero n_fetch and n_used here,..
 566         (print_insn_z80_buf): ..do it here instead.
 567
 568 2020-01-04  Alan Modra  <amodra@gmail.com>
 569
 570         * m32r-ibld.c: Regenerate.
 571
 572 2020-01-04  Alan Modra  <amodra@gmail.com>
 573
 574         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 575
 576 2020-01-04  Alan Modra  <amodra@gmail.com>
 577
 578         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 579
 580 2020-01-04  Alan Modra  <amodra@gmail.com>
 581
 582         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 583
 584 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 585
 586         * aarch64-tbl.h (aarch64_opcode_table): Use
 587         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 588
 589 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 590
 591         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 592         forms of SUDOT and USDOT.
 593
 594 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 595
 596         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 597         uzip{1,2}.
 598         * opcodes/aarch64-dis-2.c: Re-generate.
 599
 600 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 601
 602         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 603         FMMLA encoding.
 604         * opcodes/aarch64-dis-2.c: Re-generate.
 605
 606 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 607
 608         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 609
 610 2020-01-01  Alan Modra  <amodra@gmail.com>
 611
 612         Update year range in copyright notice of all files.
 613
 614 For older changes see ChangeLog-2019
 615 \f
 616 Copyright (C) 2020 Free Software Foundation, Inc.
 617
 618 Copying and distribution of this file, with or without modification,
 619 are permitted in any medium without royalty provided the copyright
 620 notice and this notice are preserved.
 621
 622 Local Variables:
 623 mode: change-log
 624 left-margin: 8
 625 fill-column: 74
 626 version-control: never
 627 End: