opcodes/ChangeLog

   1 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
   2
   3         * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
   4         apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
   5         apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
   6         (aarch64_sys_reg_supported_p): Add feature test for new registers.
   7
   8 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
   9
  10         * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
  11         (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
  12         autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
  13         autibsp.
  14         * aarch64-asm-2.c: Regenerate.
  15         * aarch64-dis-2.c: Regenerate.
  16
  17 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  18
  19         * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
  20
  21 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
  22
  23         PR binutils/20799
  24         * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
  25         * i386-dis.c (EdqwS): Removed.
  26         (dqw_swap_mode): Likewise.
  27         (intel_operand_size): Don't check dqw_swap_mode.
  28         (OP_E_register): Likewise.
  29         (OP_E_memory): Likewise.
  30         (OP_G): Likewise.
  31         (OP_EX): Likewise.
  32         * i386-opc.tbl: Remove "S" from EVEX vpextrw.
  33         * i386-tbl.h: Regerated.
  34
  35 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
  36
  37         * i386-opc.tbl: Merge AVX512F vmovq.
  38         * i386-tbl.h: Regerated.
  39
  40 2016-11-08  H.J. Lu  <hongjiu.lu@intel.com>
  41
  42         PR binutils/20701
  43         * i386-dis.c (THREE_BYTE_0F7A): Removed.
  44         (dis386_twobyte): Don't use THREE_BYTE_0F7A.
  45         (three_byte_table): Remove THREE_BYTE_0F7A.
  46
  47 2016-11-07  H.J. Lu  <hongjiu.lu@intel.com>
  48
  49         PR binutils/20775
  50         * i386-dis.c (FGRPd9_2): Replace 0 with 1.
  51         (FGRPd9_4): Replace 1 with 2.
  52         (FGRPd9_5): Replace 2 with 3.
  53         (FGRPd9_6): Replace 3 with 4.
  54         (FGRPd9_7): Replace 4 with 5.
  55         (FGRPda_5): Replace 5 with 6.
  56         (FGRPdb_4): Replace 6 with 7.
  57         (FGRPde_3): Replace 7 with 8.
  58         (FGRPdf_4): Replace 8 with 9.
  59         (fgrps): Add an entry for Bad_Opcode.
  60
  61 2016-11-04  Andrew Burgess  <andrew.burgess@embecosm.com>
  62
  63         * arc-opc.c (arc_flag_operands): Add F_DI14.
  64         (arc_flag_classes): Add C_DI14.
  65         * arc-nps400-tbl.h: Add new exc instructions.
  66
  67 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
  68
  69         * arc-dis.c (arc_insn_length): Return length 8 for instructions with
  70         major opcode 0xa.
  71         * arc-nps-400-tbl.h: Add dcmac instruction.
  72         * arc-opc.c (arc_operands): Added operands for dcmac instruction.
  73         (insert_nps_rbdouble_64): Added.
  74         (extract_nps_rbdouble_64): Added.
  75         (insert_nps_proto_size): Added.
  76         (extract_nps_proto_size): Added.
  77
  78 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
  79
  80         * arc-dis.c (struct arc_operand_iterator): Remove all fields
  81         relating to long instruction processing, add new limm field.
  82         (OPCODE): Rename to...
  83         (OPCODE_32BIT_INSN): ...this.
  84         (OPCODE_AC): Delete.
  85         (skip_this_opcode): Handle different instruction lengths, update
  86         macro name.
  87         (special_flag_p): Update parameter type.
  88         (find_format_from_table): Update for more instruction lengths.
  89         (find_format_long_instructions): Delete.
  90         (find_format): Update for more instruction lengths.
  91         (arc_insn_length): Likewise.
  92         (extract_operand_value): Update for more instruction lengths.
  93         (operand_iterator_next): Remove code relating to long
  94         instructions.
  95         (arc_opcode_to_insn_type): New function.
  96         (print_insn_arc):Update for more instructions lengths.
  97         * arc-ext.c (extInstruction_t): Change argument type.
  98         * arc-ext.h (extInstruction_t): Change argument type.
  99         * arc-fxi.h: Change type unsigned to unsigned long long
 100         extensively throughout.
 101         * arc-nps400-tbl.h: Add long instructions taken from
 102         arc_long_opcodes table in arc-opc.c.
 103         * arc-opc.c: Update parameter types on insert/extract handlers.
 104         (arc_long_opcodes): Delete.
 105         (arc_num_long_opcodes): Delete.
 106         (arc_opcode_len): Update for more instruction lengths.
 107
 108 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 109
 110         * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
 111
 112 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 113
 114         * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
 115         with arc_opcode_len.
 116         (find_format_long_instructions): Likewise.
 117         * arc-opc.c (arc_opcode_len): New function.
 118
 119 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 120
 121         * arc-nps400-tbl.h: Fix some instruction masks.
 122
 123 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 124
 125         * i386-dis.c (REG_82): Removed.
 126         (X86_64_82_REG_0): Likewise.
 127         (X86_64_82_REG_1): Likewise.
 128         (X86_64_82_REG_2): Likewise.
 129         (X86_64_82_REG_3): Likewise.
 130         (X86_64_82_REG_4): Likewise.
 131         (X86_64_82_REG_5): Likewise.
 132         (X86_64_82_REG_6): Likewise.
 133         (X86_64_82_REG_7): Likewise.
 134         (X86_64_82): New.
 135         (dis386): Use X86_64_82 instead of REG_82.
 136         (reg_table): Remove REG_82.
 137         (x86_64_table): Add X86_64_82.  Remove X86_64_82_REG_0,
 138         X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
 139         X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
 140         X86_64_82_REG_7.
 141
 142 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 143
 144         PR binutils/20754
 145         * i386-dis.c (REG_82): New.
 146         (X86_64_82_REG_0): Likewise.
 147         (X86_64_82_REG_1): Likewise.
 148         (X86_64_82_REG_2): Likewise.
 149         (X86_64_82_REG_3): Likewise.
 150         (X86_64_82_REG_4): Likewise.
 151         (X86_64_82_REG_5): Likewise.
 152         (X86_64_82_REG_6): Likewise.
 153         (X86_64_82_REG_7): Likewise.
 154         (dis386): Use REG_82.
 155         (reg_table): Add REG_82.
 156         (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
 157         X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
 158         X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
 159
 160 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 161
 162         * i386-dis.c (REG_82): Renamed to ...
 163         (REG_83): This.
 164         (dis386): Updated.
 165         (reg_table): Likewise.
 166
 167 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 168
 169         * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
 170         * i386-dis-evex.h (evex_table): Updated.
 171         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
 172         CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 173         (cpu_flags): Add CpuAVX512_4VNNIW.
 174         * i386-opc.h (enum): (AVX512_4VNNIW): New.
 175         (i386_cpu_flags): Add cpuavx512_4vnniw.
 176         * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
 177         * i386-init.h: Regenerate.
 178         * i386-tbl.h: Ditto.
 179
 180 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 181
 182         * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
 183         PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
 184         * i386-dis-evex.h (evex_table): Updated.
 185         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
 186         CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 187         (cpu_flags): Add CpuAVX512_4FMAPS.
 188         (opcode_modifiers): Add ImplicitQuadGroup modifier.
 189         * i386-opc.h (AVX512_4FMAP): New.
 190         (i386_cpu_flags): Add cpuavx512_4fmaps.
 191         (ImplicitQuadGroup): New.
 192         (i386_opcode_modifier): Add implicitquadgroup.
 193         * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
 194         * i386-init.h: Regenerate.
 195         * i386-tbl.h: Ditto.
 196
 197 2016-11-01  Palmer Dabbelt  <palmer@dabbelt.com>
 198             Andrew Waterman <andrew@sifive.com>
 199
 200         Add support for RISC-V architecture.
 201         * configure.ac: Add entry for bfd_riscv_arch.
 202         * configure: Regenerate.
 203         * disassemble.c (disassembler): Add support for riscv.
 204         (disassembler_usage): Likewise.
 205         * riscv-dis.c: New file.
 206         * riscv-opc.c: New file.
 207
 208 2016-10-21  H.J. Lu  <hongjiu.lu@intel.com>
 209
 210         * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
 211         (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
 212         (rm_table): Update the RM_0FAE_REG_7 entry.
 213         * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
 214         (cpu_flags): Remove CpuPCOMMIT.
 215         * i386-opc.h (CpuPCOMMIT): Removed.
 216         (i386_cpu_flags): Remove cpupcommit.
 217         * i386-opc.tbl: Remove pcommit.
 218         * i386-init.h: Regenerated.
 219         * i386-tbl.h: Likewise.
 220
 221 2016-10-20  H.J. Lu  <hongjiu.lu@intel.com>
 222
 223         PR binutis/20705
 224         * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
 225         the highest bit in VEX.vvvv for the 3-byte VEX prefix in
 226         32-bit mode.  Don't check vex.register_specifier in 32-bit
 227         mode.
 228         (OP_VEX): Check for invalid mask registers.
 229
 230 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 231
 232         PR binutis/20699
 233         * i386-dis.c (OP_E_memory): Check addr32flag in stead of
 234         sizeflag.
 235
 236 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 237
 238         PR binutis/20704
 239         * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
 240
 241 2016-10-18  Maciej W. Rozycki  <macro@imgtec.com>
 242
 243         * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
 244         local variable to `index_regno'.
 245
 246 2016-10-17  Cupertino Miranda  <cmiranda@synopsys.com>
 247
 248         * arc-tbl.h: Removed any "inv.+" instructions from the table.
 249
 250 2016-10-14  Claudiu Zissulescu  <claziss@synopsys.com>
 251
 252         * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
 253         usage on ISA basis.
 254
 255 2016-10-11  Jiong Wang  <jiong.wang@arm.com>
 256
 257         PR target/20666
 258         * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
 259
 260 2016-10-07  Jiong Wang  <jiong.wang@arm.com>
 261
 262         PR target/20667
 263         * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
 264         available.
 265
 266 2016-10-07  Alan Modra  <amodra@gmail.com>
 267
 268         * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
 269
 270 2016-10-06  Alan Modra  <amodra@gmail.com>
 271
 272         * aarch64-opc.c: Spell fall through comments consistently.
 273         * i386-dis.c: Likewise.
 274         * aarch64-dis.c: Add missing fall through comments.
 275         * aarch64-opc.c: Likewise.
 276         * arc-dis.c: Likewise.
 277         * arm-dis.c: Likewise.
 278         * i386-dis.c: Likewise.
 279         * m68k-dis.c: Likewise.
 280         * mep-asm.c: Likewise.
 281         * ns32k-dis.c: Likewise.
 282         * sh-dis.c: Likewise.
 283         * tic4x-dis.c: Likewise.
 284         * tic6x-dis.c: Likewise.
 285         * vax-dis.c: Likewise.
 286
 287 2016-10-06  Alan Modra  <amodra@gmail.com>
 288
 289         * arc-ext.c (create_map): Add missing break.
 290         * msp430-decode.opc (encode_as): Likewise.
 291         * msp430-decode.c: Regenerate.
 292
 293 2016-10-06  Alan Modra  <amodra@gmail.com>
 294
 295         * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
 296         * crx-dis.c (print_insn_crx): Likewise.
 297
 298 2016-09-30  H.J. Lu  <hongjiu.lu@intel.com>
 299
 300         PR binutils/20657
 301         * i386-dis.c (putop): Don't assign alt twice.
 302
 303 2016-09-29  Jiong Wang  <jiong.wang@arm.com>
 304
 305         PR target/20553
 306         * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
 307
 308 2016-09-29  Alan Modra  <amodra@gmail.com>
 309
 310         * ppc-opc.c (L): Make compulsory.
 311         (LOPT): New, optional form of L.
 312         (HTM_R): Define as LOPT.
 313         (L0, L1): Delete.
 314         (L32OPT): New, optional for 32-bit L.
 315         (L2OPT): New, 2-bit L for dcbf.
 316         (SVC_LEC): Update.
 317         (L2): Define.
 318         (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
 319         (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
 320         <dcbf>: Use L2OPT.
 321         <tlbiel, tlbie>: Use LOPT.
 322         <wclr, wclrall>: Use L2.
 323
 324 2016-09-26  Vlad Zakharov  <vzakhar@synopsys.com>
 325
 326         * Makefile.in: Regenerate.
 327         * configure: Likewise.
 328
 329 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
 330
 331         * arc-ext-tbl.h (EXTINSN2OPF): Define.
 332         (EXTINSN2OP): Use EXTINSN2OPF.
 333         (bspeekm, bspop, modapp): New extension instructions.
 334         * arc-opc.c (F_DNZ_ND): Define.
 335         (F_DNZ_D): Likewise.
 336         (F_SIZEB1): Changed.
 337         (C_DNZ_D): Define.
 338         (C_HARD): Changed.
 339         * arc-tbl.h (dbnz): New instruction.
 340         (prealloc): Allow it for ARC EM.
 341         (xbfu): Likewise.
 342
 343 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 344
 345         * aarch64-opc.c (print_immediate_offset_address): Print spaces
 346         after commas in addresses.
 347         (aarch64_print_operand): Likewise.
 348
 349 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 350
 351         * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
 352         rather than "should be" or "expected to be" in error messages.
 353
 354 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 355
 356         * aarch64-dis.c (remove_dot_suffix): New function, split out from...
 357         (print_mnemonic_name): ...here.
 358         (print_comment): New function.
 359         (print_aarch64_insn): Call it.
 360         * aarch64-opc.c (aarch64_conds): Add SVE names.
 361         (aarch64_print_operand): Print alternative condition names in
 362         a comment.
 363
 364 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 365
 366         * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
 367         (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
 368         (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
 369         (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
 370         (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
 371         (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
 372         (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
 373         (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
 374         (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
 375         (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
 376         (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
 377         (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
 378         (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
 379         (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
 380         (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
 381         (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
 382         (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
 383         (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
 384         (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
 385         (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
 386         (OP_SVE_XWU, OP_SVE_XXU): New macros.
 387         (aarch64_feature_sve): New variable.
 388         (SVE): New macro.
 389         (_SVE_INSN): Likewise.
 390         (aarch64_opcode_table): Add SVE instructions.
 391         * aarch64-opc.h (extract_fields): Declare.
 392         * aarch64-opc-2.c: Regenerate.
 393         * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
 394         * aarch64-asm-2.c: Regenerate.
 395         * aarch64-dis.c (extract_fields): Make global.
 396         (do_misc_decoding): Handle the new SVE aarch64_ops.
 397         * aarch64-dis-2.c: Regenerate.
 398
 399 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 400
 401         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
 402         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
 403         aarch64_field_kinds.
 404         * aarch64-opc.c (fields): Add corresponding entries.
 405         * aarch64-asm.c (aarch64_get_variant): New function.
 406         (aarch64_encode_variant_using_iclass): Likewise.
 407         (aarch64_opcode_encode): Call it.
 408         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
 409         (aarch64_opcode_decode): Call it.
 410
 411 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 412
 413         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
 414         and FP register operands.
 415         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
 416         (FLD_SVE_Vn): New aarch64_field_kinds.
 417         * aarch64-opc.c (fields): Add corresponding entries.
 418         (aarch64_print_operand): Handle the new SVE core and FP register
 419         operands.
 420         * aarch64-opc-2.c: Regenerate.
 421         * aarch64-asm-2.c: Likewise.
 422         * aarch64-dis-2.c: Likewise.
 423
 424 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 425
 426         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
 427         immediate operands.
 428         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
 429         * aarch64-opc.c (fields): Add corresponding entry.
 430         (operand_general_constraint_met_p): Handle the new SVE FP immediate
 431         operands.
 432         (aarch64_print_operand): Likewise.
 433         * aarch64-opc-2.c: Regenerate.
 434         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
 435         (ins_sve_float_zero_one): New inserters.
 436         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
 437         (aarch64_ins_sve_float_half_two): Likewise.
 438         (aarch64_ins_sve_float_zero_one): Likewise.
 439         * aarch64-asm-2.c: Regenerate.
 440         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
 441         (ext_sve_float_zero_one): New extractors.
 442         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
 443         (aarch64_ext_sve_float_half_two): Likewise.
 444         (aarch64_ext_sve_float_zero_one): Likewise.
 445         * aarch64-dis-2.c: Regenerate.
 446
 447 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 448
 449         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 450         integer immediate operands.
 451         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
 452         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
 453         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
 454         * aarch64-opc.c (fields): Add corresponding entries.
 455         (operand_general_constraint_met_p): Handle the new SVE integer
 456         immediate operands.
 457         (aarch64_print_operand): Likewise.
 458         (aarch64_sve_dupm_mov_immediate_p): New function.
 459         * aarch64-opc-2.c: Regenerate.
 460         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
 461         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
 462         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
 463         (aarch64_ins_limm): ...here.
 464         (aarch64_ins_inv_limm): New function.
 465         (aarch64_ins_sve_aimm): Likewise.
 466         (aarch64_ins_sve_asimm): Likewise.
 467         (aarch64_ins_sve_limm_mov): Likewise.
 468         (aarch64_ins_sve_shlimm): Likewise.
 469         (aarch64_ins_sve_shrimm): Likewise.
 470         * aarch64-asm-2.c: Regenerate.
 471         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
 472         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
 473         * aarch64-dis.c (decode_limm): New function, split out from...
 474         (aarch64_ext_limm): ...here.
 475         (aarch64_ext_inv_limm): New function.
 476         (decode_sve_aimm): Likewise.
 477         (aarch64_ext_sve_aimm): Likewise.
 478         (aarch64_ext_sve_asimm): Likewise.
 479         (aarch64_ext_sve_limm_mov): Likewise.
 480         (aarch64_top_bit): Likewise.
 481         (aarch64_ext_sve_shlimm): Likewise.
 482         (aarch64_ext_sve_shrimm): Likewise.
 483         * aarch64-dis-2.c: Regenerate.
 484
 485 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 486
 487         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
 488         operands.
 489         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
 490         the AARCH64_MOD_MUL_VL entry.
 491         (value_aligned_p): Cope with non-power-of-two alignments.
 492         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
 493         (print_immediate_offset_address): Likewise.
 494         (aarch64_print_operand): Likewise.
 495         * aarch64-opc-2.c: Regenerate.
 496         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
 497         (ins_sve_addr_ri_s9xvl): New inserters.
 498         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 499         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 500         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 501         * aarch64-asm-2.c: Regenerate.
 502         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 503         (ext_sve_addr_ri_s9xvl): New extractors.
 504         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 505         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 506         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 507         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 508         * aarch64-dis-2.c: Regenerate.
 509
 510 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 511
 512         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 513         address operands.
 514         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 515         (FLD_SVE_xs_22): New aarch64_field_kinds.
 516         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 517         (get_operand_specific_data): New function.
 518         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 519         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 520         (operand_general_constraint_met_p): Handle the new SVE address
 521         operands.
 522         (sve_reg): New array.
 523         (get_addr_sve_reg_name): New function.
 524         (aarch64_print_operand): Handle the new SVE address operands.
 525         * aarch64-opc-2.c: Regenerate.
 526         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 527         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 528         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 529         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 530         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 531         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 532         (aarch64_ins_sve_addr_zi_u5): Likewise.
 533         (aarch64_ins_sve_addr_zz): Likewise.
 534         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 535         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 536         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 537         * aarch64-asm-2.c: Regenerate.
 538         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 539         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 540         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 541         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 542         (aarch64_ext_sve_addr_ri_u6): Likewise.
 543         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 544         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 545         (aarch64_ext_sve_addr_zi_u5): Likewise.
 546         (aarch64_ext_sve_addr_zz): Likewise.
 547         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 548         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 549         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 550         * aarch64-dis-2.c: Regenerate.
 551
 552 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 553
 554         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 555         AARCH64_OPND_SVE_PATTERN_SCALED.
 556         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 557         * aarch64-opc.c (fields): Add a corresponding entry.
 558         (set_multiplier_out_of_range_error): New function.
 559         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 560         (operand_general_constraint_met_p): Handle
 561         AARCH64_OPND_SVE_PATTERN_SCALED.
 562         (print_register_offset_address): Use PRIi64 to print the
 563         shift amount.
 564         (aarch64_print_operand): Likewise.  Handle
 565         AARCH64_OPND_SVE_PATTERN_SCALED.
 566         * aarch64-opc-2.c: Regenerate.
 567         * aarch64-asm.h (ins_sve_scale): New inserter.
 568         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 569         * aarch64-asm-2.c: Regenerate.
 570         * aarch64-dis.h (ext_sve_scale): New inserter.
 571         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 572         * aarch64-dis-2.c: Regenerate.
 573
 574 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 575
 576         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 577         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 578         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 579         (FLD_SVE_prfop): Likewise.
 580         * aarch64-opc.c: Include libiberty.h.
 581         (aarch64_sve_pattern_array): New variable.
 582         (aarch64_sve_prfop_array): Likewise.
 583         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 584         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 585         AARCH64_OPND_SVE_PRFOP.
 586         * aarch64-asm-2.c: Regenerate.
 587         * aarch64-dis-2.c: Likewise.
 588         * aarch64-opc-2.c: Likewise.
 589
 590 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 591
 592         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 593         AARCH64_OPND_QLF_P_[ZM].
 594         (aarch64_print_operand): Print /z and /m where appropriate.
 595
 596 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 597
 598         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 599         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
 600         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
 601         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
 602         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
 603         * aarch64-opc.c (fields): Add corresponding entries here.
 604         (operand_general_constraint_met_p): Check that SVE register lists
 605         have the correct length.  Check the ranges of SVE index registers.
 606         Check for cases where p8-p15 are used in 3-bit predicate fields.
 607         (aarch64_print_operand): Handle the new SVE operands.
 608         * aarch64-opc-2.c: Regenerate.
 609         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 610         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 611         (aarch64_ins_sve_reglist): Likewise.
 612         * aarch64-asm-2.c: Regenerate.
 613         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 614         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 615         (aarch64_ext_sve_reglist): Likewise.
 616         * aarch64-dis-2.c: Regenerate.
 617
 618 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 619
 620         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 621         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 622         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 623         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 624         tied operands.
 625
 626 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 627
 628         * aarch64-opc.c (get_offset_int_reg_name): New function.
 629         (print_immediate_offset_address): Likewise.
 630         (print_register_offset_address): Take the base and offset
 631         registers as parameters.
 632         (aarch64_print_operand): Update caller accordingly.  Use
 633         print_immediate_offset_address.
 634
 635 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 636
 637         * aarch64-opc.c (BANK): New macro.
 638         (R32, R64): Take a register number as argument
 639         (int_reg): Use BANK.
 640
 641 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 642
 643         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 644         (aarch64_print_operand): Update accordingly.
 645
 646 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 647
 648         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
 649         for FPIMM.
 650         * aarch64-asm.h (ins_fpimm): New inserter.
 651         * aarch64-asm.c (aarch64_ins_fpimm): New function.
 652         * aarch64-asm-2.c: Regenerate.
 653         * aarch64-dis.h (ext_fpimm): New extractor.
 654         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
 655         (aarch64_ext_fpimm): New function.
 656         * aarch64-dis-2.c: Regenerate.
 657
 658 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 659
 660         * aarch64-asm.c: Include libiberty.h.
 661         (insert_fields): New function.
 662         (aarch64_ins_imm): Use it.
 663         * aarch64-dis.c (extract_fields): New function.
 664         (aarch64_ext_imm): Use it.
 665
 666 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 667
 668         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
 669         with an esize parameter.
 670         (operand_general_constraint_met_p): Update accordingly.
 671         Fix misindented code.
 672         * aarch64-asm.c (aarch64_ins_limm): Update call to
 673         aarch64_logical_immediate_p.
 674
 675 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 676
 677         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
 678
 679 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 680
 681         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
 682
 683 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
 684
 685         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
 686
 687 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
 688
 689         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
 690         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
 691         xor3>: Delete mnemonics.
 692         <cp_abort>: Rename mnemonic from ...
 693         <cpabort>: ...to this.
 694         <setb>: Change to a X form instruction.
 695         <sync>: Change to 1 operand form.
 696         <copy>: Delete mnemonic.
 697         <copy_first>: Rename mnemonic from ...
 698         <copy>: ...to this.
 699         <paste, paste.>: Delete mnemonics.
 700         <paste_last>: Rename mnemonic from ...
 701         <paste.>: ...to this.
 702
 703 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 704
 705         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
 706
 707 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 708
 709         * s390-mkopc.c (main): Support alternate arch strings.
 710
 711 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
 712
 713         * s390-opc.txt: Fix kmctr instruction type.
 714
 715 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
 716
 717         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
 718         * i386-init.h: Regenerated.
 719
 720 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
 721
 722         * opcodes/arc-dis.c (print_insn_arc): Changed.
 723
 724 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
 725
 726         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
 727         camellia_fl.
 728
 729 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 730
 731         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
 732         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
 733         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
 734
 735 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
 736
 737         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
 738         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
 739         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
 740         PREFIX_MOD_3_0FAE_REG_4.
 741         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
 742         PREFIX_MOD_3_0FAE_REG_4.
 743         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
 744         (cpu_flags): Add CpuPTWRITE.
 745         * i386-opc.h (CpuPTWRITE): New.
 746         (i386_cpu_flags): Add cpuptwrite.
 747         * i386-opc.tbl: Add ptwrite instruction.
 748         * i386-init.h: Regenerated.
 749         * i386-tbl.h: Likewise.
 750
 751 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 752
 753         * arc-dis.h: Wrap around in extern "C".
 754
 755 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 756
 757         * aarch64-tbl.h (V8_2_INSN): New macro.
 758         (aarch64_opcode_table): Use it.
 759
 760 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 761
 762         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
 763         CORE_INSN, __FP_INSN and SIMD_INSN.
 764
 765 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 766
 767         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
 768         (aarch64_opcode_table): Update uses accordingly.
 769
 770 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
 771         Kwok Cheung Yeung  <kcy@codesourcery.com>
 772
 773         opcodes/
 774         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
 775         'e_cmplwi' to 'e_cmpli' instead.
 776         (OPVUPRT, OPVUPRT_MASK): Define.
 777         (powerpc_opcodes): Add E200Z4 insns.
 778         (vle_opcodes): Add context save/restore insns.
 779
 780 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
 781
 782         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
 783         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
 784         "j".
 785
 786 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 787
 788         * arc-nps400-tbl.h: Change block comments to GNU format.
 789         * arc-dis.c: Add new globals addrtypenames,
 790         addrtypenames_max, and addtypeunknown.
 791         (get_addrtype): New function.
 792         (print_insn_arc): Print colons and address types when
 793         required.
 794         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
 795         define insert and extract functions for all address types.
 796         (arc_operands): Add operands for colon and all address
 797         types.
 798         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
 799         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
 800         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
 801         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
 802         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
 803         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
 804
 805 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
 806
 807         * configure: Regenerated.
 808
 809 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
 810
 811         * arc-dis.c (skipclass): New structure.
 812         (decodelist): New variable.
 813         (is_compatible_p): New function.
 814         (new_element): Likewise.
 815         (skip_class_p): Likewise.
 816         (find_format_from_table): Use skip_class_p function.
 817         (find_format): Decode first the extension instructions.
 818         (print_insn_arc): Select either ARCEM or ARCHS based on elf
 819         e_flags.
 820         (parse_option): New function.
 821         (parse_disassembler_options): Likewise.
 822         (print_arc_disassembler_options): Likewise.
 823         (print_insn_arc): Use parse_disassembler_options function.  Proper
 824         select ARCv2 cpu variant.
 825         * disassemble.c (disassembler_usage): Add ARC disassembler
 826         options.
 827
 828 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
 829
 830         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
 831         annotation from the "nal" entry and reorder it beyond "bltzal".
 832
 833 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
 834
 835         * sparc-opc.c (ldtxa): New macro.
 836         (sparc_opcodes): Use the macro defined above to add entries for
 837         the LDTXA instructions.
 838         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
 839         instruction.
 840
 841 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
 842
 843         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
 844         and "jmpc".
 845
 846 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 847
 848         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
 849         (movzb): Adjust to cover all permitted suffixes.
 850         (movzw): New.
 851         * i386-tbl.h: Re-generate.
 852
 853 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 854
 855         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
 856         (lgdt): Remove Tbyte from non-64-bit variant.
 857         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
 858         xsaves64, xsavec64): Remove Disp16.
 859         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
 860         Remove Disp32S from non-64-bit variants. Remove Disp16 from
 861         64-bit variants.
 862         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
 863         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
 864         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
 865         64-bit variants.
 866         * i386-tbl.h: Re-generate.
 867
 868 2016-07-01  Jan Beulich  <jbeulich@suse.com>
 869
 870         * i386-opc.tbl (xlat): Remove RepPrefixOk.
 871         * i386-tbl.h: Re-generate.
 872
 873 2016-06-30  Yao Qi  <yao.qi@linaro.org>
 874
 875         * arm-dis.c (print_insn): Fix typo in comment.
 876
 877 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
 878
 879         * aarch64-opc.c (operand_general_constraint_met_p): Check the
 880         range of ldst_elemlist operands.
 881         (print_register_list): Use PRIi64 to print the index.
 882         (aarch64_print_operand): Likewise.
 883
 884 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 885
 886         * mcore-opc.h: Remove sentinal.
 887         * mcore-dis.c (print_insn_mcore): Adjust.
 888
 889 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
 890
 891         * arc-opc.c: Correct description of availability of NPS400
 892         features.
 893
 894 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
 895
 896         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
 897         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
 898         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
 899         xor3>: New mnemonics.
 900         <setb>: Change to a VX form instruction.
 901         (insert_sh6): Add support for rldixor.
 902         (extract_sh6): Likewise.
 903
 904 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 905
 906         * arc-ext.h: Wrap in extern C.
 907
 908 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
 909
 910         * arc-dis.c (arc_insn_length): Add comment on instruction length.
 911         Use same method for determining instruction length on ARC700 and
 912         NPS-400.
 913         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
 914         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
 915         with the NPS400 subclass.
 916         * arc-opc.c: Likewise.
 917
 918 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 919
 920         * sparc-opc.c (rdasr): New macro.
 921         (wrasr): Likewise.
 922         (rdpr): Likewise.
 923         (wrpr): Likewise.
 924         (rdhpr): Likewise.
 925         (wrhpr): Likewise.
 926         (sparc_opcodes): Use the macros above to fix and expand the
 927         definition of read/write instructions from/to
 928         asr/privileged/hyperprivileged instructions.
 929         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
 930         %hva_mask_nz.  Prefer softint_set and softint_clear over
 931         set_softint and clear_softint.
 932         (print_insn_sparc): Support %ver in Rd.
 933
 934 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 935
 936         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
 937         architecture according to the hardware capabilities they require.
 938
 939 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 940
 941         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
 942         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
 943         bfd_mach_sparc_v9{c,d,e,v,m}.
 944         * sparc-opc.c (MASK_V9C): Define.
 945         (MASK_V9D): Likewise.
 946         (MASK_V9E): Likewise.
 947         (MASK_V9V): Likewise.
 948         (MASK_V9M): Likewise.
 949         (v6): Add MASK_V9{C,D,E,V,M}.
 950         (v6notlet): Likewise.
 951         (v7): Likewise.
 952         (v8): Likewise.
 953         (v9): Likewise.
 954         (v9andleon): Likewise.
 955         (v9a): Likewise.
 956         (v9b): Likewise.
 957         (v9c): Define.
 958         (v9d): Likewise.
 959         (v9e): Likewise.
 960         (v9v): Likewise.
 961         (v9m): Likewise.
 962         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
 963
 964 2016-06-15  Nick Clifton  <nickc@redhat.com>
 965
 966         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
 967         constants to match expected behaviour.
 968         (nds32_parse_opcode): Likewise.  Also for whitespace.
 969
 970 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
 971
 972         * arc-opc.c (extract_rhv1): Extract value from insn.
 973
 974 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 975
 976         * arc-nps400-tbl.h: Add ldbit instruction.
 977         * arc-opc.c: Add flag classes required for ldbit.
 978
 979 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 980
 981         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
 982         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 983         support the above instructions.
 984
 985 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 986
 987         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
 988         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
 989         csma, cbba, zncv, and hofs.
 990         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 991         support the above instructions.
 992
 993 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 994
 995         * arc-nps400-tbl.h: Add andab and orab instructions.
 996
 997 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 998
 999         * arc-nps400-tbl.h: Add addl-like instructions.
1000
1001 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1002
1003         * arc-nps400-tbl.h: Add mxb and imxb instructions.
1004
1005 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1006
1007         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1008         instructions.
1009
1010 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1011
1012         * s390-dis.c (option_use_insn_len_bits_p): New file scope
1013         variable.
1014         (init_disasm): Handle new command line option "insnlength".
1015         (print_s390_disassembler_options): Mention new option in help
1016         output.
1017         (print_insn_s390): Use the encoded insn length when dumping
1018         unknown instructions.
1019
1020 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
1021
1022         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1023          to the address and set as symbol address for LDS/ STS immediate operands.
1024
1025 2016-06-07  Alan Modra  <amodra@gmail.com>
1026
1027         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
1028         cpu for "vle" to e500.
1029         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1030         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1031         (PPCNONE): Delete, substitute throughout.
1032         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
1033         except for major opcode 4 and 31.
1034         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1035
1036 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
1037
1038         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1039         ARM_EXT_RAS in relevant entries.
1040
1041 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
1042
1043         PR binutils/20196
1044         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1045         opcodes for E6500.
1046
1047 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
1048
1049         PR binutis/18386
1050         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1051         (indir_v_mode): New.
1052         Add comments for '&'.
1053         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1054         (putop): Handle '&'.
1055         (intel_operand_size): Handle indir_v_mode.
1056         (OP_E_register): Likewise.
1057         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
1058         64-bit indirect call/jmp for AMD64.
1059         * i386-tbl.h: Regenerated
1060
1061 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1062
1063         * arc-dis.c (struct arc_operand_iterator): New structure.
1064         (find_format_from_table): All the old content from find_format,
1065         with some minor adjustments, and parameter renaming.
1066         (find_format_long_instructions): New function.
1067         (find_format): Rewritten.
1068         (arc_insn_length): Add LSB parameter.
1069         (extract_operand_value): New function.
1070         (operand_iterator_next): New function.
1071         (print_insn_arc): Use new functions to find opcode, and iterator
1072         over operands.
1073         * arc-opc.c (insert_nps_3bit_dst_short): New function.
1074         (extract_nps_3bit_dst_short): New function.
1075         (insert_nps_3bit_src2_short): New function.
1076         (extract_nps_3bit_src2_short): New function.
1077         (insert_nps_bitop1_size): New function.
1078         (extract_nps_bitop1_size): New function.
1079         (insert_nps_bitop2_size): New function.
1080         (extract_nps_bitop2_size): New function.
1081         (insert_nps_bitop_mod4_msb): New function.
1082         (extract_nps_bitop_mod4_msb): New function.
1083         (insert_nps_bitop_mod4_lsb): New function.
1084         (extract_nps_bitop_mod4_lsb): New function.
1085         (insert_nps_bitop_dst_pos3_pos4): New function.
1086         (extract_nps_bitop_dst_pos3_pos4): New function.
1087         (insert_nps_bitop_ins_ext): New function.
1088         (extract_nps_bitop_ins_ext): New function.
1089         (arc_operands): Add new operands.
1090         (arc_long_opcodes): New global array.
1091         (arc_num_long_opcodes): New global.
1092         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1093
1094 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1095
1096         * nds32-asm.h: Add extern "C".
1097         * sh-opc.h: Likewise.
1098
1099 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
1100
1101         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1102         0,b,limm to the rflt instruction.
1103
1104 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1105
1106         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1107         constant.
1108
1109 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
1110
1111         PR gas/20145
1112         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1113         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1114         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1115         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1116         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1117         * i386-init.h: Regenerated.
1118
1119 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1120
1121         PR gas/20145
1122         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
1123         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
1124         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1125         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1126         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
1127         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1128         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1129         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
1130         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1131         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1132         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
1133         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
1134         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
1135         CpuRegMask for AVX512.
1136         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1137         and CpuRegMask.
1138         (set_bitfield_from_cpu_flag_init): New function.
1139         (set_bitfield): Remove const on f.  Call
1140         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1141         * i386-opc.h (CpuRegMMX): New.
1142         (CpuRegXMM): Likewise.
1143         (CpuRegYMM): Likewise.
1144         (CpuRegZMM): Likewise.
1145         (CpuRegMask): Likewise.
1146         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1147         and cpuregmask.
1148         * i386-init.h: Regenerated.
1149         * i386-tbl.h: Likewise.
1150
1151 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1152
1153         PR gas/20154
1154         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1155         (opcode_modifiers): Add AMD64 and Intel64.
1156         (main): Properly verify CpuMax.
1157         * i386-opc.h (CpuAMD64): Removed.
1158         (CpuIntel64): Likewise.
1159         (CpuMax): Set to CpuNo64.
1160         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1161         (AMD64): New.
1162         (Intel64): Likewise.
1163         (i386_opcode_modifier): Add amd64 and intel64.
1164         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1165         on call and jmp.
1166         * i386-init.h: Regenerated.
1167         * i386-tbl.h: Likewise.
1168
1169 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1170
1171         PR gas/20154
1172         * i386-gen.c (main): Fail if CpuMax is incorrect.
1173         * i386-opc.h (CpuMax): Set to CpuIntel64.
1174         * i386-tbl.h: Regenerated.
1175
1176 2016-05-27  Nick Clifton  <nickc@redhat.com>
1177
1178         PR target/20150
1179         * msp430-dis.c (msp430dis_read_two_bytes): New function.
1180         (msp430dis_opcode_unsigned): New function.
1181         (msp430dis_opcode_signed): New function.
1182         (msp430_singleoperand): Use the new opcode reading functions.
1183         Only disassenmble bytes if they were successfully read.
1184         (msp430_doubleoperand): Likewise.
1185         (msp430_branchinstr): Likewise.
1186         (msp430x_callx_instr): Likewise.
1187         (print_insn_msp430): Check that it is safe to read bytes before
1188         attempting disassembly.  Use the new opcode reading functions.
1189
1190 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
1191
1192         * ppc-opc.c (CY): New define.  Document it.
1193         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1194
1195 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1196
1197         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1198         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1199         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
1200         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1201         CPU_ANY_AVX_FLAGS.
1202         * i386-init.h: Regenerated.
1203
1204 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1205
1206         PR gas/20141
1207         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1208         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1209         * i386-init.h: Regenerated.
1210
1211 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1212
1213         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1214         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
1215         * i386-init.h: Regenerated.
1216
1217 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1218
1219         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1220         information.
1221         (print_insn_arc): Set insn_type information.
1222         * arc-opc.c (C_CC): Add F_CLASS_COND.
1223         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1224         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1225         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1226         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1227         (brne, brne_s, jeq_s, jne_s): Likewise.
1228
1229 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1230
1231         * arc-tbl.h (neg): New instruction variant.
1232
1233 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
1234
1235         * arc-dis.c (find_format, find_format, get_auxreg)
1236         (print_insn_arc): Changed.
1237         * arc-ext.h (INSERT_XOP): Likewise.
1238
1239 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1240
1241         * tic54x-dis.c (sprint_mmr): Adjust.
1242         * tic54x-opc.c: Likewise.
1243
1244 2016-05-19  Alan Modra  <amodra@gmail.com>
1245
1246         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1247
1248 2016-05-19  Alan Modra  <amodra@gmail.com>
1249
1250         * ppc-opc.c: Formatting.
1251         (NSISIGNOPT): Define.
1252         (powerpc_opcodes <subis>): Use NSISIGNOPT.
1253
1254 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
1255
1256         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1257         replacing references to `micromips_ase' throughout.
1258         (_print_insn_mips): Don't use file-level microMIPS annotation to
1259         determine the disassembly mode with the symbol table.
1260
1261 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
1262
1263         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1264
1265 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
1266
1267         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1268         mips64r6.
1269         * mips-opc.c (D34): New macro.
1270         (mips_builtin_opcodes): Define bposge32c for DSPr3.
1271
1272 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
1273
1274         * i386-dis.c (prefix_table): Add RDPID instruction.
1275         * i386-gen.c (cpu_flag_init): Add RDPID flag.
1276         (cpu_flags): Add RDPID bitfield.
1277         * i386-opc.h (enum): Add RDPID element.
1278         (i386_cpu_flags): Add RDPID field.
1279         * i386-opc.tbl: Add RDPID instruction.
1280         * i386-init.h: Regenerate.
1281         * i386-tbl.h: Regenerate.
1282
1283 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1284
1285         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1286         branch type of a symbol.
1287         (print_insn): Likewise.
1288
1289 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1290
1291         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1292         Mainline Security Extensions instructions.
1293         (thumb_opcodes): Add entries for narrow ARMv8-M Security
1294         Extensions instructions.
1295         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1296         instructions.
1297         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1298         special registers.
1299
1300 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
1301
1302         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1303
1304 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
1305
1306         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1307         (arcExtMap_genOpcode): Likewise.
1308         * arc-opc.c (arg_32bit_rc): Define new variable.
1309         (arg_32bit_u6): Likewise.
1310         (arg_32bit_limm): Likewise.
1311
1312 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1313
1314         * aarch64-gen.c (VERIFIER): Define.
1315         * aarch64-opc.c (VERIFIER): Define.
1316         (verify_ldpsw): Use static linkage.
1317         * aarch64-opc.h (verify_ldpsw): Remove.
1318         * aarch64-tbl.h: Use VERIFIER for verifiers.
1319
1320 2016-04-28  Nick Clifton  <nickc@redhat.com>
1321
1322         PR target/19722
1323         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1324         * aarch64-opc.c (verify_ldpsw): New function.
1325         * aarch64-opc.h (verify_ldpsw): New prototype.
1326         * aarch64-tbl.h: Add initialiser for verifier field.
1327         (LDPSW): Set verifier to verify_ldpsw.
1328
1329 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
1330
1331         PR binutils/19983
1332         PR binutils/19984
1333         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1334         smaller than address size.
1335
1336 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1337
1338         * alpha-dis.c: Regenerate.
1339         * crx-dis.c: Likewise.
1340         * disassemble.c: Likewise.
1341         * epiphany-opc.c: Likewise.
1342         * fr30-opc.c: Likewise.
1343         * frv-opc.c: Likewise.
1344         * ip2k-opc.c: Likewise.
1345         * iq2000-opc.c: Likewise.
1346         * lm32-opc.c: Likewise.
1347         * lm32-opinst.c: Likewise.
1348         * m32c-opc.c: Likewise.
1349         * m32r-opc.c: Likewise.
1350         * m32r-opinst.c: Likewise.
1351         * mep-opc.c: Likewise.
1352         * mt-opc.c: Likewise.
1353         * or1k-opc.c: Likewise.
1354         * or1k-opinst.c: Likewise.
1355         * tic80-opc.c: Likewise.
1356         * xc16x-opc.c: Likewise.
1357         * xstormy16-opc.c: Likewise.
1358
1359 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1360
1361         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1362         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1363         calcsd, and calcxd instructions.
1364         * arc-opc.c (insert_nps_bitop_size): Delete.
1365         (extract_nps_bitop_size): Delete.
1366         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1367         (extract_nps_qcmp_m3): Define.
1368         (extract_nps_qcmp_m2): Define.
1369         (extract_nps_qcmp_m1): Define.
1370         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1371         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1372         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1373         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1374         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1375         NPS_QCMP_M3.
1376
1377 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1378
1379         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1380
1381 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1382
1383         * Makefile.in: Regenerated with automake 1.11.6.
1384         * aclocal.m4: Likewise.
1385
1386 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1387
1388         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1389         instructions.
1390         * arc-opc.c (insert_nps_cmem_uimm16): New function.
1391         (extract_nps_cmem_uimm16): New function.
1392         (arc_operands): Add NPS_XLDST_UIMM16 operand.
1393
1394 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1395
1396         * arc-dis.c (arc_insn_length): New function.
1397         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1398         (find_format): Change insnLen parameter to unsigned.
1399
1400 2016-04-13  Nick Clifton  <nickc@redhat.com>
1401
1402         PR target/19937
1403         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1404         the LD.B and LD.BU instructions.
1405
1406 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1407
1408         * arc-dis.c (find_format): Check for extension flags.
1409         (print_flags): New function.
1410         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1411         .extAuxRegister.
1412         * arc-ext.c (arcExtMap_coreRegName): Use
1413         LAST_EXTENSION_CORE_REGISTER.
1414         (arcExtMap_coreReadWrite): Likewise.
1415         (dump_ARC_extmap): Update printing.
1416         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1417         (arc_aux_regs): Add cpu field.
1418         * arc-regs.h: Add cpu field, lower case name aux registers.
1419
1420 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1421
1422         * arc-tbl.h: Add rtsc, sleep with no arguments.
1423
1424 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1425
1426         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1427         Initialize.
1428         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1429         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1430         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1431         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1432         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1433         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1434         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1435         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1436         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1437         (arc_opcode arc_opcodes): Null terminate the array.
1438         (arc_num_opcodes): Remove.
1439         * arc-ext.h (INSERT_XOP): Define.
1440         (extInstruction_t): Likewise.
1441         (arcExtMap_instName): Delete.
1442         (arcExtMap_insn): New function.
1443         (arcExtMap_genOpcode): Likewise.
1444         * arc-ext.c (ExtInstruction): Remove.
1445         (create_map): Zero initialize instruction fields.
1446         (arcExtMap_instName): Remove.
1447         (arcExtMap_insn): New function.
1448         (dump_ARC_extmap): More info while debuging.
1449         (arcExtMap_genOpcode): New function.
1450         * arc-dis.c (find_format): New function.
1451         (print_insn_arc): Use find_format.
1452         (arc_get_disassembler): Enable dump_ARC_extmap only when
1453         debugging.
1454
1455 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1456
1457         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1458         instruction bits out.
1459
1460 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1461
1462         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1463         * arc-opc.c (arc_flag_operands): Add new flags.
1464         (arc_flag_classes): Add new classes.
1465
1466 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1467
1468         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1469
1470 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1471
1472         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1473         encode1, rflt, crc16, and crc32 instructions.
1474         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1475         (arc_flag_classes): Add C_NPS_R.
1476         (insert_nps_bitop_size_2b): New function.
1477         (extract_nps_bitop_size_2b): Likewise.
1478         (insert_nps_bitop_uimm8): Likewise.
1479         (extract_nps_bitop_uimm8): Likewise.
1480         (arc_operands): Add new operand entries.
1481
1482 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1483
1484         * arc-regs.h: Add a new subclass field.  Add double assist
1485         accumulator register values.
1486         * arc-tbl.h: Use DPA subclass to mark the double assist
1487         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1488         * arc-opc.c (RSP): Define instead of SP.
1489         (arc_aux_regs): Add the subclass field.
1490
1491 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1492
1493         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1494
1495 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1496
1497         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1498         NPS_R_SRC1.
1499
1500 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1501
1502         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1503         issues.  No functional changes.
1504
1505 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1506
1507         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1508         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1509         (RTT): Remove duplicate.
1510         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1511         (PCT_CONFIG*): Remove.
1512         (D1L, D1H, D2H, D2L): Define.
1513
1514 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1515
1516         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1517
1518 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1519
1520         * arc-tbl.h (invld07): Remove.
1521         * arc-ext-tbl.h: New file.
1522         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1523         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1524
1525 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1526
1527         Fix -Wstack-usage warnings.
1528         * aarch64-dis.c (print_operands): Substitute size.
1529         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1530
1531 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1532
1533         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1534         to get a proper diagnostic when an invalid ASR register is used.
1535
1536 2016-03-22  Nick Clifton  <nickc@redhat.com>
1537
1538         * configure: Regenerate.
1539
1540 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1541
1542         * arc-nps400-tbl.h: New file.
1543         * arc-opc.c: Add top level comment.
1544         (insert_nps_3bit_dst): New function.
1545         (extract_nps_3bit_dst): New function.
1546         (insert_nps_3bit_src2): New function.
1547         (extract_nps_3bit_src2): New function.
1548         (insert_nps_bitop_size): New function.
1549         (extract_nps_bitop_size): New function.
1550         (arc_flag_operands): Add nps400 entries.
1551         (arc_flag_classes): Add nps400 entries.
1552         (arc_operands): Add nps400 entries.
1553         (arc_opcodes): Add nps400 include.
1554
1555 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1556
1557         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1558         the new class enum values.
1559
1560 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1561
1562         * arc-dis.c (print_insn_arc): Handle nps400.
1563
1564 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1565
1566         * arc-opc.c (BASE): Delete.
1567
1568 2016-03-18  Nick Clifton  <nickc@redhat.com>
1569
1570         PR target/19721
1571         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1572         of MOV insn that aliases an ORR insn.
1573
1574 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1575
1576         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1577
1578 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1579
1580         * mcore-opc.h: Add const qualifiers.
1581         * microblaze-opc.h (struct op_code_struct): Likewise.
1582         * sh-opc.h: Likewise.
1583         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1584         (tic4x_print_op): Likewise.
1585
1586 2016-03-02  Alan Modra  <amodra@gmail.com>
1587
1588         * or1k-desc.h: Regenerate.
1589         * fr30-ibld.c: Regenerate.
1590         * rl78-decode.c: Regenerate.
1591
1592 2016-03-01  Nick Clifton  <nickc@redhat.com>
1593
1594         PR target/19747
1595         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1596
1597 2016-02-24  Renlin Li  <renlin.li@arm.com>
1598
1599         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1600         (print_insn_coprocessor): Support fp16 instructions.
1601
1602 2016-02-24  Renlin Li  <renlin.li@arm.com>
1603
1604         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1605         vminnm, vrint(mpna).
1606
1607 2016-02-24  Renlin Li  <renlin.li@arm.com>
1608
1609         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1610         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1611
1612 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1613
1614         * i386-dis.c (print_insn): Parenthesize expression to prevent
1615         truncated addresses.
1616         (OP_J): Likewise.
1617
1618 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1619             Janek van Oirschot  <jvanoirs@synopsys.com>
1620
1621         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1622         variable.
1623
1624 2016-02-04  Nick Clifton  <nickc@redhat.com>
1625
1626         PR target/19561
1627         * msp430-dis.c (print_insn_msp430): Add a special case for
1628         decoding an RRC instruction with the ZC bit set in the extension
1629         word.
1630
1631 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1632
1633         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1634         * epiphany-ibld.c: Regenerate.
1635         * fr30-ibld.c: Regenerate.
1636         * frv-ibld.c: Regenerate.
1637         * ip2k-ibld.c: Regenerate.
1638         * iq2000-ibld.c: Regenerate.
1639         * lm32-ibld.c: Regenerate.
1640         * m32c-ibld.c: Regenerate.
1641         * m32r-ibld.c: Regenerate.
1642         * mep-ibld.c: Regenerate.
1643         * mt-ibld.c: Regenerate.
1644         * or1k-ibld.c: Regenerate.
1645         * xc16x-ibld.c: Regenerate.
1646         * xstormy16-ibld.c: Regenerate.
1647
1648 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1649
1650         * epiphany-dis.c: Regenerated from latest cpu files.
1651
1652 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1653
1654         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1655         test bit.
1656
1657 2016-01-25  Renlin Li  <renlin.li@arm.com>
1658
1659         * arm-dis.c (mapping_symbol_for_insn): New function.
1660         (find_ifthen_state): Call mapping_symbol_for_insn().
1661
1662 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1663
1664         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1665         of MSR UAO immediate operand.
1666
1667 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1668
1669         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1670         instruction support.
1671
1672 2016-01-17  Alan Modra  <amodra@gmail.com>
1673
1674         * configure: Regenerate.
1675
1676 2016-01-14  Nick Clifton  <nickc@redhat.com>
1677
1678         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1679         instructions that can support stack pointer operations.
1680         * rl78-decode.c: Regenerate.
1681         * rl78-dis.c: Fix display of stack pointer in MOVW based
1682         instructions.
1683
1684 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1685
1686         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1687         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1688         erxtatus_el1 and erxaddr_el1.
1689
1690 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1691
1692         * arm-dis.c (arm_opcodes): Add "esb".
1693         (thumb_opcodes): Likewise.
1694
1695 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1696
1697         * ppc-opc.c <xscmpnedp>: Delete.
1698         <xvcmpnedp>: Likewise.
1699         <xvcmpnedp.>: Likewise.
1700         <xvcmpnesp>: Likewise.
1701         <xvcmpnesp.>: Likewise.
1702
1703 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1704
1705         PR gas/13050
1706         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1707         addition to ISA_A.
1708
1709 2016-01-01  Alan Modra  <amodra@gmail.com>
1710
1711         Update year range in copyright notice of all files.
1712
1713 For older changes see ChangeLog-2015
1714 \f
1715 Copyright (C) 2016 Free Software Foundation, Inc.
1716
1717 Copying and distribution of this file, with or without modification,
1718 are permitted in any medium without royalty provided the copyright
1719 notice and this notice are preserved.
1720
1721 Local Variables:
1722 mode: change-log
1723 left-margin: 8
1724 fill-column: 74
1725 version-control: never
1726 End: