opcodes/ChangeLog

   1 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
   2
   3         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
   4         immediate in br.n instruction.
   5
   6 2021-03-25  Jan Beulich  <jbeulich@suse.com>
   7
   8         * i386-dis.c (XMGatherD, VexGatherD): New.
   9         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
  10         (print_insn): Check masking for S/G insns.
  11         (OP_E_memory): New local variable check_gather. Extend mandatory
  12         SIB check. Check register conflicts for (EVEX-encoded) gathers.
  13         Extend check for disallowed 16-bit addressing.
  14         (OP_VEX): New local variables modrm_reg and sib_index. Convert
  15         if()s to switch(). Check register conflicts for (VEX-encoded)
  16         gathers. Drop no longer reachable cases.
  17         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
  18         vgatherdp*.
  19
  20 2021-03-25  Jan Beulich  <jbeulich@suse.com>
  21
  22         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
  23         zeroing-masking without masking.
  24
  25 2021-03-25  Jan Beulich  <jbeulich@suse.com>
  26
  27         * i386-opc.tbl (invlpgb): Fix multi-operand form.
  28         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
  29         single-operand forms as deprecated.
  30         * i386-tbl.h: Re-generate.
  31
  32 2021-03-25  Alan Modra  <amodra@gmail.com>
  33
  34         PR 27647
  35         * ppc-opc.c (XLOCB_MASK): Delete.
  36         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
  37         XLBH_MASK.
  38         (powerpc_opcodes): Accept a BH field on all extended forms of
  39         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
  40
  41 2021-03-24  Jan Beulich  <jbeulich@suse.com>
  42
  43         * i386-gen.c (output_i386_opcode): Drop processing of
  44         opcode_length. Calculate length from base_opcode. Adjust prefix
  45         encoding determination.
  46         (process_i386_opcodes): Drop output of fake opcode_length.
  47         * i386-opc.h (struct insn_template): Drop opcode_length field.
  48         * i386-opc.tbl: Drop opcode length field from all templates.
  49         * i386-tbl.h: Re-generate.
  50
  51 2021-03-24  Jan Beulich  <jbeulich@suse.com>
  52
  53         * i386-gen.c (process_i386_opcode_modifier): Return void. New
  54         parameter "prefix". Drop local variable "regular_encoding".
  55         Record prefix setting / check for consistency.
  56         (output_i386_opcode): Parse opcode_length and base_opcode
  57         earlier. Derive prefix encoding. Drop no longer applicable
  58         consistency checking. Adjust process_i386_opcode_modifier()
  59         invocation.
  60         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
  61         invocation.
  62         * i386-tbl.h: Re-generate.
  63
  64 2021-03-24  Jan Beulich  <jbeulich@suse.com>
  65
  66         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
  67         check.
  68         * i386-opc.h (Prefix_*): Move #define-s.
  69         * i386-opc.tbl: Move pseudo prefix enumerator values to
  70         extension opcode field. Introduce pseudopfx template.
  71         * i386-tbl.h: Re-generate.
  72
  73 2021-03-23  Jan Beulich  <jbeulich@suse.com>
  74
  75         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
  76         comment.
  77         * i386-tbl.h: Re-generate.
  78
  79 2021-03-23  Jan Beulich  <jbeulich@suse.com>
  80
  81         * i386-opc.h (struct insn_template): Move cpu_flags field past
  82         opcode_modifier one.
  83         * i386-tbl.h: Re-generate.
  84
  85 2021-03-23  Jan Beulich  <jbeulich@suse.com>
  86
  87         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
  88         * i386-opc.h (OpcodeSpace): New enumerator.
  89         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
  90         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
  91         SPACE_XOP09, SPACE_XOP0A): ... respectively.
  92         (struct i386_opcode_modifier): New field opcodespace. Shrink
  93         opcodeprefix field.
  94         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
  95         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
  96         OpcodePrefix uses.
  97         * i386-tbl.h: Re-generate.
  98
  99 2021-03-22  Martin Liska  <mliska@suse.cz>
 100
 101         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 102         * arc-dis.c (parse_option): Likewise.
 103         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 104         * cris-dis.c (print_with_operands): Likewise.
 105         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 106         * i386-dis.c (print_insn): Likewise.
 107         * ia64-gen.c (fetch_insn_class): Likewise.
 108         (parse_resource_users): Likewise.
 109         (in_iclass): Likewise.
 110         (lookup_specifier): Likewise.
 111         (insert_opcode_dependencies): Likewise.
 112         * mips-dis.c (parse_mips_ase_option): Likewise.
 113         (parse_mips_dis_option): Likewise.
 114         * s390-dis.c (disassemble_init_s390): Likewise.
 115         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 116
 117 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 118
 119         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 120
 121 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 122
 123         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 124         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 125
 126 2021-03-12  Alan Modra  <amodra@gmail.com>
 127
 128         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 129
 130 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 131
 132         * i386-dis.c (OP_XMM): Re-order checks.
 133
 134 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 135
 136         * i386-dis.c (putop): Drop need_vex check when also checking
 137         vex.evex.
 138         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 139         checking vex.b.
 140
 141 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 142
 143         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 144         checks. Move case label past broadcast check.
 145
 146 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 147
 148         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 149         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 150         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 151         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 152         EVEX_W_0F38C7_M_0_L_2): Delete.
 153         (REG_EVEX_0F38C7_M_0_L_2): New.
 154         (intel_operand_size): Handle VEX and EVEX the same for
 155         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 156         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 157         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 158         vex_vsib_q_w_d_mode uses.
 159         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 160         0F38A1, and 0F38A3 entries.
 161         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 162         entry.
 163         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 164         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 165         0F38A3 entries.
 166
 167 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 168
 169         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 170         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 171         MOD_VEX_0FXOP_09_12): Rename to ...
 172         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 173         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 174         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 175         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 176         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 177         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 178         (reg_table): Adjust comments.
 179         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 180         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 181         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 182         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 183         (vex_len_table): Adjust opcode 0A_12 entry.
 184         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 185         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 186         (rm_table): Move hreset entry.
 187
 188 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 189
 190         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 191         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 192         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 193         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 194         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 195         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 196         (get_valid_dis386): Also handle 512-bit vector length when
 197         vectoring into vex_len_table[].
 198         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 199         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 200         entries.
 201         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 202         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 203         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 204         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 205         entries.
 206
 207 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 208
 209         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 210         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 211         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 212         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 213         entries.
 214         * i386-dis-evex-len.h (evex_len_table): Likewise.
 215         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 216
 217 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 218
 219         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 220         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 221         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 222         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 223         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 224         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 225         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 226         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 227         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 228         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 229         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 230         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 231         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 232         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 233         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 234         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 235         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 236         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 237         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 238         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 239         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 240         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 241         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 242         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 243         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 244         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 245         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 246         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 247         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 248         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 249         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 250         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 251         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 252         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 253         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 254         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 255         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 256         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 257         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 258         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 259         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 260         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 261         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 262         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 263         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 264         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 265         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 266         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 267         EVEX_W_0F3A43_L_n): New.
 268         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 269         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 270         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 271         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 272         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 273         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 274         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 275         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 276         0F385B, 0F38C6, and 0F38C7 entries.
 277         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 278         0F38C6 and 0F38C7.
 279         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 280         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 281         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 282         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 283
 284 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 285
 286         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 287         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 288         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 289         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 290         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 291         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 292         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 293         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 294         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 295         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 296         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 297         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 298         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 299         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 300         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 301         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 302         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 303         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 304         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 305         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 306         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 307         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 308         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 309         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 310         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 311         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 312         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 313         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 314         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 315         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 316         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 317         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 318         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 319         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 320         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 321         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 322         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 323         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 324         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 325         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 326         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 327         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 328         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 329         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 330         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 331         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 332         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 333         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 334         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 335         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 336         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 337         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 338         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 339         VEX_W_0F99_P_2_LEN_0): Delete.
 340         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 341         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 342         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 343         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 344         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 345         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 346         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 347         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 348         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 349         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 350         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 351         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 352         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 353         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 354         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 355         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 356         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 357         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 358         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 359         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 360         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 361         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 362         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 363         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 364         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 365         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 366         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 367         (prefix_table): No longer link to vex_len_table[] for opcodes
 368         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 369         0F92, 0F93, 0F98, and 0F99.
 370         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 371         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 372         0F98, and 0F99.
 373         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 374         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 375         0F98, and 0F99.
 376         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 377         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 378         0F98, and 0F99.
 379         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 380         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 381         0F98, and 0F99.
 382
 383 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 384
 385         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 386         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 387         REG_VEX_0F73_M_0 respectively.
 388         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 389         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 390         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 391         MOD_VEX_0F73_REG_7): Delete.
 392         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 393         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 394         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 395         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 396         PREFIX_VEX_0F3AF0_L_0 respectively.
 397         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 398         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 399         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 400         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 401         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 402         VEX_LEN_0F38F7): New.
 403         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 404         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 405         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 406         0F38F3.
 407         (prefix_table): No longer link to vex_len_table[] for opcodes
 408         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 409         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 410         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 411         0F38F6, 0F38F7, and 0F3AF0.
 412         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 413         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 414         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 415         0F73.
 416
 417 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 418
 419         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 420         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 421         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 422         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 423         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 424         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 425         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 426         73.
 427         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 428         0F72, and 0F73.
 429         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 430         0F73.
 431
 432 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 433
 434         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 435         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 436         (reg_table): Don't link to mod_table[] where not needed. Add
 437         PREFIX_IGNORED to nop entries.
 438         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 439         (mod_table): Add nop entries next to prefetch ones. Drop
 440         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 441         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 442         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 443         PREFIX_OPCODE from endbr* entries.
 444         (get_valid_dis386): Also consider entry's name when zapping
 445         vindex.
 446         (print_insn): Handle PREFIX_IGNORED.
 447
 448 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 449
 450         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 451         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 452         element.
 453         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 454         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 455         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 456         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 457         (struct i386_opcode_modifier): Delete notrackprefixok,
 458         islockable, hleprefixok, and repprefixok fields. Add prefixok
 459         field.
 460         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 461         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 462         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 463         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 464         Replace HLEPrefixOk.
 465         * opcodes/i386-tbl.h: Re-generate.
 466
 467 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 468
 469         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 470         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 471         64-bit form.
 472         * opcodes/i386-tbl.h: Re-generate.
 473
 474 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 475
 476         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 477         for {} instead of {0}. Don't look for '0'.
 478         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 479         size specifiers.
 480
 481 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 482
 483         PR 27158
 484         * riscv-dis.c (print_insn_args): Updated encoding macros.
 485         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 486         (match_c_addi16sp): Updated encoding macros.
 487         (match_c_lui): Likewise.
 488         (match_c_lui_with_hint): Likewise.
 489         (match_c_addi4spn): Likewise.
 490         (match_c_slli): Likewise.
 491         (match_slli_as_c_slli): Likewise.
 492         (match_c_slli64): Likewise.
 493         (match_srxi_as_c_srxi): Likewise.
 494         (riscv_insn_types): Added .insn css/cl/cs.
 495
 496 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 497
 498         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 499         (default_priv_spec): Updated type to riscv_spec_class.
 500         (parse_riscv_dis_option): Updated.
 501         * riscv-opc.c: Moved stuff and make the file tidy.
 502
 503 2021-02-17  Alan Modra  <amodra@gmail.com>
 504
 505         * wasm32-dis.c: Include limits.h.
 506         (CHAR_BIT): Provide backup define.
 507         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 508         Correct signed overflow checking.
 509
 510 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 511
 512         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 513         * i386-tbl.h: Re-generate.
 514
 515 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 516
 517         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 518         Oword.
 519         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 520
 521 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 522
 523         * s390-mkopc.c (main): Accept arch14 as cpu string.
 524         * s390-opc.txt: Add new arch14 instructions.
 525
 526 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 527
 528         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 529         favour of LIBINTL.
 530         * configure: Regenerated.
 531
 532 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 533
 534         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 535         * tic54x-opc.c (regs): Rename to ...
 536         (tic54x_regs): ... this.
 537         (mmregs): Rename to ...
 538         (tic54x_mmregs): ... this.
 539         (condition_codes): Rename to ...
 540         (tic54x_condition_codes): ... this.
 541         (cc2_codes): Rename to ...
 542         (tic54x_cc2_codes): ... this.
 543         (cc3_codes): Rename to ...
 544         (tic54x_cc3_codes): ... this.
 545         (status_bits): Rename to ...
 546         (tic54x_status_bits): ... this.
 547         (misc_symbols): Rename to ...
 548         (tic54x_misc_symbols): ... this.
 549
 550 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
 551
 552         * riscv-opc.c (MASK_RVB_IMM): Removed.
 553         (riscv_opcodes): Removed zb* instructions.
 554         (riscv_ext_version_table): Removed versions for zb*.
 555
 556 2021-01-26  Alan Modra  <amodra@gmail.com>
 557
 558         * i386-gen.c (parse_template): Ensure entire template_instance
 559         is initialised.
 560
 561 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 562
 563         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
 564         (riscv_fpr_names_abi): Likewise.
 565         (riscv_opcodes): Likewise.
 566         (riscv_insn_types): Likewise.
 567
 568 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 569
 570         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 571
 572 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 573
 574         * riscv-dis.c: Comments tidy and improvement.
 575         * riscv-opc.c: Likewise.
 576
 577 2021-01-13  Alan Modra  <amodra@gmail.com>
 578
 579         * Makefile.in: Regenerate.
 580
 581 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 582
 583         PR binutils/26792
 584         * configure.ac: Use GNU_MAKE_JOBSERVER.
 585         * aclocal.m4: Regenerated.
 586         * configure: Likewise.
 587
 588 2021-01-12  Nick Clifton  <nickc@redhat.com>
 589
 590         * po/sr.po: Updated Serbian translation.
 591
 592 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
 593
 594         PR ld/27173
 595         * configure: Regenerated.
 596
 597 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 598
 599         * aarch64-asm-2.c: Regenerate.
 600         * aarch64-dis-2.c: Likewise.
 601         * aarch64-opc-2.c: Likewise.
 602         * aarch64-opc.c (aarch64_print_operand):
 603         Delete handling of AARCH64_OPND_CSRE_CSR.
 604         * aarch64-tbl.h (aarch64_feature_csre): Delete.
 605         (CSRE): Likewise.
 606         (_CSRE_INSN): Likewise.
 607         (aarch64_opcode_table): Delete csr.
 608
 609 2021-01-11  Nick Clifton  <nickc@redhat.com>
 610
 611         * po/de.po: Updated German translation.
 612         * po/fr.po: Updated French translation.
 613         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 614         * po/sv.po: Updated Swedish translation.
 615         * po/uk.po: Updated Ukranian translation.
 616
 617 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
 618
 619         * configure: Regenerated.
 620
 621 2021-01-09  Nick Clifton  <nickc@redhat.com>
 622
 623         * configure: Regenerate.
 624         * po/opcodes.pot: Regenerate.
 625
 626 2021-01-09  Nick Clifton  <nickc@redhat.com>
 627
 628         * 2.36 release branch crated.
 629
 630 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
 631
 632         * ppc-opc.c (insert_dw, (extract_dw): New functions.
 633         (DW, (XRC_MASK): Define.
 634         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
 635
 636 2021-01-09  Alan Modra  <amodra@gmail.com>
 637
 638         * configure: Regenerate.
 639
 640 2021-01-08  Nick Clifton  <nickc@redhat.com>
 641
 642         * po/sv.po: Updated Swedish translation.
 643
 644 2021-01-08  Nick Clifton  <nickc@redhat.com>
 645
 646         PR 27129
 647         * aarch64-dis.c (determine_disassembling_preference): Move call to
 648         aarch64_match_operands_constraint outside of the assertion.
 649         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
 650         Replace with a return of FALSE.
 651
 652         PR 27139
 653         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
 654         core system register.
 655
 656 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
 657
 658         * configure: Regenerate.
 659
 660 2021-01-07  Nick Clifton  <nickc@redhat.com>
 661
 662         * po/fr.po: Updated French translation.
 663
 664 2021-01-07  Fredrik Noring  <noring@nocrew.org>
 665
 666         * m68k-opc.c (chkl): Change minimum architecture requirement to
 667         m68020.
 668
 669 2021-01-07  Philipp Tomsich  <prt@gnu.org>
 670
 671         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
 672
 673 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
 674             Jim Wilson  <jimw@sifive.com>
 675             Andrew Waterman  <andrew@sifive.com>
 676             Maxim Blinov  <maxim.blinov@embecosm.com>
 677             Kito Cheng  <kito.cheng@sifive.com>
 678             Nelson Chu  <nelson.chu@sifive.com>
 679
 680         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
 681         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
 682
 683 2021-01-01  Alan Modra  <amodra@gmail.com>
 684
 685         Update year range in copyright notice of all files.
 686
 687 For older changes see ChangeLog-2020
 688 \f
 689 Copyright (C) 2021 Free Software Foundation, Inc.
 690
 691 Copying and distribution of this file, with or without modification,
 692 are permitted in any medium without royalty provided the copyright
 693 notice and this notice are preserved.
 694
 695 Local Variables:
 696 mode: change-log
 697 left-margin: 8
 698 fill-column: 74
 699 version-control: never
 700 End: