opcodes/ChangeLog

   1 2019-10-28  Nick Clifton  <nickc@redhat.com>
   2
   3         * csky-dis.c (csky_chars_to_number): Check for a negative
   4         count. Use an unsigned integer to construct the return value.
   5
   6 2019-10-28  Nick Clifton  <nickc@redhat.com>
   7
   8         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
   9         operand buffer.  Set value to 15 not 13.
  10         (get_register_operand): Use OPERAND_BUFFER_LEN.
  11         (get_indirect_operand): Likewise.
  12         (print_two_operand): Likewise.
  13         (print_three_operand): Likewise.
  14         (print_oar_insn): Likewise.
  15
  16 2019-10-28  Nick Clifton  <nickc@redhat.com>
  17
  18         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
  19         (bit_extract_simple): Likewise.
  20         (bit_copy): Likewise.
  21         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
  22         index_offset array are not accessed.
  23
  24 2019-10-28  Nick Clifton  <nickc@redhat.com>
  25
  26         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
  27         operand.
  28
  29 2019-10-25  Nick Clifton  <nickc@redhat.com>
  30
  31         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
  32         access to opcodes.op array element.
  33
  34 2019-10-23  Nick Clifton  <nickc@redhat.com>
  35
  36         * rx-dis.c (get_register_name): Fix spelling typo in error
  37         message.
  38         (get_condition_name, get_flag_name, get_double_register_name)
  39         (get_double_register_high_name, get_double_register_low_name)
  40         (get_double_control_register_name, get_double_condition_name)
  41         (get_opsize_name, get_size_name): Likewise.
  42
  43 2019-10-22  Nick Clifton  <nickc@redhat.com>
  44
  45         * rx-dis.c (get_size_name): New function.  Provides safe
  46         access to name array.
  47         (get_opsize_name): Likewise.
  48         (print_insn_rx): Use the accessor functions.
  49
  50 2019-10-16  Nick Clifton  <nickc@redhat.com>
  51
  52         * rx-dis.c (get_register_name): New function.  Provides safe
  53         access to name array.
  54         (get_condition_name, get_flag_name, get_double_register_name)
  55         (get_double_register_high_name, get_double_register_low_name)
  56         (get_double_control_register_name, get_double_condition_name):
  57         Likewise.
  58         (print_insn_rx): Use the accessor functions.
  59
  60 2019-10-09  Nick Clifton  <nickc@redhat.com>
  61
  62         PR 25041
  63         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
  64         instructions.
  65
  66 2019-10-07  Jan Beulich  <jbeulich@suse.com>
  67
  68         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
  69         (cmpsd): Likewise. Move EsSeg to other operand.
  70         * opcodes/i386-tbl.h: Re-generate.
  71
  72 2019-09-23  Alan Modra  <amodra@gmail.com>
  73
  74         * m68k-dis.c: Include cpu-m68k.h
  75
  76 2019-09-23  Alan Modra  <amodra@gmail.com>
  77
  78         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
  79         "elf/mips.h" earlier.
  80
  81 2018-09-20  Jan Beulich  <jbeulich@suse.com>
  82
  83         PR gas/25012
  84         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
  85         with SReg operand.
  86         * i386-tbl.h: Re-generate.
  87
  88 2019-09-18  Alan Modra  <amodra@gmail.com>
  89
  90         * arc-ext.c: Update throughout for bfd section macro changes.
  91
  92 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
  93
  94         * Makefile.in: Re-generate.
  95         * configure: Re-generate.
  96
  97 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
  98
  99         * riscv-opc.c (riscv_opcodes): Change subset field
 100         to insn_class field for all instructions.
 101         (riscv_insn_types): Likewise.
 102
 103 2019-09-16  Phil Blundell  <pb@pbcl.net>
 104
 105         * configure: Regenerated.
 106
 107 2019-09-10  Miod Vallat  <miod@online.fr>
 108
 109         PR 24982
 110         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 111
 112 2019-09-09  Phil Blundell  <pb@pbcl.net>
 113
 114         binutils 2.33 branch created.
 115
 116 2019-09-03  Nick Clifton  <nickc@redhat.com>
 117
 118         PR 24961
 119         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 120         greater than zero before indexing via (bufcnt -1).
 121
 122 2019-09-03  Nick Clifton  <nickc@redhat.com>
 123
 124         PR 24958
 125         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 126         (MAX_SPEC_REG_NAME_LEN): Define.
 127         (struct mmix_dis_info): Use defined constants for array lengths.
 128         (get_reg_name): New function.
 129         (get_sprec_reg_name): New function.
 130         (print_insn_mmix): Use new functions.
 131
 132 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 133
 134         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 135         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 136         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 137
 138 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 139
 140         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 141         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 142         (aarch64_sys_reg_supported_p): Update checks for the above.
 143
 144 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 145
 146         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 147         cases MVE_SQRSHRL and MVE_UQRSHLL.
 148         (print_insn_mve): Add case for specifier 'k' to check
 149         specific bit of the instruction.
 150
 151 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 152
 153         PR 24854
 154         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 155         encountering an unknown machine type.
 156         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 157         cases return -1 rather than calling abort.
 158
 159 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 160
 161         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 162         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 163         IgnoreSize.
 164         * i386-tbl.h: Re-generate.
 165
 166 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 167
 168         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 169         instructions.
 170
 171 2019-07-30  Mel Chen <mel.chen@sifive.com>
 172
 173         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 174         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 175
 176         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 177         fscsr.
 178
 179 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 180
 181         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 182         and MPY class instructions.
 183         (parse_option): Add nps400 option.
 184         (print_arc_disassembler_options): Add nps400 info.
 185
 186 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 187
 188         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 189         (bspop): Likewise.
 190         (modapp): Likewise.
 191         * arc-opc.c (RAD_CHK): Add.
 192         * arc-tbl.h: Regenerate.
 193
 194 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 195
 196         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 197         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 198
 199 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 200
 201         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 202         instructions as UNPREDICTABLE.
 203
 204 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 205
 206         * bpf-desc.c: Regenerated.
 207
 208 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 209
 210         * i386-gen.c (static_assert): Define.
 211         (main): Use it.
 212         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 213         (Opcode_Modifier_Num): ... this.
 214         (Mem): Delete.
 215
 216 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 217
 218         * i386-gen.c (operand_types): Move RegMem ...
 219         (opcode_modifiers): ... here.
 220         * i386-opc.h (RegMem): Move to opcode modifer enum.
 221         (union i386_operand_type): Move regmem field ...
 222         (struct i386_opcode_modifier): ... here.
 223         * i386-opc.tbl (RegMem): Define.
 224         (mov, movq): Move RegMem on segment, control, debug, and test
 225         register flavors.
 226         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 227         to non-SSE2AVX flavor.
 228         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 229         Move RegMem on register only flavors. Drop IgnoreSize from
 230         legacy encoding flavors.
 231         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 232         flavors.
 233         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 234         register only flavors.
 235         (vmovd): Move RegMem and drop IgnoreSize on register only
 236         flavor. Change opcode and operand order to store form.
 237         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 238
 239 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 240
 241         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 242         entries.
 243         * i386-opc.h (SReg2, SReg3): Replace by ...
 244         (SReg): ... this.
 245         (union i386_operand_type): Replace sreg fields.
 246         * i386-opc.tbl (mov, ): Use SReg.
 247         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 248         register flavors.
 249         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 250         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 251
 252 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 253
 254         * bpf-desc.c: Regenerate.
 255         * bpf-opc.c: Likewise.
 256         * bpf-opc.h: Likewise.
 257
 258 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 259
 260         * bpf-desc.c: Regenerate.
 261         * bpf-opc.c: Likewise.
 262
 263 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 264
 265         * arm-dis.c (print_insn_coprocessor): Rename index to
 266         index_operand.
 267
 268 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 269
 270         * riscv-opc.c (riscv_insn_types): Add r4 type.
 271
 272         * riscv-opc.c (riscv_insn_types): Add b and j type.
 273
 274         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 275         format for sb type and correct s type.
 276
 277 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 278
 279         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 280         SVE FMOV alias of FCPY.
 281
 282 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 283
 284         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 285         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 286
 287 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 288
 289         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 290         registers in an instruction prefixed by MOVPRFX.
 291
 292 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 293
 294         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 295         sve_size_13 icode to account for variant behaviour of
 296         pmull{t,b}.
 297         * aarch64-dis-2.c: Regenerate.
 298         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 299         sve_size_13 icode to account for variant behaviour of
 300         pmull{t,b}.
 301         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 302         (OP_SVE_VVV_Q_D): Add new qualifier.
 303         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 304         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 305         AES and those not.
 306
 307 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 308
 309         * opcodes/i386-gen.c (operand_type_init): Remove
 310         OPERAND_TYPE_VEC_IMM4 entry.
 311         (operand_types): Remove Vec_Imm4.
 312         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 313         (union i386_operand_type): Remove vec_imm4.
 314         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 315         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 316
 317 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 318
 319         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 320         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 321         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 322         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 323         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 324         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 325         * i386-tbl.h: Re-generate.
 326
 327 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 328
 329         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 330         register operands.
 331         * i386-tbl.h: Re-generate.
 332
 333 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 334
 335         * i386-opc.tbl (C): New.
 336         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 337         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 338         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 339         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 340         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 341         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 342         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 343         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 344         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 345         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 346         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 347         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 348         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 349         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 350         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 351         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 352         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 353         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 354         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 355         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 356         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 357         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 358         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 359         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 360         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 361         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 362         flavors.
 363         * i386-tbl.h: Re-generate.
 364
 365 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 366
 367         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 368         register operands.
 369         * i386-tbl.h: Re-generate.
 370
 371 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 372
 373         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 374         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 375         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 376         * i386-tbl.h: Re-generate.
 377
 378 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 379
 380         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 381         Disp8MemShift from register only templates.
 382         * i386-tbl.h: Re-generate.
 383
 384 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 385
 386         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 387         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 388         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 389         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 390         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 391         EVEX_W_0F11_P_3_M_1): Delete.
 392         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 393         EVEX_W_0F11_P_3): New.
 394         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 395         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 396         MOD_EVEX_0F11_PREFIX_3 table entries.
 397         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 398         PREFIX_EVEX_0F11 table entries.
 399         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 400         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 401         EVEX_W_0F11_P_3_M_{0,1} table entries.
 402
 403 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 404
 405         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 406         Delete.
 407
 408 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 409
 410         PR binutils/24719
 411         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 412         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 413         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 414         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 415         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 416         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 417         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 418         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 419         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 420         PREFIX_EVEX_0F38C6_REG_6 entries.
 421         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 422         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 423         EVEX_W_0F38C7_R_6_P_2 entries.
 424         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 425         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 426         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 427         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 428         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 429         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 430         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 431
 432 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 433
 434         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 435         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 436         VEX_LEN_0F2D_P_3): Delete.
 437         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 438         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 439         (prefix_table): ... here.
 440
 441 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 442
 443         * i386-dis.c (Iq): Delete.
 444         (Id): New.
 445         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 446         TBM insns.
 447         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 448         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 449         (OP_E_memory): Also honor needindex when deciding whether an
 450         address size prefix needs printing.
 451         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 452
 453 2019-06-26  Jim Wilson  <jimw@sifive.com>
 454
 455         PR binutils/24739
 456         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 457         Set info->display_endian to info->endian_code.
 458
 459 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 460
 461         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 462         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 463         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 464         OPERAND_TYPE_ACC64 entries.
 465         * i386-init.h: Re-generate.
 466
 467 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 468
 469         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 470         Delete.
 471         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 472         of dqa_mode.
 473         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 474         entries here.
 475         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 476         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 477
 478 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 479
 480         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 481         variables.
 482
 483 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 484
 485         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 486         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 487         movnti.
 488         * i386-opc.tbl (movnti): Add IgnoreSize.
 489         * i386-tbl.h: Re-generate.
 490
 491 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 492
 493         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 494         * i386-tbl.h: Re-generate.
 495
 496 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 497
 498         * i386-dis-evex.h: Break into ...
 499         * i386-dis-evex-len.h: New file.
 500         * i386-dis-evex-mod.h: Likewise.
 501         * i386-dis-evex-prefix.h: Likewise.
 502         * i386-dis-evex-reg.h: Likewise.
 503         * i386-dis-evex-w.h: Likewise.
 504         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 505         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 506         i386-dis-evex-mod.h.
 507
 508 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 509
 510         PR binutils/24700
 511         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 512         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 513         EVEX_W_0F385B_P_2.
 514         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 515         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 516         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 517         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 518         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 519         EVEX_LEN_0F385B_P_2_W_1.
 520         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 521         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 522         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 523         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 524         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 525         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 526         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 527         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 528         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 529         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 530
 531 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 532
 533         PR binutils/24691
 534         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 535         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 536         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 537         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 538         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 539         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 540         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 541         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 542         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 543         EVEX_LEN_0F3A43_P_2_W_1.
 544         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 545         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 546         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 547         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 548         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 549         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 550         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 551         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 552         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 553         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 554         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 555         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 556
 557 2019-06-14  Nick Clifton  <nickc@redhat.com>
 558
 559         * po/fr.po; Updated French translation.
 560
 561 2019-06-13  Stafford Horne  <shorne@gmail.com>
 562
 563         * or1k-asm.c: Regenerated.
 564         * or1k-desc.c: Regenerated.
 565         * or1k-desc.h: Regenerated.
 566         * or1k-dis.c: Regenerated.
 567         * or1k-ibld.c: Regenerated.
 568         * or1k-opc.c: Regenerated.
 569         * or1k-opc.h: Regenerated.
 570         * or1k-opinst.c: Regenerated.
 571
 572 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 573
 574         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 575
 576 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 577
 578         PR binutils/24633
 579         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 580         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 581         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 582         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 583         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 584         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 585         EVEX_LEN_0F3A1B_P_2_W_1.
 586         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 587         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 588         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 589         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 590         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 591         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 592         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 593         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 594
 595 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 596
 597         PR binutils/24626
 598         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 599         EVEX.vvvv when disassembling VEX and EVEX instructions.
 600         (OP_VEX): Set vex.register_specifier to 0 after readding
 601         vex.register_specifier.
 602         (OP_Vex_2src_1): Likewise.
 603         (OP_Vex_2src_2): Likewise.
 604         (OP_LWP_E): Likewise.
 605         (OP_EX_Vex): Don't check vex.register_specifier.
 606         (OP_XMM_Vex): Likewise.
 607
 608 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 609             Lili Cui  <lili.cui@intel.com>
 610
 611         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 612         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 613         instructions.
 614         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 615         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 616         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 617         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 618         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 619         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 620         * i386-init.h: Regenerated.
 621         * i386-tbl.h: Likewise.
 622
 623 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 624             Lili Cui  <lili.cui@intel.com>
 625
 626         * doc/c-i386.texi: Document enqcmd.
 627         * testsuite/gas/i386/enqcmd-intel.d: New file.
 628         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 629         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 630         * testsuite/gas/i386/enqcmd.d: Likewise.
 631         * testsuite/gas/i386/enqcmd.s: Likewise.
 632         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 633         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 634         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 635         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 636         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 637         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 638         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 639         and x86-64-enqcmd.
 640
 641 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 642
 643         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 644
 645 2019-06-03  Alan Modra  <amodra@gmail.com>
 646
 647         * ppc-dis.c (prefix_opcd_indices): Correct size.
 648
 649 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 650
 651         PR gas/24625
 652         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 653         Disp8ShiftVL.
 654         * i386-tbl.h: Regenerated.
 655
 656 2019-05-24  Alan Modra  <amodra@gmail.com>
 657
 658         * po/POTFILES.in: Regenerate.
 659
 660 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 661             Alan Modra  <amodra@gmail.com>
 662
 663         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 664         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 665         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 666         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 667         XTOP>): Define and add entries.
 668         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 669         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 670         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 671         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 672
 673 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 674             Alan Modra  <amodra@gmail.com>
 675
 676         * ppc-dis.c (ppc_opts): Add "future" entry.
 677         (PREFIX_OPCD_SEGS): Define.
 678         (prefix_opcd_indices): New array.
 679         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 680         (lookup_prefix): New function.
 681         (print_insn_powerpc): Handle 64-bit prefix instructions.
 682         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 683         (PMRR, POWERXX): Define.
 684         (prefix_opcodes): New instruction table.
 685         (prefix_num_opcodes): New constant.
 686
 687 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 688
 689         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 690         * configure: Regenerated.
 691         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 692         and cpu/bpf.opc.
 693         (HFILES): Add bpf-desc.h and bpf-opc.h.
 694         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 695         bpf-ibld.c and bpf-opc.c.
 696         (BPF_DEPS): Define.
 697         * Makefile.in: Regenerated.
 698         * disassemble.c (ARCH_bpf): Define.
 699         (disassembler): Add case for bfd_arch_bpf.
 700         (disassemble_init_for_target): Likewise.
 701         (enum epbf_isa_attr): Define.
 702         * disassemble.h: extern print_insn_bpf.
 703         * bpf-asm.c: Generated.
 704         * bpf-opc.h: Likewise.
 705         * bpf-opc.c: Likewise.
 706         * bpf-ibld.c: Likewise.
 707         * bpf-dis.c: Likewise.
 708         * bpf-desc.h: Likewise.
 709         * bpf-desc.c: Likewise.
 710
 711 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 712
 713         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 714         and VMSR with the new operands.
 715
 716 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 717
 718         * arm-dis.c (enum mve_instructions): New enum
 719         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 720         and cneg.
 721         (mve_opcodes): New instructions as above.
 722         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 723         csneg and csel.
 724         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 725
 726 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 727
 728         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 729         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 730         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 731         uqshl, urshrl and urshr.
 732         (is_mve_okay_in_it): Add new instructions to TRUE list.
 733         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 734         (print_insn_mve): Updated to accept new %j,
 735         %<bitfield>m and %<bitfield>n patterns.
 736
 737 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 738
 739         * mips-opc.c (mips_builtin_opcodes): Change source register
 740         constraint for DAUI.
 741
 742 2019-05-20  Nick Clifton  <nickc@redhat.com>
 743
 744         * po/fr.po: Updated French translation.
 745
 746 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 747             Michael Collison <michael.collison@arm.com>
 748
 749         * arm-dis.c (thumb32_opcodes): Add new instructions.
 750         (enum mve_instructions): Likewise.
 751         (enum mve_undefined): Add new reasons.
 752         (is_mve_encoding_conflict): Handle new instructions.
 753         (is_mve_undefined): Likewise.
 754         (is_mve_unpredictable): Likewise.
 755         (print_mve_undefined): Likewise.
 756         (print_mve_size): Likewise.
 757
 758 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 759             Michael Collison <michael.collison@arm.com>
 760
 761         * arm-dis.c (thumb32_opcodes): Add new instructions.
 762         (enum mve_instructions): Likewise.
 763         (is_mve_encoding_conflict): Handle new instructions.
 764         (is_mve_undefined): Likewise.
 765         (is_mve_unpredictable): Likewise.
 766         (print_mve_size): Likewise.
 767
 768 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 769             Michael Collison <michael.collison@arm.com>
 770
 771         * arm-dis.c (thumb32_opcodes): Add new instructions.
 772         (enum mve_instructions): Likewise.
 773         (is_mve_encoding_conflict): Likewise.
 774         (is_mve_unpredictable): Likewise.
 775         (print_mve_size): Likewise.
 776
 777 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 778             Michael Collison <michael.collison@arm.com>
 779
 780         * arm-dis.c (thumb32_opcodes): Add new instructions.
 781         (enum mve_instructions): Likewise.
 782         (is_mve_encoding_conflict): Handle new instructions.
 783         (is_mve_undefined): Likewise.
 784         (is_mve_unpredictable): Likewise.
 785         (print_mve_size): Likewise.
 786
 787 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 788             Michael Collison <michael.collison@arm.com>
 789
 790         * arm-dis.c (thumb32_opcodes): Add new instructions.
 791         (enum mve_instructions): Likewise.
 792         (is_mve_encoding_conflict): Handle new instructions.
 793         (is_mve_undefined): Likewise.
 794         (is_mve_unpredictable): Likewise.
 795         (print_mve_size): Likewise.
 796         (print_insn_mve): Likewise.
 797
 798 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 799             Michael Collison <michael.collison@arm.com>
 800
 801         * arm-dis.c (thumb32_opcodes): Add new instructions.
 802         (print_insn_thumb32): Handle new instructions.
 803
 804 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 805             Michael Collison <michael.collison@arm.com>
 806
 807         * arm-dis.c (enum mve_instructions): Add new instructions.
 808         (enum mve_undefined): Add new reasons.
 809         (is_mve_encoding_conflict): Handle new instructions.
 810         (is_mve_undefined): Likewise.
 811         (is_mve_unpredictable): Likewise.
 812         (print_mve_undefined): Likewise.
 813         (print_mve_size): Likewise.
 814         (print_mve_shift_n): Likewise.
 815         (print_insn_mve): Likewise.
 816
 817 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 818             Michael Collison <michael.collison@arm.com>
 819
 820         * arm-dis.c (enum mve_instructions): Add new instructions.
 821         (is_mve_encoding_conflict): Handle new instructions.
 822         (is_mve_unpredictable): Likewise.
 823         (print_mve_rotate): Likewise.
 824         (print_mve_size): Likewise.
 825         (print_insn_mve): Likewise.
 826
 827 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 828             Michael Collison <michael.collison@arm.com>
 829
 830         * arm-dis.c (enum mve_instructions): Add new instructions.
 831         (is_mve_encoding_conflict): Handle new instructions.
 832         (is_mve_unpredictable): Likewise.
 833         (print_mve_size): Likewise.
 834         (print_insn_mve): Likewise.
 835
 836 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 837             Michael Collison <michael.collison@arm.com>
 838
 839         * arm-dis.c (enum mve_instructions): Add new instructions.
 840         (enum mve_undefined): Add new reasons.
 841         (is_mve_encoding_conflict): Handle new instructions.
 842         (is_mve_undefined): Likewise.
 843         (is_mve_unpredictable): Likewise.
 844         (print_mve_undefined): Likewise.
 845         (print_mve_size): Likewise.
 846         (print_insn_mve): Likewise.
 847
 848 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 849             Michael Collison <michael.collison@arm.com>
 850
 851         * arm-dis.c (enum mve_instructions): Add new instructions.
 852         (is_mve_encoding_conflict): Handle new instructions.
 853         (is_mve_undefined): Likewise.
 854         (is_mve_unpredictable): Likewise.
 855         (print_mve_size): Likewise.
 856         (print_insn_mve): Likewise.
 857
 858 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 859             Michael Collison <michael.collison@arm.com>
 860
 861         * arm-dis.c (enum mve_instructions): Add new instructions.
 862         (enum mve_unpredictable): Add new reasons.
 863         (enum mve_undefined): Likewise.
 864         (is_mve_okay_in_it): Handle new isntructions.
 865         (is_mve_encoding_conflict): Likewise.
 866         (is_mve_undefined): Likewise.
 867         (is_mve_unpredictable): Likewise.
 868         (print_mve_vmov_index): Likewise.
 869         (print_simd_imm8): Likewise.
 870         (print_mve_undefined): Likewise.
 871         (print_mve_unpredictable): Likewise.
 872         (print_mve_size): Likewise.
 873         (print_insn_mve): Likewise.
 874
 875 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 876             Michael Collison <michael.collison@arm.com>
 877
 878         * arm-dis.c (enum mve_instructions): Add new instructions.
 879         (enum mve_unpredictable): Add new reasons.
 880         (enum mve_undefined): Likewise.
 881         (is_mve_encoding_conflict): Handle new instructions.
 882         (is_mve_undefined): Likewise.
 883         (is_mve_unpredictable): Likewise.
 884         (print_mve_undefined): Likewise.
 885         (print_mve_unpredictable): Likewise.
 886         (print_mve_rounding_mode): Likewise.
 887         (print_mve_vcvt_size): Likewise.
 888         (print_mve_size): Likewise.
 889         (print_insn_mve): Likewise.
 890
 891 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 892             Michael Collison <michael.collison@arm.com>
 893
 894         * arm-dis.c (enum mve_instructions): Add new instructions.
 895         (enum mve_unpredictable): Add new reasons.
 896         (enum mve_undefined): Likewise.
 897         (is_mve_undefined): Handle new instructions.
 898         (is_mve_unpredictable): Likewise.
 899         (print_mve_undefined): Likewise.
 900         (print_mve_unpredictable): Likewise.
 901         (print_mve_size): Likewise.
 902         (print_insn_mve): Likewise.
 903
 904 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 905             Michael Collison <michael.collison@arm.com>
 906
 907         * arm-dis.c (enum mve_instructions): Add new instructions.
 908         (enum mve_undefined): Add new reasons.
 909         (insns): Add new instructions.
 910         (is_mve_encoding_conflict):
 911         (print_mve_vld_str_addr): New print function.
 912         (is_mve_undefined): Handle new instructions.
 913         (is_mve_unpredictable): Likewise.
 914         (print_mve_undefined): Likewise.
 915         (print_mve_size): Likewise.
 916         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 917         (print_insn_mve):  Handle new operands.
 918
 919 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 920             Michael Collison <michael.collison@arm.com>
 921
 922         * arm-dis.c (enum mve_instructions): Add new instructions.
 923         (enum mve_unpredictable): Add new reasons.
 924         (is_mve_encoding_conflict): Handle new instructions.
 925         (is_mve_unpredictable): Likewise.
 926         (mve_opcodes): Add new instructions.
 927         (print_mve_unpredictable): Handle new reasons.
 928         (print_mve_register_blocks): New print function.
 929         (print_mve_size): Handle new instructions.
 930         (print_insn_mve): Likewise.
 931
 932 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 933             Michael Collison <michael.collison@arm.com>
 934
 935         * arm-dis.c (enum mve_instructions): Add new instructions.
 936         (enum mve_unpredictable): Add new reasons.
 937         (enum mve_undefined): Likewise.
 938         (is_mve_encoding_conflict): Handle new instructions.
 939         (is_mve_undefined): Likewise.
 940         (is_mve_unpredictable): Likewise.
 941         (coprocessor_opcodes): Move NEON VDUP from here...
 942         (neon_opcodes): ... to here.
 943         (mve_opcodes): Add new instructions.
 944         (print_mve_undefined):  Handle new reasons.
 945         (print_mve_unpredictable): Likewise.
 946         (print_mve_size): Handle new instructions.
 947         (print_insn_neon): Handle vdup.
 948         (print_insn_mve): Handle new operands.
 949
 950 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 951             Michael Collison <michael.collison@arm.com>
 952
 953         * arm-dis.c (enum mve_instructions): Add new instructions.
 954         (enum mve_unpredictable): Add new values.
 955         (mve_opcodes): Add new instructions.
 956         (vec_condnames): New array with vector conditions.
 957         (mve_predicatenames): New array with predicate suffixes.
 958         (mve_vec_sizename): New array with vector sizes.
 959         (enum vpt_pred_state): New enum with vector predication states.
 960         (struct vpt_block): New struct type for vpt blocks.
 961         (vpt_block_state): Global struct to keep track of state.
 962         (mve_extract_pred_mask): New helper function.
 963         (num_instructions_vpt_block): Likewise.
 964         (mark_outside_vpt_block): Likewise.
 965         (mark_inside_vpt_block): Likewise.
 966         (invert_next_predicate_state): Likewise.
 967         (update_next_predicate_state): Likewise.
 968         (update_vpt_block_state): Likewise.
 969         (is_vpt_instruction): Likewise.
 970         (is_mve_encoding_conflict): Add entries for new instructions.
 971         (is_mve_unpredictable): Likewise.
 972         (print_mve_unpredictable): Handle new cases.
 973         (print_instruction_predicate): Likewise.
 974         (print_mve_size): New function.
 975         (print_vec_condition): New function.
 976         (print_insn_mve): Handle vpt blocks and new print operands.
 977
 978 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 979
 980         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 981         8, 14 and 15 for Armv8.1-M Mainline.
 982
 983 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 984             Michael Collison <michael.collison@arm.com>
 985
 986         * arm-dis.c (enum mve_instructions): New enum.
 987         (enum mve_unpredictable): Likewise.
 988         (enum mve_undefined): Likewise.
 989         (struct mopcode32): New struct.
 990         (is_mve_okay_in_it): New function.
 991         (is_mve_architecture): Likewise.
 992         (arm_decode_field): Likewise.
 993         (arm_decode_field_multiple): Likewise.
 994         (is_mve_encoding_conflict): Likewise.
 995         (is_mve_undefined): Likewise.
 996         (is_mve_unpredictable): Likewise.
 997         (print_mve_undefined): Likewise.
 998         (print_mve_unpredictable): Likewise.
 999         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1000         (print_insn_mve): New function.
1001         (print_insn_thumb32): Handle MVE architecture.
1002         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1003
1004 2019-05-10  Nick Clifton  <nickc@redhat.com>
1005
1006         PR 24538
1007         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1008         end of the table prematurely.
1009
1010 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1011
1012         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1013         macros for R6.
1014
1015 2019-05-11  Alan Modra  <amodra@gmail.com>
1016
1017         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1018         when -Mraw is in effect.
1019
1020 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1021
1022         * aarch64-dis-2.c: Regenerate.
1023         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1024         (OP_SVE_BBB): New variant set.
1025         (OP_SVE_DDDD): New variant set.
1026         (OP_SVE_HHH): New variant set.
1027         (OP_SVE_HHHU): New variant set.
1028         (OP_SVE_SSS): New variant set.
1029         (OP_SVE_SSSU): New variant set.
1030         (OP_SVE_SHH): New variant set.
1031         (OP_SVE_SBBU): New variant set.
1032         (OP_SVE_DSS): New variant set.
1033         (OP_SVE_DHHU): New variant set.
1034         (OP_SVE_VMV_HSD_BHS): New variant set.
1035         (OP_SVE_VVU_HSD_BHS): New variant set.
1036         (OP_SVE_VVVU_SD_BH): New variant set.
1037         (OP_SVE_VVVU_BHSD): New variant set.
1038         (OP_SVE_VVV_QHD_DBS): New variant set.
1039         (OP_SVE_VVV_HSD_BHS): New variant set.
1040         (OP_SVE_VVV_HSD_BHS2): New variant set.
1041         (OP_SVE_VVV_BHS_HSD): New variant set.
1042         (OP_SVE_VV_BHS_HSD): New variant set.
1043         (OP_SVE_VVV_SD): New variant set.
1044         (OP_SVE_VVU_BHS_HSD): New variant set.
1045         (OP_SVE_VZVV_SD): New variant set.
1046         (OP_SVE_VZVV_BH): New variant set.
1047         (OP_SVE_VZV_SD): New variant set.
1048         (aarch64_opcode_table): Add sve2 instructions.
1049
1050 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1051
1052         * aarch64-asm-2.c: Regenerated.
1053         * aarch64-dis-2.c: Regenerated.
1054         * aarch64-opc-2.c: Regenerated.
1055         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1056         for SVE_SHLIMM_UNPRED_22.
1057         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1058         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1059         operand.
1060
1061 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1062
1063         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1064         sve_size_tsz_bhs iclass encode.
1065         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1066         sve_size_tsz_bhs iclass decode.
1067
1068 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1069
1070         * aarch64-asm-2.c: Regenerated.
1071         * aarch64-dis-2.c: Regenerated.
1072         * aarch64-opc-2.c: Regenerated.
1073         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1074         for SVE_Zm4_11_INDEX.
1075         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1076         (fields): Handle SVE_i2h field.
1077         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1078         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1079
1080 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1081
1082         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1083         sve_shift_tsz_bhsd iclass encode.
1084         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1085         sve_shift_tsz_bhsd iclass decode.
1086
1087 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1088
1089         * aarch64-asm-2.c: Regenerated.
1090         * aarch64-dis-2.c: Regenerated.
1091         * aarch64-opc-2.c: Regenerated.
1092         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1093         (aarch64_encode_variant_using_iclass): Handle
1094         sve_shift_tsz_hsd iclass encode.
1095         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1096         sve_shift_tsz_hsd iclass decode.
1097         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1098         for SVE_SHRIMM_UNPRED_22.
1099         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1100         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1101         operand.
1102
1103 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1104
1105         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1106         sve_size_013 iclass encode.
1107         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1108         sve_size_013 iclass decode.
1109
1110 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1111
1112         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1113         sve_size_bh iclass encode.
1114         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1115         sve_size_bh iclass decode.
1116
1117 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1118
1119         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1120         sve_size_sd2 iclass encode.
1121         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1122         sve_size_sd2 iclass decode.
1123         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1124         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1125
1126 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1127
1128         * aarch64-asm-2.c: Regenerated.
1129         * aarch64-dis-2.c: Regenerated.
1130         * aarch64-opc-2.c: Regenerated.
1131         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1132         for SVE_ADDR_ZX.
1133         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1134         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1135
1136 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1137
1138         * aarch64-asm-2.c: Regenerated.
1139         * aarch64-dis-2.c: Regenerated.
1140         * aarch64-opc-2.c: Regenerated.
1141         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1142         for SVE_Zm3_11_INDEX.
1143         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1144         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1145         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1146         fields.
1147         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1148
1149 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1150
1151         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1152         sve_size_hsd2 iclass encode.
1153         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1154         sve_size_hsd2 iclass decode.
1155         * aarch64-opc.c (fields): Handle SVE_size field.
1156         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1157
1158 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1159
1160         * aarch64-asm-2.c: Regenerated.
1161         * aarch64-dis-2.c: Regenerated.
1162         * aarch64-opc-2.c: Regenerated.
1163         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1164         for SVE_IMM_ROT3.
1165         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1166         (fields): Handle SVE_rot3 field.
1167         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1168         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1169
1170 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1171
1172         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1173         instructions.
1174
1175 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1176
1177         * aarch64-tbl.h
1178         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1179         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1180         aarch64_feature_sve2bitperm): New feature sets.
1181         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1182         for feature set addresses.
1183         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1184         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1185
1186 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1187             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1188
1189         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1190         argument and set ASE_EVA_R6 appropriately.
1191         (set_default_mips_dis_options): Pass ISA to above.
1192         (parse_mips_dis_option): Likewise.
1193         * mips-opc.c (EVAR6): New macro.
1194         (mips_builtin_opcodes): Add llwpe, scwpe.
1195
1196 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1197
1198         * aarch64-asm-2.c: Regenerated.
1199         * aarch64-dis-2.c: Regenerated.
1200         * aarch64-opc-2.c: Regenerated.
1201         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1202         AARCH64_OPND_TME_UIMM16.
1203         (aarch64_print_operand): Likewise.
1204         * aarch64-tbl.h (QL_IMM_NIL): New.
1205         (TME): New.
1206         (_TME_INSN): New.
1207         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1208
1209 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1210
1211         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1212
1213 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1214             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1215
1216         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1217
1218 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1219
1220         * s12z-opc.h: Add extern "C" bracketing to help
1221         users who wish to use this interface in c++ code.
1222
1223 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1224
1225         * s12z-opc.c (bm_decode): Handle bit map operations with the
1226         "reserved0" mode.
1227
1228 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1229
1230         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1231         specifier.  Add entries for VLDR and VSTR of system registers.
1232         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1233         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1234         of %J and %K format specifier.
1235
1236 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1237
1238         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1239         Add new entries for VSCCLRM instruction.
1240         (print_insn_coprocessor): Handle new %C format control code.
1241
1242 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1243
1244         * arm-dis.c (enum isa): New enum.
1245         (struct sopcode32): New structure.
1246         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1247         set isa field of all current entries to ANY.
1248         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1249         Only match an entry if its isa field allows the current mode.
1250
1251 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1252
1253         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1254         CLRM.
1255         (print_insn_thumb32): Add logic to print %n CLRM register list.
1256
1257 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1258
1259         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1260         and %Q patterns.
1261
1262 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1263
1264         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1265         (print_insn_thumb32): Edit the switch case for %Z.
1266
1267 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1268
1269         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1270
1271 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1272
1273         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1274
1275 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1276
1277         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1278
1279 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1280
1281         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1282         Arm register with r13 and r15 unpredictable.
1283         (thumb32_opcodes): New instructions for bfx and bflx.
1284
1285 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1286
1287         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1288
1289 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1290
1291         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1292
1293 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1294
1295         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1296
1297 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1298
1299         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1300
1301 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1302
1303         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1304         "optr". ("operator" is a reserved word in c++).
1305
1306 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1307
1308         * aarch64-opc.c (aarch64_print_operand): Add case for
1309         AARCH64_OPND_Rt_SP.
1310         (verify_constraints): Likewise.
1311         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1312         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1313         to accept Rt|SP as first operand.
1314         (AARCH64_OPERANDS): Add new Rt_SP.
1315         * aarch64-asm-2.c: Regenerated.
1316         * aarch64-dis-2.c: Regenerated.
1317         * aarch64-opc-2.c: Regenerated.
1318
1319 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1320
1321         * aarch64-asm-2.c: Regenerated.
1322         * aarch64-dis-2.c: Likewise.
1323         * aarch64-opc-2.c: Likewise.
1324         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1325
1326 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1327
1328         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1329
1330 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1331
1332         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1333         * i386-init.h: Regenerated.
1334
1335 2019-04-07  Alan Modra  <amodra@gmail.com>
1336
1337         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1338         op_separator to control printing of spaces, comma and parens
1339         rather than need_comma, need_paren and spaces vars.
1340
1341 2019-04-07  Alan Modra  <amodra@gmail.com>
1342
1343         PR 24421
1344         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1345         (print_insn_neon, print_insn_arm): Likewise.
1346
1347 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1348
1349         * i386-dis-evex.h (evex_table): Updated to support BF16
1350         instructions.
1351         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1352         and EVEX_W_0F3872_P_3.
1353         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1354         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1355         * i386-opc.h (enum): Add CpuAVX512_BF16.
1356         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1357         * i386-opc.tbl: Add AVX512 BF16 instructions.
1358         * i386-init.h: Regenerated.
1359         * i386-tbl.h: Likewise.
1360
1361 2019-04-05  Alan Modra  <amodra@gmail.com>
1362
1363         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1364         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1365         to favour printing of "-" branch hint when using the "y" bit.
1366         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1367
1368 2019-04-05  Alan Modra  <amodra@gmail.com>
1369
1370         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1371         opcode until first operand is output.
1372
1373 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1374
1375         PR gas/24349
1376         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1377         (valid_bo_post_v2): Add support for 'at' branch hints.
1378         (insert_bo): Only error on branch on ctr.
1379         (get_bo_hint_mask): New function.
1380         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1381         for inserting 'at' branch hints.
1382         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1383         for extracting 'at' branch hints.
1384         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1385         (BOE): Delete operand.
1386         (BOM, BOP): New operands.
1387         (RM): Update value.
1388         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1389         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1390         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1391         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1392         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1393         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1394         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1395         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1396         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1397         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1398         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1399         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1400         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1401         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1402         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1403         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1404         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1405         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1406         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1407         bttarl+>: New extended mnemonics.
1408
1409 2019-03-28  Alan Modra  <amodra@gmail.com>
1410
1411         PR 24390
1412         * ppc-opc.c (BTF): Define.
1413         (powerpc_opcodes): Use for mtfsb*.
1414         * ppc-dis.c (print_insn_powerpc): Print fields with both
1415         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1416
1417 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1418
1419         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1420         (mapping_symbol_for_insn): Implement new algorithm.
1421         (print_insn): Remove duplicate code.
1422
1423 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1424
1425         * aarch64-dis.c (print_insn_aarch64):
1426         Implement override.
1427
1428 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1429
1430         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1431         order.
1432
1433 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1434
1435         * aarch64-dis.c (last_stop_offset): New.
1436         (print_insn_aarch64): Use stop_offset.
1437
1438 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1439
1440         PR gas/24359
1441         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1442         CPU_ANY_AVX2_FLAGS.
1443         * i386-init.h: Regenerated.
1444
1445 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1446
1447         PR gas/24348
1448         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1449         vmovdqu16, vmovdqu32 and vmovdqu64.
1450         * i386-tbl.h: Regenerated.
1451
1452 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1453
1454         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1455         from vstrszb, vstrszh, and vstrszf.
1456
1457 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1458
1459         * s390-opc.txt: Add instruction descriptions.
1460
1461 2019-02-08  Jim Wilson  <jimw@sifive.com>
1462
1463         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1464         <bne>: Likewise.
1465
1466 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1467
1468         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1469
1470 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1471
1472         PR binutils/23212
1473         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1474         * aarch64-opc.c (verify_elem_sd): New.
1475         (fields): Add FLD_sz entr.
1476         * aarch64-tbl.h (_SIMD_INSN): New.
1477         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1478         fmulx scalar and vector by element isns.
1479
1480 2019-02-07  Nick Clifton  <nickc@redhat.com>
1481
1482         * po/sv.po: Updated Swedish translation.
1483
1484 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1485
1486         * s390-mkopc.c (main): Accept arch13 as cpu string.
1487         * s390-opc.c: Add new instruction formats and instruction opcode
1488         masks.
1489         * s390-opc.txt: Add new arch13 instructions.
1490
1491 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1492
1493         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1494         (aarch64_opcode): Change encoding for stg, stzg
1495         st2g and st2zg.
1496         * aarch64-asm-2.c: Regenerated.
1497         * aarch64-dis-2.c: Regenerated.
1498         * aarch64-opc-2.c: Regenerated.
1499
1500 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1501
1502         * aarch64-asm-2.c: Regenerated.
1503         * aarch64-dis-2.c: Likewise.
1504         * aarch64-opc-2.c: Likewise.
1505         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1506
1507 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1508             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1509
1510         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1511         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1512         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1513         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1514         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1515         case for ldstgv_indexed.
1516         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1517         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1518         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1519         * aarch64-asm-2.c: Regenerated.
1520         * aarch64-dis-2.c: Regenerated.
1521         * aarch64-opc-2.c: Regenerated.
1522
1523 2019-01-23  Nick Clifton  <nickc@redhat.com>
1524
1525         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1526
1527 2019-01-21  Nick Clifton  <nickc@redhat.com>
1528
1529         * po/de.po: Updated German translation.
1530         * po/uk.po: Updated Ukranian translation.
1531
1532 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1533         * mips-dis.c (mips_arch_choices): Fix typo in
1534         gs464, gs464e and gs264e descriptors.
1535
1536 2019-01-19  Nick Clifton  <nickc@redhat.com>
1537
1538         * configure: Regenerate.
1539         * po/opcodes.pot: Regenerate.
1540
1541 2018-06-24  Nick Clifton  <nickc@redhat.com>
1542
1543         2.32 branch created.
1544
1545 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1546
1547         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1548         if it is null.
1549         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1550         zero.
1551
1552 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1553
1554         * configure: Regenerate.
1555
1556 2019-01-07  Alan Modra  <amodra@gmail.com>
1557
1558         * configure: Regenerate.
1559         * po/POTFILES.in: Regenerate.
1560
1561 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1562
1563         * s12z-opc.c: New file.
1564         * s12z-opc.h: New file.
1565         * s12z-dis.c: Removed all code not directly related to display
1566         of instructions.  Used the interface provided by the new files
1567         instead.
1568         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1569         * Makefile.in: Regenerate.
1570         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1571         * configure: Regenerate.
1572
1573 2019-01-01  Alan Modra  <amodra@gmail.com>
1574
1575         Update year range in copyright notice of all files.
1576
1577 For older changes see ChangeLog-2018
1578 \f
1579 Copyright (C) 2019 Free Software Foundation, Inc.
1580
1581 Copying and distribution of this file, with or without modification,
1582 are permitted in any medium without royalty provided the copyright
1583 notice and this notice are preserved.
1584
1585 Local Variables:
1586 mode: change-log
1587 left-margin: 8
1588 fill-column: 74
1589 version-control: never
1590 End: