opcodes/ChangeLog

   1 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
   2
   3         * aarch64-asm-2.c: Regenerate.
   4         * aarch64-dis-2.c: Regenerate.
   5         * aarch64-opc-2.c: Regenerate.
   6         * aarch64-tbl.h (QL_V3SAMEH): New.
   7         (aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
   8         fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
   9         fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
  10         fcmgt, facgt and fminp to the vector three same group.
  11
  12 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  13
  14         * aarch64-tbl.h (aarch64_feature_simd_f16): New.
  15         (SIMD_F16): New.
  16
  17 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  18
  19         * aarch64-opc.c (aarch64_sys_reg_supported_p): Add mistakenly
  20         removed statement.
  21         (aarch64_pstatefield_supported_p): Move feature checks for AT
  22         registers ..
  23         (aarch64_sys_ins_reg_supported_p): .. to here.
  24
  25 2015-12-12  Alan Modra  <amodra@gmail.com>
  26
  27         PR 19359
  28         * ppc-opc.c (insert_fxm): Remove "ignored" from error message.
  29         (powerpc_opcodes): Remove single-operand mfcr.
  30
  31 2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
  32
  33         * aarch64-asm.c (aarch64_ins_hint): New.
  34         * aarch64-asm.h (aarch64_ins_hint): Declare.
  35         * aarch64-dis.c (aarch64_ext_hint): New.
  36         * aarch64-dis.h (aarch64_ext_hint): Declare.
  37         * aarch64-opc-2.c: Regenerate.
  38         * aarch64-opc.c (aarch64_hint_options): New.
  39         * aarch64-tbl.h (AARCH64_OPERANDS): Fix typos.
  40
  41 2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
  42
  43         * aarch64-gen.c (find_alias_opcode): Set max_num_aliases to 16.
  44
  45 2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
  46
  47         * aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1,
  48         pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1,
  49         pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and
  50         pmscr_el2.
  51         (aarch64_sys_reg_supported_p): Add architecture feature tests for
  52         the new registers.
  53
  54 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
  55
  56         * aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".
  57         (aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register
  58         feature test for "s1e1rp" and "s1e1wp".
  59
  60 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
  61
  62         * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
  63         (aarch64_sys_ins_reg_supported_p): New.
  64
  65 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
  66
  67         * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
  68         with aarch64_sys_ins_reg_has_xt.
  69         (aarch64_ext_sysins_op): Likewise.
  70         * aarch64-opc.c (operand_general_constraint_met_p): Likewise.
  71         (F_HASXT): New.
  72         (aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
  73         (aarch64_sys_regs_dc): Likewise.
  74         (aarch64_sys_regs_at): Likewise.
  75         (aarch64_sys_regs_tlbi): Likewise.
  76         (aarch64_sys_ins_reg_has_xt): New.
  77
  78 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
  79
  80         * aarch64-opc.c (aarch64_sys_regs): Add "uao".
  81         (aarch64_sys_reg_supported_p): Add comment.  Add checks for "uao".
  82         (aarch64_pstatefields): Add "uao".
  83         (aarch64_pstatefield_supported_p): Add checks for "uao".
  84
  85 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
  86
  87         * aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
  88         "errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
  89         "erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
  90         (aarch64_sys_reg_supported_p): Add architecture feature tests for
  91         new registers.
  92
  93 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
  94
  95         * aarch64-asm-2.c: Regenerate.
  96         * aarch64-dis-2.c: Regenerate.
  97         * aarch64-tbl.h (aarch64_feature_ras): New.
  98         (RAS): New.
  99         (aarch64_opcode_table): Add "esb".
 100
 101 2015-12-09  H.J. Lu  <hongjiu.lu@intel.com>
 102
 103         * i386-dis.c (MOD_0F01_REG_5): New.
 104         (RM_0F01_REG_5): Likewise.
 105         (reg_table): Use MOD_0F01_REG_5.
 106         (mod_table): Add MOD_0F01_REG_5.
 107         (rm_table): Add RM_0F01_REG_5.
 108         * i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
 109         (cpu_flags): Add CpuOSPKE.
 110         * i386-opc.h (CpuOSPKE): New.
 111         (i386_cpu_flags): Add cpuospke.
 112         * i386-opc.tbl: Add rdpkru and wrpkru instructions.
 113         * i386-init.h: Regenerated.
 114         * i386-tbl.h: Likewise.
 115
 116 2015-12-07  DJ Delorie  <dj@redhat.com>
 117
 118         * rl78-decode.opc: Enable MULU for all ISAs.
 119         * rl78-decode.c: Regenerate.
 120
 121 2015-12-07  Alan Modra  <amodra@gmail.com>
 122
 123         * opcodes/ppc-opc.c (powerpc_opcodes): Sort power9 insns by
 124         major opcode/xop.
 125
 126 2015-12-04  Claudiu Zissulescu  <claziss@synopsys.com>
 127
 128         * arc-dis.c (special_flag_p): Match full mnemonic.
 129         * arc-opc.c (print_insn_arc): Check section size to read
 130         appropriate number of bytes. Fix printing.
 131         * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
 132         arguments.
 133
 134 2015-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 135
 136         * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
 137         <ldah>: ... to this.
 138
 139 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 140
 141         * aarch64-asm-2.c: Regenerate.
 142         * aarch64-dis-2.c: Regenerate.
 143         * aarch64-opc-2.c: Regenerate.
 144         * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New.
 145         (QL_INT2FP_H, QL_FP2INT_H): New.
 146         (QL_FP2_H, QL_FP3_H, QL_FP4_H): New
 147         (QL_DST_H): New.
 148         (QL_FCCMP_H): New.
 149         (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf,
 150         fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau,
 151         fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp,
 152         fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm,
 153         frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax,
 154         fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and
 155         fcsel.
 156
 157 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 158
 159         * aarch64-opc.c (half_conv_t): New.
 160         (expand_fp_imm): Replace is_dp flag with the parameter size to
 161         specify the number of bytes for the required expansion.  Treat
 162         a 16-bit expansion like a 32-bit expansion.  Add check for an
 163         unsupported size request.  Update comment.
 164         (aarch64_print_operand): Update to support 16-bit floating point
 165         values.  Update for changes to expand_fp_imm.
 166
 167 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 168
 169         * aarch64-tbl.h (aarch64_feature_fp_f16): New.
 170         (FP_F16): New.
 171
 172 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 173
 174         * aarch64-asm-2.c: Regenerate.
 175         * aarch64-dis-2.c: Regenerate.
 176         * aarch64-opc-2.c: Regenerate.
 177         * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
 178         "rev64".
 179
 180 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 181
 182         * aarch64-asm-2.c: Regenerate.
 183         * aarch64-asm.c (convert_bfc_to_bfm): New.
 184         (convert_to_real): Add case for OP_BFC.
 185         * aarch64-dis-2.c: Regenerate.
 186         * aarch64-dis.c: (convert_bfm_to_bfc): New.
 187         (convert_to_alias): Add case for OP_BFC.
 188         * aarch64-opc-2.c: Regenerate.
 189         * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
 190         to allow width operand in three-operand instructions.
 191         * aarch64-tbl.h (QL_BF1): New.
 192         (aarch64_feature_v8_2): New.
 193         (ARMV8_2): New.
 194         (aarch64_opcode_table): Add "bfc".
 195
 196 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 197
 198         * aarch64-asm-2.c: Regenerate.
 199         * aarch64-dis-2.c: Regenerate.
 200         * aarch64-dis.c: Weaken assert.
 201         * aarch64-gen.c: Include the instruction in the list of its
 202         possible aliases.
 203
 204 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 205
 206         * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
 207         (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
 208         feature test.
 209
 210 2015-11-23  Tristan Gingold  <gingold@adacore.com>
 211
 212         * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
 213
 214 2015-11-20  Matthew Wahab  <matthew.wahab@arm.com>
 215
 216         * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
 217         sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
 218         tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
 219         amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
 220         cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
 221         cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
 222         cnthv_ctl_el2, cnthv_cval_el2.
 223         (aarch64_sys_reg_supported_p): Update for the new system
 224         registers.
 225
 226 2015-11-20  Nick Clifton  <nickc@redhat.com>
 227
 228         PR binutils/19224
 229         * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
 230
 231 2015-11-20  Nick Clifton  <nickc@redhat.com>
 232
 233         * po/zh_CN.po: Updated simplified Chinese translation.
 234
 235 2015-11-19  Matthew Wahab  <matthew.wahab@arm.com>
 236
 237         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
 238         of MSR PAN immediate operand.
 239
 240 2015-11-16  Nick Clifton  <nickc@redhat.com>
 241
 242         * rx-dis.c (condition_names): Replace always and never with
 243         invalid, since the always/never conditions can never be legal.
 244
 245 2015-11-13  Tristan Gingold  <gingold@adacore.com>
 246
 247         * configure: Regenerate.
 248
 249 2015-11-11  Alan Modra  <amodra@gmail.com>
 250             Peter Bergner <bergner@vnet.ibm.com>
 251
 252         * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
 253         Add PPC_OPCODE_VSX3 to the vsx entry.
 254         (powerpc_init_dialect): Set default dialect to power9.
 255         * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
 256         insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
 257         extract_l1 insert_xtq6, extract_xtq6): New static functions.
 258         (insert_esync): Test for illegal L operand value.
 259         (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
 260         XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
 261         XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
 262         XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
 263         PPCVSX3): New defines.
 264         (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
 265         fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
 266         <mcrxr>: Use XBFRARB_MASK.
 267         <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
 268         bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
 269         cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
 270         cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
 271         lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
 272         lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
 273         modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
 274         rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
 275         stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
 276         subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
 277         vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
 278         vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
 279         vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
 280         vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
 281         vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
 282         vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
 283         vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
 284         xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
 285         xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
 286         xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
 287         xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
 288         xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
 289         xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
 290         xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
 291         xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
 292         xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
 293         xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
 294         xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
 295         xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
 296         xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
 297         <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
 298         <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
 299
 300 2015-11-02  Nick Clifton  <nickc@redhat.com>
 301
 302         * rx-decode.opc (rx_decode_opcode): Decode extra NOP
 303         instructions.
 304         * rx-decode.c: Regenerate.
 305
 306 2015-11-02  Nick Clifton  <nickc@redhat.com>
 307
 308         * rx-decode.opc (rx_disp): If the displacement is zero, set the
 309         type to RX_Operand_Zero_Indirect.
 310         * rx-decode.c: Regenerate.
 311         * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
 312
 313 2015-10-28  Yao Qi  <yao.qi@linaro.org>
 314
 315         * aarch64-dis.c (aarch64_decode_insn): Add one argument
 316         noaliases_p.  Update comments.  Pass noaliases_p rather than
 317         no_aliases to aarch64_opcode_decode.
 318         (print_insn_aarch64_word): Pass no_aliases to
 319         aarch64_decode_insn.
 320
 321 2015-10-27  Vinay  <Vinay.G@kpit.com>
 322
 323         PR binutils/19159
 324         * rl78-decode.opc (MOV): Added offset to DE register in index
 325         addressing mode.
 326         * rl78-decode.c: Regenerate.
 327
 328 2015-10-27  Vinay Kumar  <vinay.g@kpit.com>
 329
 330         PR binutils/19158
 331         * rl78-decode.opc: Add 's' print operator to instructions that
 332         access system registers.
 333         * rl78-decode.c: Regenerate.
 334         * rl78-dis.c (print_insn_rl78_common): Decode all system
 335         registers.
 336
 337 2015-10-27  Vinay Kumar  <vinay.g@kpit.com>
 338
 339         PR binutils/19157
 340         * rl78-decode.opc: Add 'a' print operator to mov instructions
 341         using stack pointer plus index addressing.
 342         * rl78-decode.c: Regenerate.
 343
 344 2015-10-14  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 345
 346         * s390-opc.c: Fix comment.
 347         * s390-opc.txt: Change instruction type for troo, trot, trto, and
 348         trtt to RRF_U0RER since the second parameter does not need to be a
 349         register pair.
 350
 351 2015-10-08  Nick Clifton  <nickc@redhat.com>
 352
 353         * arc-dis.c (print_insn_arc): Initiallise insn array.
 354
 355 2015-10-07  Yao Qi  <yao.qi@linaro.org>
 356
 357         * aarch64-dis.c (aarch64_ext_sysins_op): Access field
 358         'name' rather than 'template'.
 359         * aarch64-opc.c (aarch64_print_operand): Likewise.
 360
 361 2015-10-07  Claudiu Zissulescu <claziss@synopsys.com>
 362
 363         * arc-dis.c: Revamped file for ARC support
 364         * arc-dis.h: Likewise.
 365         * arc-ext.c: Likewise.
 366         * arc-ext.h: Likewise.
 367         * arc-opc.c: Likewise.
 368         * arc-fxi.h: New file.
 369         * arc-regs.h: Likewise.
 370         * arc-tbl.h: Likewise.
 371
 372 2015-10-02  Yao Qi  <yao.qi@linaro.org>
 373
 374         * aarch64-dis.c (disas_aarch64_insn): Remove static.  Change
 375         argument insn type to aarch64_insn.  Rename to ...
 376         (aarch64_decode_insn): ... it.
 377         (print_insn_aarch64_word): Caller updated.
 378
 379 2015-10-02  Yao Qi  <yao.qi@linaro.org>
 380
 381         * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
 382         (print_insn_aarch64_word): Caller updated.
 383
 384 2015-09-29  Dominik Vogt  <vogt@linux.vnet.ibm.com>
 385
 386         * s390-mkopc.c (main): Parse htm and vx flag.
 387         * s390-opc.txt: Mark instructions from the hardware transactional
 388         memory and vector facilities with the "htm"/"vx" flag.
 389
 390 2015-09-28  Nick Clifton  <nickc@redhat.com>
 391
 392         * po/de.po: Updated German translation.
 393
 394 2015-09-28  Tom Rix  <tom@bumblecow.com>
 395
 396         * ppc-opc.c (PPC500): Mark some opcodes as invalid
 397
 398 2015-09-23  Nick Clifton  <nickc@redhat.com>
 399
 400         * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
 401         function.
 402         * tic30-dis.c (print_branch): Likewise.
 403         * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
 404         value before left shifting.
 405         * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
 406         * hppa-dis.c (print_insn_hppa): Likewise.
 407         * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
 408         array.
 409         * msp430-dis.c (msp430_singleoperand): Likewise.
 410         (msp430_doubleoperand): Likewise.
 411         (print_insn_msp430): Likewise.
 412         * nds32-asm.c (parse_operand): Likewise.
 413         * sh-opc.h (MASK): Likewise.
 414         * v850-dis.c (get_operand_value): Likewise.
 415
 416 2015-09-22  Nick Clifton  <nickc@redhat.com>
 417
 418         * rx-decode.opc (bwl): Use RX_Bad_Size.
 419         (sbwl): Likewise.
 420         (ubwl): Likewise.  Rename to ubw.
 421         (uBWL): Rename to uBW.
 422         Replace all references to uBWL with uBW.
 423         * rx-decode.c: Regenerate.
 424         * rx-dis.c (size_names): Add entry for RX_Bad_Size.
 425         (opsize_names): Likewise.
 426         (print_insn_rx): Detect and report RX_Bad_Size.
 427
 428 2015-09-22  Anton Blanchard  <anton@samba.org>
 429
 430         * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
 431
 432 2015-08-25  Jose E. Marchesi  <jose.marchesi@oracle.com>
 433
 434         * sparc-dis.c (print_insn_sparc): Handle the privileged register
 435         %pmcdper.
 436
 437 2015-08-24  Jan Stancek  <jstancek@redhat.com>
 438
 439         * i386-dis.c (print_insn): Fix decoding of three byte operands.
 440
 441 2015-08-21  Alexander Fomin  <alexander.fomin@intel.com>
 442
 443         PR binutils/18257
 444         * i386-dis.c: Use MOD_TABLE for most of mask instructions.
 445         (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
 446         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 447         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 448         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 449         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 450         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 451         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 452         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 453         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 454         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 455         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 456         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 457         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 458         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 459         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 460         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 461         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 462         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 463         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 464         MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
 465         MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
 466         MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
 467         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 468         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 469         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 470         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 471         MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 472         MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 473         MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 474         MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
 475         (vex_w_table): Replace terminals with MOD_TABLE entries for
 476         most of mask instructions.
 477
 478 2015-08-17  Alan Modra  <amodra@gmail.com>
 479
 480         * cgen.sh: Trim trailing space from cgen output.
 481         * ia64-gen.c (print_dependency_table): Don't generate trailing space.
 482         (print_dis_table): Likewise.
 483         * opc2c.c (dump_lines): Likewise.
 484         (orig_filename): Warning fix.
 485         * ia64-asmtab.c: Regenerate.
 486
 487 2015-08-13  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 488
 489         * arm-dis.c (print_insn_arm): Disassembling for all targets V6
 490         and higher with ARM instruction set will now mark the 26-bit
 491         versions of teq,tst,cmn and cmp as UNPREDICTABLE.
 492         (arm_opcodes): Fix for unpredictable nop being recognized as a
 493         teq.
 494
 495 2015-08-12  Simon Dardis  <simon.dardis@imgtec.com>
 496
 497         * micromips-opc.c (micromips_opcodes): Re-order table so that move
 498         based on 'or' is first.
 499         * mips-opc.c (mips_builtin_opcodes): Ditto.
 500
 501 2015-08-11  Nick Clifton  <nickc@redhat.com>
 502
 503         PR 18800
 504         * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
 505         instruction.
 506
 507 2015-08-10  Robert Suchanek  <robert.suchanek@imgtec.com>
 508
 509         * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
 510
 511 2015-08-07  Amit Pawar <Amit.Pawar@amd.com>
 512
 513         * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
 514         * i386-init.h: Regenerated.
 515
 516 2015-07-30  H.J. Lu  <hongjiu.lu@intel.com>
 517
 518         PR binutils/13571
 519         * i386-dis.c (MOD_0FC3): New.
 520         (PREFIX_0FC3): Renamed to ...
 521         (PREFIX_MOD_0_0FC3): This.
 522         (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
 523         (prefix_table): Replace Ma with Ev on movntiS.
 524         (mod_table): Add MOD_0FC3.
 525
 526 2015-07-27  H.J. Lu  <hongjiu.lu@intel.com>
 527
 528         * configure: Regenerated.
 529
 530 2015-07-23  Alan Modra  <amodra@gmail.com>
 531
 532         PR 18708
 533         * i386-dis.c (get64): Avoid signed integer overflow.
 534
 535 2015-07-22  Alexander Fomin  <alexander.fomin@intel.com>
 536
 537         PR binutils/18631
 538         * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
 539         "EXEvexHalfBcstXmmq" for the second operand.
 540         (EVEX_W_0F79_P_2): Likewise.
 541         (EVEX_W_0F7A_P_2): Likewise.
 542         (EVEX_W_0F7B_P_2): Likewise.
 543
 544 2015-07-16  Alessandro Marzocchi  <alessandro.marzocchi@gmail.com>
 545
 546         * arm-dis.c (print_insn_coprocessor): Added support for quarter
 547         float bitfield format.
 548         (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
 549         quarter float bitfield format.
 550
 551 2015-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 552
 553         * configure: Regenerated.
 554
 555 2015-07-03  Alan Modra  <amodra@gmail.com>
 556
 557         * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
 558         * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries.  Add
 559         PPC_OPCODE_7450 to 7450 entry.  Add PPC_OPCODE_750 to 750cl entry.
 560
 561 2015-07-01  Sandra Loosemore  <sandra@codesourcery.com>
 562             Cesar Philippidis  <cesar@codesourcery.com>
 563
 564         * nios2-dis.c (nios2_extract_opcode): New.
 565         (nios2_disassembler_state): New.
 566         (nios2_find_opcode_hash): Use mach parameter to select correct
 567         disassembler state.
 568         (nios2_print_insn_arg): Extend to support new R2 argument letters
 569         and formats.
 570         (print_insn_nios2): Check for 16-bit instruction at end of memory.
 571         * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
 572         (NIOS2_NUM_OPCODES): Rename to...
 573         (NIOS2_NUM_R1_OPCODES): This.
 574         (nios2_r2_opcodes): New.
 575         (NIOS2_NUM_R2_OPCODES): New.
 576         (nios2_num_r2_opcodes): New.
 577         (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
 578         (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
 579         (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
 580         (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
 581         (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
 582
 583 2015-06-30  Amit Pawar  <Amit.Pawar@amd.com>
 584
 585         * i386-dis.c (OP_Mwaitx): New.
 586         (rm_table): Add monitorx/mwaitx.
 587         * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
 588         and CPU_ZNVER1_FLAGS.  Add CPU_MWAITX_FLAGS.
 589         (operand_type_init): Add CpuMWAITX.
 590         * i386-opc.h (CpuMWAITX): New.
 591         (i386_cpu_flags): Add cpumwaitx.
 592         * i386-opc.tbl: Add monitorx and mwaitx.
 593         * i386-init.h: Regenerated.
 594         * i386-tbl.h: Likewise.
 595
 596 2015-06-22  Peter Bergner  <bergner@vnet.ibm.com>
 597
 598         * ppc-opc.c (insert_ls): Test for invalid LS operands.
 599         (insert_esync): New function.
 600         (LS, WC): Use insert_ls.
 601         (ESYNC): Use insert_esync.
 602
 603 2015-06-22  Nick Clifton  <nickc@redhat.com>
 604
 605         * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
 606         requested region lies beyond it.
 607         * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
 608         looking for 32-bit insns.
 609         * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
 610         data.
 611         * sh-dis.c (print_insn_sh): Likewise.
 612         * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
 613         blocks of instructions.
 614         * vax-dis.c (print_insn_vax): Check that the requested address
 615         does not clash with the stop_vma.
 616
 617 2015-06-19  Peter Bergner  <bergner@vnet.ibm.com>
 618
 619         * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
 620         * ppc-opc.c (FXM4): Add non-zero optional value.
 621         (TBR): Likewise.
 622         (SXL): Likewise.
 623         (insert_fxm): Handle new default operand value.
 624         (extract_fxm): Likewise.
 625         (insert_tbr): Likewise.
 626         (extract_tbr): Likewise.
 627
 628 2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
 629
 630         * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
 631
 632 2015-06-16  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 633
 634         * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
 635
 636 2015-06-12  Peter Bergner  <bergner@vnet.ibm.com>
 637
 638         * ppc-opc.c: Add comment accidentally removed by old commit.
 639         (MTMSRD_L): Delete.
 640
 641 2015-06-04  Peter Bergner  <bergner@vnet.ibm.com>
 642
 643         * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
 644
 645 2015-06-04  Nick Clifton  <nickc@redhat.com>
 646
 647         PR 18474
 648         * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
 649
 650 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 651
 652         * arm-dis.c (arm_opcodes): Add "setpan".
 653         (thumb_opcodes): Add "setpan".
 654
 655 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 656
 657         * arm-dis.c (select_arm_features): Rework to avoid used of redefined
 658         macros.
 659
 660 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 661
 662         * aarch64-tbl.h (aarch64_feature_rdma): New.
 663         (RDMA): New.
 664         (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
 665         * aarch64-asm-2.c: Regenerate.
 666         * aarch64-dis-2.c: Regenerate.
 667         * aarch64-opc-2.c: Regenerate.
 668
 669 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 670
 671         * aarch64-tbl.h (aarch64_feature_lor): New.
 672         (LOR): New.
 673         (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
 674         "stllrb", "stllrh".
 675         * aarch64-asm-2.c: Regenerate.
 676         * aarch64-dis-2.c: Regenerate.
 677         * aarch64-opc-2.c: Regenerate.
 678
 679 2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
 680
 681         * aarch64-opc.c (F_ARCHEXT): New.
 682         (aarch64_sys_regs): Add "pan".
 683         (aarch64_sys_reg_supported_p): New.
 684         (aarch64_pstatefields): Add "pan".
 685         (aarch64_pstatefield_supported_p): New.
 686
 687 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 688
 689         * i386-tbl.h: Regenerate.
 690
 691 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 692
 693         * i386-dis.c (print_insn): Swap rounding mode specifier and
 694         general purpose register in Intel mode.
 695
 696 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 697
 698         * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
 699         * i386-tbl.h: Regenerate.
 700
 701 2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>
 702
 703         * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
 704         * i386-init.h: Regenerated.
 705
 706 2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>
 707
 708         PR binutis/18386
 709         * i386-dis.c: Add comments for '@'.
 710         (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
 711         (enum x86_64_isa): New.
 712         (isa64): Likewise.
 713         (print_i386_disassembler_options): Add amd64 and intel64.
 714         (print_insn): Handle amd64 and intel64.
 715         (putop): Handle '@'.
 716         (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
 717         * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
 718         * i386-opc.h (AMD64): New.
 719         (CpuIntel64): Likewise.
 720         (i386_cpu_flags): Add cpuamd64 and cpuintel64.
 721         * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
 722         Mark direct call/jmp without Disp16|Disp32 as Intel64.
 723         * i386-init.h: Regenerated.
 724         * i386-tbl.h: Likewise.
 725
 726 2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>
 727
 728         * ppc-opc.c (IH) New define.
 729         (powerpc_opcodes) <wait>: Do not enable for POWER7.
 730         <tlbie>: Add RS operand for POWER7.
 731         <slbia>: Add IH operand for POWER6.
 732
 733 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 734
 735         * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
 736         direct branch.
 737         (jmp): Likewise.
 738         * i386-tbl.h: Regenerated.
 739
 740 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 741
 742         * configure.ac: Support bfd_iamcu_arch.
 743         * disassemble.c (disassembler): Support bfd_iamcu_arch.
 744         * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
 745         CPU_IAMCU_COMPAT_FLAGS.
 746         (cpu_flags): Add CpuIAMCU.
 747         * i386-opc.h (CpuIAMCU): New.
 748         (i386_cpu_flags): Add cpuiamcu.
 749         * configure: Regenerated.
 750         * i386-init.h: Likewise.
 751         * i386-tbl.h: Likewise.
 752
 753 2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>
 754
 755         PR binutis/18386
 756         * i386-dis.c (X86_64_E8): New.
 757         (X86_64_E9): Likewise.
 758         Update comments on 'T', 'U', 'V'.  Add comments for '^'.
 759         (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
 760         (x86_64_table): Add X86_64_E8 and X86_64_E9.
 761         (mod_table): Replace {T|} with ^ on Jcall/Jmp.
 762         (putop): Handle '^'.
 763         (OP_J): Ignore the operand size prefix in 64-bit.  Don't check
 764         REX_W.
 765
 766 2015-04-30  DJ Delorie  <dj@redhat.com>
 767
 768         * disassemble.c (disassembler): Choose suitable disassembler based
 769         on E_ABI.
 770         * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
 771         it to decode mul/div insns.
 772         * rl78-decode.c: Regenerate.
 773         * rl78-dis.c (print_insn_rl78): Rename to...
 774         (print_insn_rl78_common): ...this, take ISA parameter.
 775         (print_insn_rl78): New.
 776         (print_insn_rl78_g10): New.
 777         (print_insn_rl78_g13): New.
 778         (print_insn_rl78_g14): New.
 779         (rl78_get_disassembler): New.
 780
 781 2015-04-29  Nick Clifton  <nickc@redhat.com>
 782
 783         * po/fr.po: Updated French translation.
 784
 785 2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>
 786
 787         * ppc-opc.c (DCBT_EO): New define.
 788         (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
 789         <lharx>: Likewise.
 790         <stbcx.>: Likewise.
 791         <sthcx.>: Likewise.
 792         <waitrsv>: Do not enable for POWER7 and later.
 793         <waitimpl>: Likewise.
 794         <dcbt>: Default to the two operand form of the instruction for all
 795         "old" cpus.  For "new" cpus, use the operand ordering that matches
 796         whether the cpu is server or embedded.
 797         <dcbtst>: Likewise.
 798
 799 2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 800
 801         * s390-opc.c: New instruction type VV0UU2.
 802         * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
 803         and WFC.
 804
 805 2015-04-23  Jan Beulich  <jbeulich@suse.com>
 806
 807         * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
 808         * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
 809         vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
 810         (vfpclasspd, vfpclassps): Add %XZ.
 811
 812 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 813
 814         * i386-dis.c (PREFIX_UD_SHIFT): Removed.
 815         (PREFIX_UD_REPZ): Likewise.
 816         (PREFIX_UD_REPNZ): Likewise.
 817         (PREFIX_UD_DATA): Likewise.
 818         (PREFIX_UD_ADDR): Likewise.
 819         (PREFIX_UD_LOCK): Likewise.
 820
 821 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 822
 823         * i386-dis.c (prefix_requirement): Removed.
 824         (print_insn): Don't set prefix_requirement.  Check
 825         dp->prefix_requirement instead of prefix_requirement.
 826
 827 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 828
 829         PR binutils/17898
 830         * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
 831         (PREFIX_MOD_0_0FC7_REG_6): This.
 832         (PREFIX_MOD_3_0FC7_REG_6): New.
 833         (PREFIX_MOD_3_0FC7_REG_7): Likewise.
 834         (prefix_table): Replace PREFIX_0FC7_REG_6 with
 835         PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
 836         PREFIX_MOD_3_0FC7_REG_7.
 837         (mod_table): Replace PREFIX_0FC7_REG_6 with
 838         PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
 839         PREFIX_MOD_3_0FC7_REG_7.
 840
 841 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 842
 843         * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
 844         (PREFIX_MANDATORY_REPNZ): Likewise.
 845         (PREFIX_MANDATORY_DATA): Likewise.
 846         (PREFIX_MANDATORY_ADDR): Likewise.
 847         (PREFIX_MANDATORY_LOCK): Likewise.
 848         (PREFIX_MANDATORY): Likewise.
 849         (PREFIX_UD_SHIFT): Set to 8
 850         (PREFIX_UD_REPZ): Updated.
 851         (PREFIX_UD_REPNZ): Likewise.
 852         (PREFIX_UD_DATA): Likewise.
 853         (PREFIX_UD_ADDR): Likewise.
 854         (PREFIX_UD_LOCK): Likewise.
 855         (PREFIX_IGNORED_SHIFT): New.
 856         (PREFIX_IGNORED_REPZ): Likewise.
 857         (PREFIX_IGNORED_REPNZ): Likewise.
 858         (PREFIX_IGNORED_DATA): Likewise.
 859         (PREFIX_IGNORED_ADDR): Likewise.
 860         (PREFIX_IGNORED_LOCK): Likewise.
 861         (PREFIX_OPCODE): Likewise.
 862         (PREFIX_IGNORED): Likewise.
 863         (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
 864         (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 865         (three_byte_table): Likewise.
 866         (mod_table): Likewise.
 867         (mandatory_prefix): Renamed to ...
 868         (prefix_requirement): This.
 869         (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 870         Update PREFIX_90 entry.
 871         (get_valid_dis386): Check prefix_requirement to see if a prefix
 872         should be ignored.
 873         (print_insn): Replace mandatory_prefix with prefix_requirement.
 874
 875 2015-04-15  Renlin Li  <renlin.li@arm.com>
 876
 877         * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
 878         use it for ssat and ssat16.
 879         (print_insn_thumb32): Add handle case for 'D' control code.
 880
 881 2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
 882             H.J. Lu  <hongjiu.lu@intel.com>
 883
 884         * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
 885         * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
 886         PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
 887         PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
 888         PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
 889         (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
 890         Fill prefix_requirement field.
 891         (struct dis386): Add prefix_requirement field.
 892         (dis386): Fill prefix_requirement field.
 893         (dis386_twobyte): Ditto.
 894         (twobyte_has_mandatory_prefix_: Remove.
 895         (reg_table): Fill prefix_requirement field.
 896         (prefix_table): Ditto.
 897         (x86_64_table): Ditto.
 898         (three_byte_table): Ditto.
 899         (xop_table): Ditto.
 900         (vex_table): Ditto.
 901         (vex_len_table): Ditto.
 902         (vex_w_table): Ditto.
 903         (mod_table): Ditto.
 904         (bad_opcode): Ditto.
 905         (print_insn): Use prefix_requirement.
 906         (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
 907         FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
 908         (float_reg): Ditto.
 909
 910 2015-03-30  Mike Frysinger  <vapier@gentoo.org>
 911
 912         * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
 913
 914 2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 915
 916         * Makefile.in: Regenerated.
 917
 918 2015-03-25  Anton Blanchard  <anton@samba.org>
 919
 920         * ppc-dis.c (disassemble_init_powerpc): Only initialise
 921         powerpc_opcd_indices and vle_opcd_indices once.
 922
 923 2015-03-25  Anton Blanchard  <anton@samba.org>
 924
 925         * ppc-opc.c (powerpc_opcodes): Add slbfee.
 926
 927 2015-03-24  Terry Guo  <terry.guo@arm.com>
 928
 929         * arm-dis.c (opcode32): Updated to use new arm feature struct.
 930         (opcode16): Likewise.
 931         (coprocessor_opcodes): Replace bit with feature struct.
 932         (neon_opcodes): Likewise.
 933         (arm_opcodes): Likewise.
 934         (thumb_opcodes): Likewise.
 935         (thumb32_opcodes): Likewise.
 936         (print_insn_coprocessor): Likewise.
 937         (print_insn_arm): Likewise.
 938         (select_arm_features): Follow new feature struct.
 939
 940 2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
 941
 942         * i386-dis.c (rm_table): Add clzero.
 943         * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
 944         Add CPU_CLZERO_FLAGS.
 945         (cpu_flags): Add CpuCLZERO.
 946         * i386-opc.h: Add CpuCLZERO.
 947         * i386-opc.tbl: Add clzero.
 948         * i386-init.h: Re-generated.
 949         * i386-tbl.h: Re-generated.
 950
 951 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 952
 953         * mips-opc.c (decode_mips_operand): Fix constraint issues
 954         with u and y operands.
 955
 956 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 957
 958         * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
 959
 960 2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 961
 962         * s390-opc.c: Add new IBM z13 instructions.
 963         * s390-opc.txt: Likewise.
 964
 965 2015-03-10  Renlin Li  <renlin.li@arm.com>
 966
 967         * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
 968         stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
 969         related alias.
 970         * aarch64-asm-2.c: Regenerate.
 971         * aarch64-dis-2.c: Likewise.
 972         * aarch64-opc-2.c: Likewise.
 973
 974 2015-03-03  Jiong Wang  <jiong.wang@arm.com>
 975
 976         * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
 977
 978 2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>
 979
 980         * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
 981         arch_sh_up.
 982         (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
 983         arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
 984
 985 2015-02-23  Vinay  <Vinay.G@kpit.com>
 986
 987         * rl78-decode.opc (MOV): Added space between two operands for
 988         'mov' instruction in index addressing mode.
 989         * rl78-decode.c: Regenerate.
 990
 991 2015-02-19  Pedro Alves  <palves@redhat.com>
 992
 993         * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
 994
 995 2015-02-10  Pedro Alves  <palves@redhat.com>
 996             Tom Tromey  <tromey@redhat.com>
 997
 998         * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
 999         microblaze_and, microblaze_xor.
1000         * microblaze-opc.h (opcodes): Adjust.
1001
1002 2015-01-28  James Bowman  <james.bowman@ftdichip.com>
1003
1004         * Makefile.am: Add FT32 files.
1005         * configure.ac: Handle FT32.
1006         * disassemble.c (disassembler): Call print_insn_ft32.
1007         * ft32-dis.c: New file.
1008         * ft32-opc.c: New file.
1009         * Makefile.in: Regenerate.
1010         * configure: Regenerate.
1011         * po/POTFILES.in: Regenerate.
1012
1013 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
1014
1015         * nds32-asm.c (keyword_sr): Add new system registers.
1016
1017 2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1018
1019         * s390-dis.c (s390_extract_operand): Support vector register
1020         operands.
1021         (s390_print_insn_with_opcode): Support new operands types and add
1022         new handling of optional operands.
1023         * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
1024         and include opcode/s390.h instead.
1025         (struct op_struct): New field `flags'.
1026         (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
1027         (dumpTable): Dump flags.
1028         (main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
1029         string.
1030         * s390-opc.c: Add new operands types, instruction formats, and
1031         instruction masks.
1032         (s390_opformats): Add new formats for .insn.
1033         * s390-opc.txt: Add new instructions.
1034
1035 2015-01-01  Alan Modra  <amodra@gmail.com>
1036
1037         Update year range in copyright notice of all files.
1038
1039 For older changes see ChangeLog-2014
1040 \f
1041 Copyright (C) 2015 Free Software Foundation, Inc.
1042
1043 Copying and distribution of this file, with or without modification,
1044 are permitted in any medium without royalty provided the copyright
1045 notice and this notice are preserved.
1046
1047 Local Variables:
1048 mode: change-log
1049 left-margin: 8
1050 fill-column: 74
1051 version-control: never
1052 End: