opcodes/ChangeLog

   1 2011-10-26  Joern Rennecke  <joern.rennecke@embecosm.com>
   2
   3         * disassemble.c (ARCH_epiphany): Move into alphasorted spot.
   4
   5         * epiphany-asm.c, epiphany-opc.h: Regenerate.
   6
   7 2011-10-25  Joern Rennecke  <joern.rennecke@embecosm.com>
   8
   9         * Makefile.am (HFILES): Add epiphany-desc.h and epiphany-opc.h .
  10         (TARGET_LIBOPCODES_CFILES): Add  epiphany-asm.c, epiphany-desc.c,
  11         epiphany-dis.c, epiphany-ibld.c and epiphany-opc.c .
  12         (CLEANFILES): Add stamp-epiphany.
  13         (EPIPHANY_DEPS): Set.  Make CGEN-generated Epiphany files depend on it.
  14         (stamp-epiphany): New rule.
  15         * configure.in: Handle bfd_epiphany_arch.
  16         * disassemble.c (ARCH_epiphany): Define.
  17         (disassembler): Handle bfd_arch_epiphany.
  18         * epiphany-asm.c: New file.
  19         * epiphany-desc.c: New file.
  20         * epiphany-desc.h: New file.
  21         * epiphany-dis.c: New file.
  22         * epiphany-ibld.c: New file.
  23         * epiphany-opc.c: New file.
  24         * epiphany-opc.h: New file.
  25         * Makefile.in: Regenerate.
  26         * configure: Regenerate.
  27         * po/POTFILES.in: Regenerate.
  28         * po/opcodes.pot: Regenerate.
  29
  30 2011-10-24  Julian Brown  <julian@codesourcery.com>
  31
  32         * m68k-opc.c (m68k_opcodes): Fix entries for ColdFire moveml.
  33
  34 2011-10-21  Jan Glauber  <jang@linux.vnet.ibm.com>
  35
  36         * s390-opc.txt: Add CPUMF instructions.
  37
  38 2011-10-18  Jie Zhang  <jie@codesourcery.com>
  39             Julian Brown  <julian@codesourcery.com>
  40
  41         * arm-dis.c (print_insn_arm): Explicitly specify rotation if needed.
  42
  43 2011-10-10  Nick Clifton  <nickc@redhat.com>
  44
  45         * po/es.po: Updated Spanish translation.
  46         * po/fi.po: Updated Finnish translation.
  47
  48 2011-09-28  Jan Beulich  <jbeulich@suse.com>
  49
  50         * ppc-opc.c (insert_nbi, insert_rbx, FRAp, FRBp, FRSp, FRTp, NBI, RAX,
  51         RBX): New.
  52         (insert_bo, insert_boe): Reject bcctr with bit 2 in bo unset.
  53         (powerpc_opcodes): Use RAX for second and RBXC for third operand of
  54         lswx. Use NBI for third operand of lswi. Use FRTp for first operand of
  55         lfdp and lfdpx. Use FRSp for first operand of stfdp and stfdpx, and
  56         mark them as invalid on POWER7. Use FRTp, FRAp, and FRBp repsectively
  57         on DFP quad instructions.
  58
  59 2011-09-27  David S. Miller  <davem@davemloft.net>
  60
  61         * sparc-opc.c (sparc_opcodes): Fix random instruction to write
  62         to a float instead of an integer register.
  63
  64 2011-09-26  David S. Miller  <davem@davemloft.net>
  65
  66         * sparc-opc.c (sparc_opcodes): Add integer multiply-add
  67         instructions.
  68
  69 2011-09-21  David S. Miller  <davem@davemloft.net>
  70
  71         * sparc-opc.c (sparc_opcodes): Annotate table with HWCAP flag
  72         bits.  Fix "fchksm16" mnemonic.
  73
  74 2011-09-08  Mark Fortescue <mark@mtfhpc.demon.co.uk>
  75
  76         The changes below bring 'mov' and 'ticc' instructions into line
  77         with the V8 SPARC Architecture Manual.
  78         * sparc-opc.c (sparc_opcodes): Add entry for 'ticc imm + regrs1'.
  79         * sparc-opc.c (sparc_opcodes): Add alias entries for
  80         'mov regrs2,%asrX'; 'mov regrs2,%y'; 'mov regrs2,%prs';
  81         'mov regrs2,%wim' and 'mov regrs2,%tbr'.
  82         * sparc-opc.c (sparc_opcodes): Move/Change entries for
  83         'mov imm,%asrX'; 'mov imm,%y'; 'mov imm,%prs'; 'mov imm,%wim'
  84         and 'mov imm,%tbr'.
  85         * sparc-opc.c (sparc_opcodes): Add wr alias entries to match above
  86         mov aliases.
  87
  88         * sparc-opc.c (sparc_opcodes): Add entry for 'save simm13,regrs1,regrd'
  89         This has been reported as being accepted by the Sun assmebler.
  90
  91 2011-09-08  David S. Miller  <davem@davemloft.net>
  92
  93         * sparc-opc.c (pdistn): Destination is integer not float register.
  94
  95 2011-09-07  Andreas Schwab  <schwab@linux-m68k.org>
  96
  97         PR gas/13145
  98         * m68k-opc.c: Use "y" in moveml pattern for mcfisa_a.
  99
 100 2011-08-26  Nick Clifton  <nickc@redhat.com>
 101
 102         * po/es.po: Updated Spanish translation.
 103
 104 2011-08-22  Nick Clifton  <nickc@redhat.com>
 105
 106         * Makefile.am (CPUDIR): Redfine to point to top level cpu
 107         directory.
 108         (stamp-frv): Use CPUDIR.
 109         (stamp-iq2000): Likewise.
 110         (stamp-lm32): Likewise.
 111         (stamp-m32c): Likewise.
 112         (stamp-mt): Likewise.
 113         (stamp-xc16x): Likewise.
 114         * Makefile.in: Regenerate.
 115
 116 2011-08-09  Chao-ying Fu  <fu@mips.com>
 117             Maciej W. Rozycki  <macro@codesourcery.com>
 118
 119         * mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2"
 120         and "mips64r2".
 121         (print_insn_args, print_insn_micromips): Handle MCU.
 122         * micromips-opc.c (MC): New macro.
 123         (micromips_opcodes): Add "aclr", "aset" and "iret".
 124         * mips-opc.c (MC): New macro.
 125         (mips_builtin_opcodes): Add "aclr", "aset" and "iret".
 126
 127 2011-08-09  Maciej W. Rozycki  <macro@codesourcery.com>
 128
 129         * micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros.
 130         (MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise.
 131         (MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise.
 132         (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros.
 133         (RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise.
 134         (RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise.
 135         (WR_s): Update macro.
 136         (micromips_opcodes): Update register use flags of: "addiu",
 137         "addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu",
 138         "and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j",
 139         "jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li",
 140         "lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not",
 141         "nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw",
 142         "swm" and "xor" instructions.
 143
 144 2011-08-05  David S. Miller  <davem@davemloft.net>
 145
 146         * sparc-dis.c (v9a_ast_reg_names): Add "cps".
 147         (X_RS3): New macro.
 148         (print_insn_sparc): Handle '4', '5', and '(' format codes.
 149         Accept %asr numbers below 28.
 150         * sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
 151         instructions.
 152
 153 2011-08-02  Quentin Neill  <quentin.neill@amd.com>
 154
 155         * i386-dis.c (xop_table): Remove spurious bextr insn.
 156
 157 2011-08-01  H.J. Lu  <hongjiu.lu@intel.com>
 158
 159         PR ld/13048
 160         * i386-dis.c (print_insn): Optimize info->mach check.
 161
 162 2011-08-01  H.J. Lu  <hongjiu.lu@intel.com>
 163
 164         PR gas/13046
 165         * i386-opc.tbl: Add Disp32S to 64bit call.
 166         * i386-tbl.h: Regenerated.
 167
 168 2011-07-24  Chao-ying Fu  <fu@mips.com>
 169             Maciej W. Rozycki  <macro@codesourcery.com>
 170
 171         * micromips-opc.c: New file.
 172         * mips-dis.c (micromips_to_32_reg_b_map): New array.
 173         (micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
 174         (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
 175         (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
 176         (micromips_to_32_reg_q_map): Likewise.
 177         (micromips_imm_b_map, micromips_imm_c_map): Likewise.
 178         (micromips_ase): New variable.
 179         (is_micromips): New function.
 180         (set_default_mips_dis_options): Handle microMIPS ASE.
 181         (print_insn_micromips): New function.
 182         (is_compressed_mode_p): Likewise.
 183         (_print_insn_mips): Handle microMIPS instructions.
 184         * Makefile.am (CFILES): Add micromips-opc.c.
 185         * configure.in (bfd_mips_arch): Add micromips-opc.lo.
 186         * Makefile.in: Regenerate.
 187         * configure: Regenerate.
 188
 189         * mips-dis.c (micromips_to_32_reg_h_map): New variable.
 190         (micromips_to_32_reg_i_map): Likewise.
 191         (micromips_to_32_reg_m_map): Likewise.
 192         (micromips_to_32_reg_n_map): New macro.
 193
 194 2011-07-24  Maciej W. Rozycki  <macro@codesourcery.com>
 195
 196         * mips-opc.c (NODS): New macro.
 197         (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
 198         (DSP_VOLA): Likewise.
 199         (mips_builtin_opcodes): Add NODS annotation to "deret" and
 200         "eret". Replace INSN_SYNC with NODS throughout.  Use NODS in
 201         place of TRAP for "wait", "waiti" and "yield".
 202         * mips16-opc.c (NODS): New macro.
 203         (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
 204         (mips16_opcodes):  Use NODS in place of TRAP for "jalrc", "jrc",
 205         "restore" and "save".
 206
 207 2011-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 208
 209         * configure.in: Handle bfd_k1om_arch.
 210         * configure: Regenerated.
 211
 212         * disassemble.c (disassembler): Handle bfd_k1om_arch.
 213
 214         * i386-dis.c (print_insn): Handle bfd_mach_k1om and
 215         bfd_mach_k1om_intel_syntax.
 216
 217         * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to
 218         ~(CpuL1OM|CpuK1OM).  Add CPU_K1OM_FLAGS.
 219         (cpu_flags): Add CpuK1OM.
 220
 221         * i386-opc.h (CpuK1OM): New.
 222         (i386_cpu_flags): Add cpuk1om.
 223
 224         * i386-init.h: Regenerated.
 225         * i386-tbl.h: Likewise.
 226
 227 2011-07-12  Nick Clifton  <nickc@redhat.com>
 228
 229         * arm-dis.c (print_insn_arm): Revert previous, undocumented,
 230         accidental change.
 231
 232 2011-07-01  Nick Clifton  <nickc@redhat.com>
 233
 234         PR binutils/12329
 235         * avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM
 236         insns using post-increment addressing.
 237
 238 2011-06-30  H.J. Lu  <hongjiu.lu@intel.com>
 239
 240         * i386-dis.c (vex_len_table): Update rorxS.
 241
 242 2011-06-30  H.J. Lu  <hongjiu.lu@intel.com>
 243
 244         AVX Programming Reference (June, 2011)
 245         * i386-dis.c (vex_len_table): Correct rorxS.
 246
 247         * i386-opc.tbl: Correct rorx.
 248         * i386-tbl.h: Regenerated.
 249
 250 2011-06-29  H.J. Lu  <hongjiu.lu@intel.com>
 251
 252         * tilegx-opc.c (find_opcode): Replace "index" with "i".
 253         * tilepro-opc.c (find_opcode): Likewise.
 254
 255 2011-06-29  Richard Sandiford  <rdsandiford@googlemail.com>
 256
 257         * mips16-opc.c (jalrc, jrc): Move earlier in file.
 258
 259 2011-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 260
 261         * i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
 262         PREFIX_VEX_0F388E.
 263
 264 2011-06-17  Andreas Schwab  <schwab@redhat.com>
 265
 266         * Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
 267         (MOSTLYCLEANFILES): ... here.
 268         * Makefile.in: Regenerate.
 269
 270 2011-06-14  Alan Modra  <amodra@gmail.com>
 271
 272         * Makefile.in: Regenerate.
 273
 274 2011-06-13  Walter Lee  <walt@tilera.com>
 275
 276         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
 277         tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
 278         * Makefile.in: Regenerate.
 279         * configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
 280         * configure: Regenerate.
 281         * disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
 282         * po/POTFILES.in: Regenerate.
 283         * tilegx-dis.c: New file.
 284         * tilegx-opc.c: New file.
 285         * tilepro-dis.c: New file.
 286         * tilepro-opc.c: New file.
 287
 288 2011-06-10  H.J. Lu  <hongjiu.lu@intel.com>
 289
 290         AVX Programming Reference (June, 2011)
 291         * i386-dis.c (XMGatherQ): New.
 292         * i386-dis.c (EXxmm_mb): New.
 293         (EXxmm_mb): Likewise.
 294         (EXxmm_mw): Likewise.
 295         (EXxmm_md): Likewise.
 296         (EXxmm_mq): Likewise.
 297         (EXxmmdw): Likewise.
 298         (EXxmmqd): Likewise.
 299         (VexGatherQ): Likewise.
 300         (MVexVSIBDWpX): Likewise.
 301         (MVexVSIBQWpX): Likewise.
 302         (xmm_mb_mode): Likewise.
 303         (xmm_mw_mode): Likewise.
 304         (xmm_md_mode): Likewise.
 305         (xmm_mq_mode): Likewise.
 306         (xmmdw_mode): Likewise.
 307         (xmmqd_mode): Likewise.
 308         (ymmxmm_mode): Likewise.
 309         (vex_vsib_d_w_dq_mode): Likewise.
 310         (vex_vsib_q_w_dq_mode): Likewise.
 311         (MOD_VEX_0F385A_PREFIX_2): Likewise.
 312         (MOD_VEX_0F388C_PREFIX_2): Likewise.
 313         (MOD_VEX_0F388E_PREFIX_2): Likewise.
 314         (PREFIX_0F3882): Likewise.
 315         (PREFIX_VEX_0F3816): Likewise.
 316         (PREFIX_VEX_0F3836): Likewise.
 317         (PREFIX_VEX_0F3845): Likewise.
 318         (PREFIX_VEX_0F3846): Likewise.
 319         (PREFIX_VEX_0F3847): Likewise.
 320         (PREFIX_VEX_0F3858): Likewise.
 321         (PREFIX_VEX_0F3859): Likewise.
 322         (PREFIX_VEX_0F385A): Likewise.
 323         (PREFIX_VEX_0F3878): Likewise.
 324         (PREFIX_VEX_0F3879): Likewise.
 325         (PREFIX_VEX_0F388C): Likewise.
 326         (PREFIX_VEX_0F388E): Likewise.
 327         (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
 328         (PREFIX_VEX_0F38F5): Likewise.
 329         (PREFIX_VEX_0F38F6): Likewise.
 330         (PREFIX_VEX_0F3A00): Likewise.
 331         (PREFIX_VEX_0F3A01): Likewise.
 332         (PREFIX_VEX_0F3A02): Likewise.
 333         (PREFIX_VEX_0F3A38): Likewise.
 334         (PREFIX_VEX_0F3A39): Likewise.
 335         (PREFIX_VEX_0F3A46): Likewise.
 336         (PREFIX_VEX_0F3AF0): Likewise.
 337         (VEX_LEN_0F3816_P_2): Likewise.
 338         (VEX_LEN_0F3819_P_2): Likewise.
 339         (VEX_LEN_0F3836_P_2): Likewise.
 340         (VEX_LEN_0F385A_P_2_M_0): Likewise.
 341         (VEX_LEN_0F38F5_P_0): Likewise.
 342         (VEX_LEN_0F38F5_P_1): Likewise.
 343         (VEX_LEN_0F38F5_P_3): Likewise.
 344         (VEX_LEN_0F38F6_P_3): Likewise.
 345         (VEX_LEN_0F38F7_P_1): Likewise.
 346         (VEX_LEN_0F38F7_P_2): Likewise.
 347         (VEX_LEN_0F38F7_P_3): Likewise.
 348         (VEX_LEN_0F3A00_P_2): Likewise.
 349         (VEX_LEN_0F3A01_P_2): Likewise.
 350         (VEX_LEN_0F3A38_P_2): Likewise.
 351         (VEX_LEN_0F3A39_P_2): Likewise.
 352         (VEX_LEN_0F3A46_P_2): Likewise.
 353         (VEX_LEN_0F3AF0_P_3): Likewise.
 354         (VEX_W_0F3816_P_2): Likewise.
 355         (VEX_W_0F3818_P_2): Likewise.
 356         (VEX_W_0F3819_P_2): Likewise.
 357         (VEX_W_0F3836_P_2): Likewise.
 358         (VEX_W_0F3846_P_2): Likewise.
 359         (VEX_W_0F3858_P_2): Likewise.
 360         (VEX_W_0F3859_P_2): Likewise.
 361         (VEX_W_0F385A_P_2_M_0): Likewise.
 362         (VEX_W_0F3878_P_2): Likewise.
 363         (VEX_W_0F3879_P_2): Likewise.
 364         (VEX_W_0F3A00_P_2): Likewise.
 365         (VEX_W_0F3A01_P_2): Likewise.
 366         (VEX_W_0F3A02_P_2): Likewise.
 367         (VEX_W_0F3A38_P_2): Likewise.
 368         (VEX_W_0F3A39_P_2): Likewise.
 369         (VEX_W_0F3A46_P_2): Likewise.
 370         (MOD_VEX_0F3818_PREFIX_2): Removed.
 371         (MOD_VEX_0F3819_PREFIX_2): Likewise.
 372         (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
 373         (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
 374         (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
 375         (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
 376         (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
 377         (VEX_LEN_0F3A0E_P_2): Likewise.
 378         (VEX_LEN_0F3A0F_P_2): Likewise.
 379         (VEX_LEN_0F3A42_P_2): Likewise.
 380         (VEX_LEN_0F3A4C_P_2): Likewise.
 381         (VEX_W_0F3818_P_2_M_0): Likewise.
 382         (VEX_W_0F3819_P_2_M_0): Likewise.
 383         (prefix_table): Updated.
 384         (three_byte_table): Likewise.
 385         (vex_table): Likewise.
 386         (vex_len_table): Likewise.
 387         (vex_w_table): Likewise.
 388         (mod_table): Likewise.
 389         (putop): Handle "LW".
 390         (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
 391         xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
 392         vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
 393         (OP_EX): Likewise.
 394         (OP_E_memory): Handle vex_vsib_d_w_dq_mode and
 395         vex_vsib_q_w_dq_mode.
 396         (OP_XMM): Handle vex_vsib_q_w_dq_mode.
 397         (OP_VEX): Likewise.
 398
 399         * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
 400         and CPU_ANY_AVX_FLAGS.  Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
 401         CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
 402         (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
 403         (opcode_modifiers): Add VecSIB.
 404
 405         * i386-opc.h (CpuAVX2): New.
 406         (CpuBMI2): Likewise.
 407         (CpuLZCNT): Likewise.
 408         (CpuINVPCID): Likewise.
 409         (VecSIB128): Likewise.
 410         (VecSIB256): Likewise.
 411         (VecSIB): Likewise.
 412         (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
 413         (i386_opcode_modifier): Add vecsib.
 414
 415         * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
 416         * i386-init.h: Regenerated.
 417         * i386-tbl.h: Likewise.
 418
 419 2011-06-03  Quentin Neill  <quentin.neill@amd.com>
 420
 421         * i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
 422         * i386-init.h: Regenerated.
 423
 424 2011-06-03  Nick Clifton  <nickc@redhat.com>
 425
 426         PR binutils/12752
 427         * arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
 428         computing address offsets.
 429         (print_arm_address): Likewise.
 430         (print_insn_arm): Likewise.
 431         (print_insn_thumb16): Likewise.
 432         (print_insn_thumb32): Likewise.
 433
 434 2011-06-02  Jie Zhang <jie@codesourcery.com>
 435             Nathan Sidwell <nathan@codesourcery.com>
 436             Maciej Rozycki <macro@codesourcery.com>
 437
 438         * arm-dis.c (print_insn_coprocessor): Explicitly print #-0
 439         as address offset.
 440         (print_arm_address): Likewise. Elide positive #0 appropriately.
 441         (print_insn_arm): Likewise.
 442
 443 2011-06-02  Nick Clifton  <nickc@redhat.com>
 444
 445         PR gas/12752
 446         * arm-dis.c (print_insn_thumb32): Do not sign extend  addresses
 447         passed to print_address_func.
 448
 449 2011-06-02  Nick Clifton  <nickc@redhat.com>
 450
 451         * arm-dis.c: Fix spelling mistakes.
 452         * op/opcodes.pot: Regenerate.
 453
 454 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 455
 456         * s390-opc.c: Replace S390_OPERAND_REG_EVEN with
 457         S390_OPERAND_REG_PAIR.  Fix INSTR_RRF_0UFEF instruction type.
 458         * s390-opc.txt: Fix cxr instruction type.
 459
 460 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 461
 462         * s390-opc.c: Add new instruction types marking register pair
 463         operands.
 464         * s390-opc.txt: Match instructions having register pair operands
 465         to the new instruction types.
 466
 467 2011-05-19  Nick Clifton  <nickc@redhat.com>
 468
 469         * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
 470         operands.
 471
 472 2011-05-10  Quentin Neill  <quentin.neill@amd.com>
 473
 474         * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
 475         * i386-init.h: Regenerated.
 476
 477 2011-04-27  Nick Clifton  <nickc@redhat.com>
 478
 479         * po/da.po: Updated Danish translation.
 480
 481 2011-04-26  Anton Blanchard  <anton@samba.org>
 482
 483         * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
 484
 485 2011-04-21  DJ Delorie  <dj@redhat.com>
 486
 487         * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
 488         * rx-decode.c: Regenerate.
 489
 490 2011-04-20  H.J. Lu  <hongjiu.lu@intel.com>
 491
 492         * i386-init.h: Regenerated.
 493
 494 2011-04-19  Quentin Neill  <quentin.neill@amd.com>
 495
 496         * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
 497         from bdver1 flags.
 498
 499 2011-04-13  Nick Clifton  <nickc@redhat.com>
 500
 501         * v850-dis.c (disassemble): Always print a closing square brace if
 502         an opening square brace was printed.
 503
 504 2011-04-12  Nick Clifton  <nickc@redhat.com>
 505
 506         PR binutils/12534
 507         * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
 508         patterns.
 509         (print_insn_thumb32): Handle %L.
 510
 511 2011-04-11  Julian Brown  <julian@codesourcery.com>
 512
 513         * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
 514         (print_insn_thumb32): Add APSR bitmask support.
 515
 516 2011-04-07  Paul Carroll<pcarroll@codesourcery.com>
 517
 518         * arm-dis.c (print_insn): init vars moved into private_data structure.
 519
 520 2011-03-24  Mike Frysinger  <vapier@gentoo.org>
 521
 522         * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
 523
 524 2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
 525
 526         * avr-dis.c (avr_operand): Add opcode_str parameter. Check for
 527         post-increment to support LPM Z+ instruction. Add support for 'E'
 528         constraint for DES instruction.
 529         (print_insn_avr): Adjust calls to avr_operand. Rename variable.
 530
 531 2011-03-14  Richard Sandiford  <richard.sandiford@linaro.org>
 532
 533         * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
 534
 535 2011-03-14  Richard Sandiford  <richard.sandiford@linaro.org>
 536
 537         * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
 538         Use branch types instead.
 539         (print_insn): Likewise.
 540
 541 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 542
 543         * mips-opc.c (mips_builtin_opcodes): Correct register use
 544         annotation of "alnv.ps".
 545
 546 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 547
 548         * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
 549
 550 2011-02-22  Mike Frysinger  <vapier@gentoo.org>
 551
 552         * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
 553
 554 2011-02-22  Mike Frysinger  <vapier@gentoo.org>
 555
 556         * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
 557
 558 2011-02-19  Mike Frysinger  <vapier@gentoo.org>
 559
 560         * bfin-dis.c (saved_state): Mark static.  Change a[01]x to ax[] and
 561         a[01]w to aw[].  Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
 562         av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
 563         exception, end_of_registers, msize, memory, bfd_mach.
 564         (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
 565         LB0REG, LC1REG, LT1REG, LB1REG): Delete
 566         (AXREG, AWREG, LCREG, LTREG, LBREG): Define.
 567         (get_allreg): Change to new defines.  Fallback to abort().
 568
 569 2011-02-14  Mike Frysinger  <vapier@gentoo.org>
 570
 571         * bfin-dis.c: Add whitespace/parenthesis where needed.
 572
 573 2011-02-14  Mike Frysinger  <vapier@gentoo.org>
 574
 575         * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
 576         than 7.
 577
 578 2011-02-13  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
 579
 580         * configure: Regenerate.
 581
 582 2011-02-13  Mike Frysinger  <vapier@gentoo.org>
 583
 584         * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
 585
 586 2011-02-13  Mike Frysinger  <vapier@gentoo.org>
 587
 588         * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1.  Output
 589         dregs only when P is set, and dregs_lo otherwise.
 590
 591 2011-02-13  Mike Frysinger  <vapier@gentoo.org>
 592
 593         * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
 594
 595 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 596
 597         * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
 598
 599 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 600
 601         * bfin-dis.c (machine_registers): Delete REG_GP.
 602         (reg_names): Delete "GP".
 603         (decode_allregs): Change REG_GP to REG_LASTREG.
 604
 605 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 606
 607         * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
 608         M_IH, M_IU): Delete.
 609
 610 2011-02-11  Mike Frysinger  <vapier@gentoo.org>
 611
 612         * bfin-dis.c (reg_names): Add const.
 613         (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
 614         decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
 615         decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
 616         decode_counters, decode_allregs): Likewise.
 617
 618 2011-02-09  Michael Snyder  <msnyder@vmware.com>
 619
 620         * i386-dis.c (OP_J): Parenthesize expression to prevent
 621         truncated addresses.
 622         (print_insn): Fix indentation off-by-one.
 623
 624 2011-02-01  Nick Clifton  <nickc@redhat.com>
 625
 626         * po/da.po: Updated Danish translation.
 627
 628 2011-01-21  Dave Murphy  <davem@devkitpro.org>
 629
 630         * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
 631
 632 2011-01-18  H.J. Lu  <hongjiu.lu@intel.com>
 633
 634         * i386-dis.c (sIbT): New.
 635         (b_T_mode): Likewise.
 636         (dis386): Replace sIb with sIbT on "pushT".
 637         (x86_64_table): Replace sIb with Ib on "aam" and "aad".
 638         (OP_sI): Handle b_T_mode.  Properly sign-extend byte.
 639
 640 2011-01-18  Jan Kratochvil  <jan.kratochvil@redhat.com>
 641
 642         * i386-init.h: Regenerated.
 643         * i386-tbl.h: Regenerated
 644
 645 2011-01-17  Quentin Neill  <quentin.neill@amd.com>
 646
 647         * i386-dis.c (REG_XOP_TBM_01): New.
 648         (REG_XOP_TBM_02): New.
 649         (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
 650         (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
 651         entries, and add bextr instruction.
 652
 653         * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
 654         (cpu_flags): Add CpuTBM.
 655
 656         * i386-opc.h (CpuTBM) New.
 657         (i386_cpu_flags): Add bit cputbm.
 658
 659         * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
 660         blcs, blsfill, blsic, t1mskc, and tzmsk.
 661
 662 2011-01-12  DJ Delorie  <dj@redhat.com>
 663
 664         * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
 665
 666 2011-01-11  Mingjie Xing  <mingjie.xing@gmail.com>
 667
 668         * mips-dis.c (print_insn_args): Adjust the value to print the real
 669         offset for "+c" argument.
 670
 671 2011-01-10  Nick Clifton  <nickc@redhat.com>
 672
 673         * po/da.po: Updated Danish translation.
 674
 675 2011-01-05  Nathan Sidwell  <nathan@codesourcery.com>
 676
 677         * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
 678
 679 2011-01-04  H.J. Lu  <hongjiu.lu@intel.com>
 680
 681         * i386-dis.c (REG_VEX_38F3): New.
 682         (PREFIX_0FBC): Likewise.
 683         (PREFIX_VEX_38F2): Likewise.
 684         (PREFIX_VEX_38F3_REG_1): Likewise.
 685         (PREFIX_VEX_38F3_REG_2): Likewise.
 686         (PREFIX_VEX_38F3_REG_3): Likewise.
 687         (PREFIX_VEX_38F7): Likewise.
 688         (VEX_LEN_38F2_P_0): Likewise.
 689         (VEX_LEN_38F3_R_1_P_0): Likewise.
 690         (VEX_LEN_38F3_R_2_P_0): Likewise.
 691         (VEX_LEN_38F3_R_3_P_0): Likewise.
 692         (VEX_LEN_38F7_P_0): Likewise.
 693         (dis386_twobyte): Use PREFIX_0FBC.
 694         (reg_table): Add REG_VEX_38F3.
 695         (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
 696         PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
 697         PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
 698         (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
 699         PREFIX_VEX_38F7.
 700         (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
 701         VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
 702         VEX_LEN_38F7_P_0.
 703
 704         * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
 705         (cpu_flags): Add CpuBMI.
 706
 707         * i386-opc.h (CpuBMI): New.
 708         (i386_cpu_flags): Add cpubmi.
 709
 710         * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
 711         * i386-init.h: Regenerated.
 712         * i386-tbl.h: Likewise.
 713
 714 2011-01-04  H.J. Lu  <hongjiu.lu@intel.com>
 715
 716         * i386-dis.c (VexGdq): New.
 717         (OP_VEX): Handle dq_mode.
 718
 719 2011-01-01  H.J. Lu  <hongjiu.lu@intel.com>
 720
 721         * i386-gen.c (process_copyright): Update copyright to 2011.
 722
 723 For older changes see ChangeLog-2010
 724 \f
 725 Local Variables:
 726 mode: change-log
 727 left-margin: 8
 728 fill-column: 74
 729 version-control: never
 730 End: