opcodes/ChangeLog

   1 2011-10-25  Joern Rennecke  <joern.rennecke@embecosm.com>
   2
   3         * Makefile.am (HFILES): Add epiphany-desc.h and epiphany-opc.h .
   4         (TARGET_LIBOPCODES_CFILES): Add  epiphany-asm.c, epiphany-desc.c,
   5         epiphany-dis.c, epiphany-ibld.c and epiphany-opc.c .
   6         (CLEANFILES): Add stamp-epiphany.
   7         (EPIPHANY_DEPS): Set.  Make CGEN-generated Epiphany files depend on it.
   8         (stamp-epiphany): New rule.
   9         * configure.in: Handle bfd_epiphany_arch.
  10         * disassemble.c (ARCH_epiphany): Define.
  11         (disassembler): Handle bfd_arch_epiphany.
  12         * epiphany-asm.c: New file.
  13         * epiphany-desc.c: New file.
  14         * epiphany-desc.h: New file.
  15         * epiphany-dis.c: New file.
  16         * epiphany-ibld.c: New file.
  17         * epiphany-opc.c: New file.
  18         * epiphany-opc.h: New file.
  19         * Makefile.in: Regenerate.
  20         * configure: Regenerate.
  21         * po/POTFILES.in: Regenerate.
  22         * po/opcodes.pot: Regenerate.
  23
  24 2011-10-24  Julian Brown  <julian@codesourcery.com>
  25
  26         * m68k-opc.c (m68k_opcodes): Fix entries for ColdFire moveml.
  27
  28 2011-10-21  Jan Glauber  <jang@linux.vnet.ibm.com>
  29
  30         * s390-opc.txt: Add CPUMF instructions.
  31
  32 2011-10-18  Jie Zhang  <jie@codesourcery.com>
  33             Julian Brown  <julian@codesourcery.com>
  34
  35         * arm-dis.c (print_insn_arm): Explicitly specify rotation if needed.
  36
  37 2011-10-10  Nick Clifton  <nickc@redhat.com>
  38
  39         * po/es.po: Updated Spanish translation.
  40         * po/fi.po: Updated Finnish translation.
  41
  42 2011-09-28  Jan Beulich  <jbeulich@suse.com>
  43
  44         * ppc-opc.c (insert_nbi, insert_rbx, FRAp, FRBp, FRSp, FRTp, NBI, RAX,
  45         RBX): New.
  46         (insert_bo, insert_boe): Reject bcctr with bit 2 in bo unset.
  47         (powerpc_opcodes): Use RAX for second and RBXC for third operand of
  48         lswx. Use NBI for third operand of lswi. Use FRTp for first operand of
  49         lfdp and lfdpx. Use FRSp for first operand of stfdp and stfdpx, and
  50         mark them as invalid on POWER7. Use FRTp, FRAp, and FRBp repsectively
  51         on DFP quad instructions.
  52
  53 2011-09-27  David S. Miller  <davem@davemloft.net>
  54
  55         * sparc-opc.c (sparc_opcodes): Fix random instruction to write
  56         to a float instead of an integer register.
  57
  58 2011-09-26  David S. Miller  <davem@davemloft.net>
  59
  60         * sparc-opc.c (sparc_opcodes): Add integer multiply-add
  61         instructions.
  62
  63 2011-09-21  David S. Miller  <davem@davemloft.net>
  64
  65         * sparc-opc.c (sparc_opcodes): Annotate table with HWCAP flag
  66         bits.  Fix "fchksm16" mnemonic.
  67
  68 2011-09-08  Mark Fortescue <mark@mtfhpc.demon.co.uk>
  69
  70         The changes below bring 'mov' and 'ticc' instructions into line
  71         with the V8 SPARC Architecture Manual.
  72         * sparc-opc.c (sparc_opcodes): Add entry for 'ticc imm + regrs1'.
  73         * sparc-opc.c (sparc_opcodes): Add alias entries for
  74         'mov regrs2,%asrX'; 'mov regrs2,%y'; 'mov regrs2,%prs';
  75         'mov regrs2,%wim' and 'mov regrs2,%tbr'.
  76         * sparc-opc.c (sparc_opcodes): Move/Change entries for
  77         'mov imm,%asrX'; 'mov imm,%y'; 'mov imm,%prs'; 'mov imm,%wim'
  78         and 'mov imm,%tbr'.
  79         * sparc-opc.c (sparc_opcodes): Add wr alias entries to match above
  80         mov aliases.
  81
  82         * sparc-opc.c (sparc_opcodes): Add entry for 'save simm13,regrs1,regrd'
  83         This has been reported as being accepted by the Sun assmebler.
  84
  85 2011-09-08  David S. Miller  <davem@davemloft.net>
  86
  87         * sparc-opc.c (pdistn): Destination is integer not float register.
  88
  89 2011-09-07  Andreas Schwab  <schwab@linux-m68k.org>
  90
  91         PR gas/13145
  92         * m68k-opc.c: Use "y" in moveml pattern for mcfisa_a.
  93
  94 2011-08-26  Nick Clifton  <nickc@redhat.com>
  95
  96         * po/es.po: Updated Spanish translation.
  97
  98 2011-08-22  Nick Clifton  <nickc@redhat.com>
  99
 100         * Makefile.am (CPUDIR): Redfine to point to top level cpu
 101         directory.
 102         (stamp-frv): Use CPUDIR.
 103         (stamp-iq2000): Likewise.
 104         (stamp-lm32): Likewise.
 105         (stamp-m32c): Likewise.
 106         (stamp-mt): Likewise.
 107         (stamp-xc16x): Likewise.
 108         * Makefile.in: Regenerate.
 109
 110 2011-08-09  Chao-ying Fu  <fu@mips.com>
 111             Maciej W. Rozycki  <macro@codesourcery.com>
 112
 113         * mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2"
 114         and "mips64r2".
 115         (print_insn_args, print_insn_micromips): Handle MCU.
 116         * micromips-opc.c (MC): New macro.
 117         (micromips_opcodes): Add "aclr", "aset" and "iret".
 118         * mips-opc.c (MC): New macro.
 119         (mips_builtin_opcodes): Add "aclr", "aset" and "iret".
 120
 121 2011-08-09  Maciej W. Rozycki  <macro@codesourcery.com>
 122
 123         * micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros.
 124         (MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise.
 125         (MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise.
 126         (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros.
 127         (RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise.
 128         (RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise.
 129         (WR_s): Update macro.
 130         (micromips_opcodes): Update register use flags of: "addiu",
 131         "addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu",
 132         "and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j",
 133         "jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li",
 134         "lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not",
 135         "nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw",
 136         "swm" and "xor" instructions.
 137
 138 2011-08-05  David S. Miller  <davem@davemloft.net>
 139
 140         * sparc-dis.c (v9a_ast_reg_names): Add "cps".
 141         (X_RS3): New macro.
 142         (print_insn_sparc): Handle '4', '5', and '(' format codes.
 143         Accept %asr numbers below 28.
 144         * sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
 145         instructions.
 146
 147 2011-08-02  Quentin Neill  <quentin.neill@amd.com>
 148
 149         * i386-dis.c (xop_table): Remove spurious bextr insn.
 150
 151 2011-08-01  H.J. Lu  <hongjiu.lu@intel.com>
 152
 153         PR ld/13048
 154         * i386-dis.c (print_insn): Optimize info->mach check.
 155
 156 2011-08-01  H.J. Lu  <hongjiu.lu@intel.com>
 157
 158         PR gas/13046
 159         * i386-opc.tbl: Add Disp32S to 64bit call.
 160         * i386-tbl.h: Regenerated.
 161
 162 2011-07-24  Chao-ying Fu  <fu@mips.com>
 163             Maciej W. Rozycki  <macro@codesourcery.com>
 164
 165         * micromips-opc.c: New file.
 166         * mips-dis.c (micromips_to_32_reg_b_map): New array.
 167         (micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
 168         (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
 169         (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
 170         (micromips_to_32_reg_q_map): Likewise.
 171         (micromips_imm_b_map, micromips_imm_c_map): Likewise.
 172         (micromips_ase): New variable.
 173         (is_micromips): New function.
 174         (set_default_mips_dis_options): Handle microMIPS ASE.
 175         (print_insn_micromips): New function.
 176         (is_compressed_mode_p): Likewise.
 177         (_print_insn_mips): Handle microMIPS instructions.
 178         * Makefile.am (CFILES): Add micromips-opc.c.
 179         * configure.in (bfd_mips_arch): Add micromips-opc.lo.
 180         * Makefile.in: Regenerate.
 181         * configure: Regenerate.
 182
 183         * mips-dis.c (micromips_to_32_reg_h_map): New variable.
 184         (micromips_to_32_reg_i_map): Likewise.
 185         (micromips_to_32_reg_m_map): Likewise.
 186         (micromips_to_32_reg_n_map): New macro.
 187
 188 2011-07-24  Maciej W. Rozycki  <macro@codesourcery.com>
 189
 190         * mips-opc.c (NODS): New macro.
 191         (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
 192         (DSP_VOLA): Likewise.
 193         (mips_builtin_opcodes): Add NODS annotation to "deret" and
 194         "eret". Replace INSN_SYNC with NODS throughout.  Use NODS in
 195         place of TRAP for "wait", "waiti" and "yield".
 196         * mips16-opc.c (NODS): New macro.
 197         (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
 198         (mips16_opcodes):  Use NODS in place of TRAP for "jalrc", "jrc",
 199         "restore" and "save".
 200
 201 2011-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 202
 203         * configure.in: Handle bfd_k1om_arch.
 204         * configure: Regenerated.
 205
 206         * disassemble.c (disassembler): Handle bfd_k1om_arch.
 207
 208         * i386-dis.c (print_insn): Handle bfd_mach_k1om and
 209         bfd_mach_k1om_intel_syntax.
 210
 211         * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to
 212         ~(CpuL1OM|CpuK1OM).  Add CPU_K1OM_FLAGS.
 213         (cpu_flags): Add CpuK1OM.
 214
 215         * i386-opc.h (CpuK1OM): New.
 216         (i386_cpu_flags): Add cpuk1om.
 217
 218         * i386-init.h: Regenerated.
 219         * i386-tbl.h: Likewise.
 220
 221 2011-07-12  Nick Clifton  <nickc@redhat.com>
 222
 223         * arm-dis.c (print_insn_arm): Revert previous, undocumented,
 224         accidental change.
 225
 226 2011-07-01  Nick Clifton  <nickc@redhat.com>
 227
 228         PR binutils/12329
 229         * avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM
 230         insns using post-increment addressing.
 231
 232 2011-06-30  H.J. Lu  <hongjiu.lu@intel.com>
 233
 234         * i386-dis.c (vex_len_table): Update rorxS.
 235
 236 2011-06-30  H.J. Lu  <hongjiu.lu@intel.com>
 237
 238         AVX Programming Reference (June, 2011)
 239         * i386-dis.c (vex_len_table): Correct rorxS.
 240
 241         * i386-opc.tbl: Correct rorx.
 242         * i386-tbl.h: Regenerated.
 243
 244 2011-06-29  H.J. Lu  <hongjiu.lu@intel.com>
 245
 246         * tilegx-opc.c (find_opcode): Replace "index" with "i".
 247         * tilepro-opc.c (find_opcode): Likewise.
 248
 249 2011-06-29  Richard Sandiford  <rdsandiford@googlemail.com>
 250
 251         * mips16-opc.c (jalrc, jrc): Move earlier in file.
 252
 253 2011-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 254
 255         * i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
 256         PREFIX_VEX_0F388E.
 257
 258 2011-06-17  Andreas Schwab  <schwab@redhat.com>
 259
 260         * Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
 261         (MOSTLYCLEANFILES): ... here.
 262         * Makefile.in: Regenerate.
 263
 264 2011-06-14  Alan Modra  <amodra@gmail.com>
 265
 266         * Makefile.in: Regenerate.
 267
 268 2011-06-13  Walter Lee  <walt@tilera.com>
 269
 270         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
 271         tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
 272         * Makefile.in: Regenerate.
 273         * configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
 274         * configure: Regenerate.
 275         * disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
 276         * po/POTFILES.in: Regenerate.
 277         * tilegx-dis.c: New file.
 278         * tilegx-opc.c: New file.
 279         * tilepro-dis.c: New file.
 280         * tilepro-opc.c: New file.
 281
 282 2011-06-10  H.J. Lu  <hongjiu.lu@intel.com>
 283
 284         AVX Programming Reference (June, 2011)
 285         * i386-dis.c (XMGatherQ): New.
 286         * i386-dis.c (EXxmm_mb): New.
 287         (EXxmm_mb): Likewise.
 288         (EXxmm_mw): Likewise.
 289         (EXxmm_md): Likewise.
 290         (EXxmm_mq): Likewise.
 291         (EXxmmdw): Likewise.
 292         (EXxmmqd): Likewise.
 293         (VexGatherQ): Likewise.
 294         (MVexVSIBDWpX): Likewise.
 295         (MVexVSIBQWpX): Likewise.
 296         (xmm_mb_mode): Likewise.
 297         (xmm_mw_mode): Likewise.
 298         (xmm_md_mode): Likewise.
 299         (xmm_mq_mode): Likewise.
 300         (xmmdw_mode): Likewise.
 301         (xmmqd_mode): Likewise.
 302         (ymmxmm_mode): Likewise.
 303         (vex_vsib_d_w_dq_mode): Likewise.
 304         (vex_vsib_q_w_dq_mode): Likewise.
 305         (MOD_VEX_0F385A_PREFIX_2): Likewise.
 306         (MOD_VEX_0F388C_PREFIX_2): Likewise.
 307         (MOD_VEX_0F388E_PREFIX_2): Likewise.
 308         (PREFIX_0F3882): Likewise.
 309         (PREFIX_VEX_0F3816): Likewise.
 310         (PREFIX_VEX_0F3836): Likewise.
 311         (PREFIX_VEX_0F3845): Likewise.
 312         (PREFIX_VEX_0F3846): Likewise.
 313         (PREFIX_VEX_0F3847): Likewise.
 314         (PREFIX_VEX_0F3858): Likewise.
 315         (PREFIX_VEX_0F3859): Likewise.
 316         (PREFIX_VEX_0F385A): Likewise.
 317         (PREFIX_VEX_0F3878): Likewise.
 318         (PREFIX_VEX_0F3879): Likewise.
 319         (PREFIX_VEX_0F388C): Likewise.
 320         (PREFIX_VEX_0F388E): Likewise.
 321         (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
 322         (PREFIX_VEX_0F38F5): Likewise.
 323         (PREFIX_VEX_0F38F6): Likewise.
 324         (PREFIX_VEX_0F3A00): Likewise.
 325         (PREFIX_VEX_0F3A01): Likewise.
 326         (PREFIX_VEX_0F3A02): Likewise.
 327         (PREFIX_VEX_0F3A38): Likewise.
 328         (PREFIX_VEX_0F3A39): Likewise.
 329         (PREFIX_VEX_0F3A46): Likewise.
 330         (PREFIX_VEX_0F3AF0): Likewise.
 331         (VEX_LEN_0F3816_P_2): Likewise.
 332         (VEX_LEN_0F3819_P_2): Likewise.
 333         (VEX_LEN_0F3836_P_2): Likewise.
 334         (VEX_LEN_0F385A_P_2_M_0): Likewise.
 335         (VEX_LEN_0F38F5_P_0): Likewise.
 336         (VEX_LEN_0F38F5_P_1): Likewise.
 337         (VEX_LEN_0F38F5_P_3): Likewise.
 338         (VEX_LEN_0F38F6_P_3): Likewise.
 339         (VEX_LEN_0F38F7_P_1): Likewise.
 340         (VEX_LEN_0F38F7_P_2): Likewise.
 341         (VEX_LEN_0F38F7_P_3): Likewise.
 342         (VEX_LEN_0F3A00_P_2): Likewise.
 343         (VEX_LEN_0F3A01_P_2): Likewise.
 344         (VEX_LEN_0F3A38_P_2): Likewise.
 345         (VEX_LEN_0F3A39_P_2): Likewise.
 346         (VEX_LEN_0F3A46_P_2): Likewise.
 347         (VEX_LEN_0F3AF0_P_3): Likewise.
 348         (VEX_W_0F3816_P_2): Likewise.
 349         (VEX_W_0F3818_P_2): Likewise.
 350         (VEX_W_0F3819_P_2): Likewise.
 351         (VEX_W_0F3836_P_2): Likewise.
 352         (VEX_W_0F3846_P_2): Likewise.
 353         (VEX_W_0F3858_P_2): Likewise.
 354         (VEX_W_0F3859_P_2): Likewise.
 355         (VEX_W_0F385A_P_2_M_0): Likewise.
 356         (VEX_W_0F3878_P_2): Likewise.
 357         (VEX_W_0F3879_P_2): Likewise.
 358         (VEX_W_0F3A00_P_2): Likewise.
 359         (VEX_W_0F3A01_P_2): Likewise.
 360         (VEX_W_0F3A02_P_2): Likewise.
 361         (VEX_W_0F3A38_P_2): Likewise.
 362         (VEX_W_0F3A39_P_2): Likewise.
 363         (VEX_W_0F3A46_P_2): Likewise.
 364         (MOD_VEX_0F3818_PREFIX_2): Removed.
 365         (MOD_VEX_0F3819_PREFIX_2): Likewise.
 366         (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
 367         (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
 368         (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
 369         (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
 370         (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
 371         (VEX_LEN_0F3A0E_P_2): Likewise.
 372         (VEX_LEN_0F3A0F_P_2): Likewise.
 373         (VEX_LEN_0F3A42_P_2): Likewise.
 374         (VEX_LEN_0F3A4C_P_2): Likewise.
 375         (VEX_W_0F3818_P_2_M_0): Likewise.
 376         (VEX_W_0F3819_P_2_M_0): Likewise.
 377         (prefix_table): Updated.
 378         (three_byte_table): Likewise.
 379         (vex_table): Likewise.
 380         (vex_len_table): Likewise.
 381         (vex_w_table): Likewise.
 382         (mod_table): Likewise.
 383         (putop): Handle "LW".
 384         (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
 385         xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
 386         vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
 387         (OP_EX): Likewise.
 388         (OP_E_memory): Handle vex_vsib_d_w_dq_mode and
 389         vex_vsib_q_w_dq_mode.
 390         (OP_XMM): Handle vex_vsib_q_w_dq_mode.
 391         (OP_VEX): Likewise.
 392
 393         * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
 394         and CPU_ANY_AVX_FLAGS.  Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
 395         CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
 396         (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
 397         (opcode_modifiers): Add VecSIB.
 398
 399         * i386-opc.h (CpuAVX2): New.
 400         (CpuBMI2): Likewise.
 401         (CpuLZCNT): Likewise.
 402         (CpuINVPCID): Likewise.
 403         (VecSIB128): Likewise.
 404         (VecSIB256): Likewise.
 405         (VecSIB): Likewise.
 406         (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
 407         (i386_opcode_modifier): Add vecsib.
 408
 409         * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
 410         * i386-init.h: Regenerated.
 411         * i386-tbl.h: Likewise.
 412
 413 2011-06-03  Quentin Neill  <quentin.neill@amd.com>
 414
 415         * i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
 416         * i386-init.h: Regenerated.
 417
 418 2011-06-03  Nick Clifton  <nickc@redhat.com>
 419
 420         PR binutils/12752
 421         * arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
 422         computing address offsets.
 423         (print_arm_address): Likewise.
 424         (print_insn_arm): Likewise.
 425         (print_insn_thumb16): Likewise.
 426         (print_insn_thumb32): Likewise.
 427
 428 2011-06-02  Jie Zhang <jie@codesourcery.com>
 429             Nathan Sidwell <nathan@codesourcery.com>
 430             Maciej Rozycki <macro@codesourcery.com>
 431
 432         * arm-dis.c (print_insn_coprocessor): Explicitly print #-0
 433         as address offset.
 434         (print_arm_address): Likewise. Elide positive #0 appropriately.
 435         (print_insn_arm): Likewise.
 436
 437 2011-06-02  Nick Clifton  <nickc@redhat.com>
 438
 439         PR gas/12752
 440         * arm-dis.c (print_insn_thumb32): Do not sign extend  addresses
 441         passed to print_address_func.
 442
 443 2011-06-02  Nick Clifton  <nickc@redhat.com>
 444
 445         * arm-dis.c: Fix spelling mistakes.
 446         * op/opcodes.pot: Regenerate.
 447
 448 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 449
 450         * s390-opc.c: Replace S390_OPERAND_REG_EVEN with
 451         S390_OPERAND_REG_PAIR.  Fix INSTR_RRF_0UFEF instruction type.
 452         * s390-opc.txt: Fix cxr instruction type.
 453
 454 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 455
 456         * s390-opc.c: Add new instruction types marking register pair
 457         operands.
 458         * s390-opc.txt: Match instructions having register pair operands
 459         to the new instruction types.
 460
 461 2011-05-19  Nick Clifton  <nickc@redhat.com>
 462
 463         * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
 464         operands.
 465
 466 2011-05-10  Quentin Neill  <quentin.neill@amd.com>
 467
 468         * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
 469         * i386-init.h: Regenerated.
 470
 471 2011-04-27  Nick Clifton  <nickc@redhat.com>
 472
 473         * po/da.po: Updated Danish translation.
 474
 475 2011-04-26  Anton Blanchard  <anton@samba.org>
 476
 477         * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
 478
 479 2011-04-21  DJ Delorie  <dj@redhat.com>
 480
 481         * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
 482         * rx-decode.c: Regenerate.
 483
 484 2011-04-20  H.J. Lu  <hongjiu.lu@intel.com>
 485
 486         * i386-init.h: Regenerated.
 487
 488 2011-04-19  Quentin Neill  <quentin.neill@amd.com>
 489
 490         * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
 491         from bdver1 flags.
 492
 493 2011-04-13  Nick Clifton  <nickc@redhat.com>
 494
 495         * v850-dis.c (disassemble): Always print a closing square brace if
 496         an opening square brace was printed.
 497
 498 2011-04-12  Nick Clifton  <nickc@redhat.com>
 499
 500         PR binutils/12534
 501         * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
 502         patterns.
 503         (print_insn_thumb32): Handle %L.
 504
 505 2011-04-11  Julian Brown  <julian@codesourcery.com>
 506
 507         * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
 508         (print_insn_thumb32): Add APSR bitmask support.
 509
 510 2011-04-07  Paul Carroll<pcarroll@codesourcery.com>
 511
 512         * arm-dis.c (print_insn): init vars moved into private_data structure.
 513
 514 2011-03-24  Mike Frysinger  <vapier@gentoo.org>
 515
 516         * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
 517
 518 2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
 519
 520         * avr-dis.c (avr_operand): Add opcode_str parameter. Check for
 521         post-increment to support LPM Z+ instruction. Add support for 'E'
 522         constraint for DES instruction.
 523         (print_insn_avr): Adjust calls to avr_operand. Rename variable.
 524
 525 2011-03-14  Richard Sandiford  <richard.sandiford@linaro.org>
 526
 527         * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
 528
 529 2011-03-14  Richard Sandiford  <richard.sandiford@linaro.org>
 530
 531         * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
 532         Use branch types instead.
 533         (print_insn): Likewise.
 534
 535 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 536
 537         * mips-opc.c (mips_builtin_opcodes): Correct register use
 538         annotation of "alnv.ps".
 539
 540 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
 541
 542         * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
 543
 544 2011-02-22  Mike Frysinger  <vapier@gentoo.org>
 545
 546         * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
 547
 548 2011-02-22  Mike Frysinger  <vapier@gentoo.org>
 549
 550         * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
 551
 552 2011-02-19  Mike Frysinger  <vapier@gentoo.org>
 553
 554         * bfin-dis.c (saved_state): Mark static.  Change a[01]x to ax[] and
 555         a[01]w to aw[].  Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
 556         av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
 557         exception, end_of_registers, msize, memory, bfd_mach.
 558         (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
 559         LB0REG, LC1REG, LT1REG, LB1REG): Delete
 560         (AXREG, AWREG, LCREG, LTREG, LBREG): Define.
 561         (get_allreg): Change to new defines.  Fallback to abort().
 562
 563 2011-02-14  Mike Frysinger  <vapier@gentoo.org>
 564
 565         * bfin-dis.c: Add whitespace/parenthesis where needed.
 566
 567 2011-02-14  Mike Frysinger  <vapier@gentoo.org>
 568
 569         * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
 570         than 7.
 571
 572 2011-02-13  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
 573
 574         * configure: Regenerate.
 575
 576 2011-02-13  Mike Frysinger  <vapier@gentoo.org>
 577
 578         * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
 579
 580 2011-02-13  Mike Frysinger  <vapier@gentoo.org>
 581
 582         * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1.  Output
 583         dregs only when P is set, and dregs_lo otherwise.
 584
 585 2011-02-13  Mike Frysinger  <vapier@gentoo.org>
 586
 587         * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
 588
 589 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 590
 591         * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
 592
 593 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 594
 595         * bfin-dis.c (machine_registers): Delete REG_GP.
 596         (reg_names): Delete "GP".
 597         (decode_allregs): Change REG_GP to REG_LASTREG.
 598
 599 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
 600
 601         * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
 602         M_IH, M_IU): Delete.
 603
 604 2011-02-11  Mike Frysinger  <vapier@gentoo.org>
 605
 606         * bfin-dis.c (reg_names): Add const.
 607         (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
 608         decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
 609         decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
 610         decode_counters, decode_allregs): Likewise.
 611
 612 2011-02-09  Michael Snyder  <msnyder@vmware.com>
 613
 614         * i386-dis.c (OP_J): Parenthesize expression to prevent
 615         truncated addresses.
 616         (print_insn): Fix indentation off-by-one.
 617
 618 2011-02-01  Nick Clifton  <nickc@redhat.com>
 619
 620         * po/da.po: Updated Danish translation.
 621
 622 2011-01-21  Dave Murphy  <davem@devkitpro.org>
 623
 624         * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
 625
 626 2011-01-18  H.J. Lu  <hongjiu.lu@intel.com>
 627
 628         * i386-dis.c (sIbT): New.
 629         (b_T_mode): Likewise.
 630         (dis386): Replace sIb with sIbT on "pushT".
 631         (x86_64_table): Replace sIb with Ib on "aam" and "aad".
 632         (OP_sI): Handle b_T_mode.  Properly sign-extend byte.
 633
 634 2011-01-18  Jan Kratochvil  <jan.kratochvil@redhat.com>
 635
 636         * i386-init.h: Regenerated.
 637         * i386-tbl.h: Regenerated
 638
 639 2011-01-17  Quentin Neill  <quentin.neill@amd.com>
 640
 641         * i386-dis.c (REG_XOP_TBM_01): New.
 642         (REG_XOP_TBM_02): New.
 643         (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
 644         (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
 645         entries, and add bextr instruction.
 646
 647         * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
 648         (cpu_flags): Add CpuTBM.
 649
 650         * i386-opc.h (CpuTBM) New.
 651         (i386_cpu_flags): Add bit cputbm.
 652
 653         * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
 654         blcs, blsfill, blsic, t1mskc, and tzmsk.
 655
 656 2011-01-12  DJ Delorie  <dj@redhat.com>
 657
 658         * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
 659
 660 2011-01-11  Mingjie Xing  <mingjie.xing@gmail.com>
 661
 662         * mips-dis.c (print_insn_args): Adjust the value to print the real
 663         offset for "+c" argument.
 664
 665 2011-01-10  Nick Clifton  <nickc@redhat.com>
 666
 667         * po/da.po: Updated Danish translation.
 668
 669 2011-01-05  Nathan Sidwell  <nathan@codesourcery.com>
 670
 671         * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
 672
 673 2011-01-04  H.J. Lu  <hongjiu.lu@intel.com>
 674
 675         * i386-dis.c (REG_VEX_38F3): New.
 676         (PREFIX_0FBC): Likewise.
 677         (PREFIX_VEX_38F2): Likewise.
 678         (PREFIX_VEX_38F3_REG_1): Likewise.
 679         (PREFIX_VEX_38F3_REG_2): Likewise.
 680         (PREFIX_VEX_38F3_REG_3): Likewise.
 681         (PREFIX_VEX_38F7): Likewise.
 682         (VEX_LEN_38F2_P_0): Likewise.
 683         (VEX_LEN_38F3_R_1_P_0): Likewise.
 684         (VEX_LEN_38F3_R_2_P_0): Likewise.
 685         (VEX_LEN_38F3_R_3_P_0): Likewise.
 686         (VEX_LEN_38F7_P_0): Likewise.
 687         (dis386_twobyte): Use PREFIX_0FBC.
 688         (reg_table): Add REG_VEX_38F3.
 689         (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
 690         PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
 691         PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
 692         (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
 693         PREFIX_VEX_38F7.
 694         (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
 695         VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
 696         VEX_LEN_38F7_P_0.
 697
 698         * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
 699         (cpu_flags): Add CpuBMI.
 700
 701         * i386-opc.h (CpuBMI): New.
 702         (i386_cpu_flags): Add cpubmi.
 703
 704         * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
 705         * i386-init.h: Regenerated.
 706         * i386-tbl.h: Likewise.
 707
 708 2011-01-04  H.J. Lu  <hongjiu.lu@intel.com>
 709
 710         * i386-dis.c (VexGdq): New.
 711         (OP_VEX): Handle dq_mode.
 712
 713 2011-01-01  H.J. Lu  <hongjiu.lu@intel.com>
 714
 715         * i386-gen.c (process_copyright): Update copyright to 2011.
 716
 717 For older changes see ChangeLog-2010
 718 \f
 719 Local Variables:
 720 mode: change-log
 721 left-margin: 8
 722 fill-column: 74
 723 version-control: never
 724 End: