opcodes/ChangeLog

   1 2019-12-11  Alan Modra  <amodra@gmail.com>
   2
   3         * cris-dis.c (print_with_operands): Avoid signed integer
   4         overflow when collecting bytes of a 32-bit integer.
   5
   6 2019-12-11  Alan Modra  <amodra@gmail.com>
   7
   8         * cr16-dis.c (EXTRACT, SBM): Rewrite.
   9         (cr16_match_opcode): Delete duplicate bcond test.
  10
  11 2019-12-11  Alan Modra  <amodra@gmail.com>
  12
  13         * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
  14         (SIGNBIT): New.
  15         (MASKBITS, SIGNEXTEND): Rewrite.
  16         (fmtconst): Don't use ? expression now that SIGNEXTEND uses
  17         unsigned arithmetic, instead assign result of SIGNEXTEND back
  18         to x.
  19         (fmtconst_val): Use 1u in shift expression.
  20
  21 2019-12-11  Alan Modra  <amodra@gmail.com>
  22
  23         * arc-dis.c (find_format_from_table): Use ull constant when
  24         shifting by up to 32.
  25
  26 2019-12-11  Alan Modra  <amodra@gmail.com>
  27
  28         PR 25270
  29         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
  30         false when field is zero for sve_size_tsz_bhs.
  31
  32 2019-12-11  Alan Modra  <amodra@gmail.com>
  33
  34         * epiphany-ibld.c: Regenerate.
  35
  36 2019-12-10  Alan Modra  <amodra@gmail.com>
  37
  38         PR 24960
  39         * disassemble.c (disassemble_free_target): New function.
  40
  41 2019-12-10  Alan Modra  <amodra@gmail.com>
  42
  43         * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
  44         * disassemble.c (disassemble_init_for_target): Likewise.
  45         * bpf-dis.c: Regenerate.
  46         * epiphany-dis.c: Regenerate.
  47         * fr30-dis.c: Regenerate.
  48         * frv-dis.c: Regenerate.
  49         * ip2k-dis.c: Regenerate.
  50         * iq2000-dis.c: Regenerate.
  51         * lm32-dis.c: Regenerate.
  52         * m32c-dis.c: Regenerate.
  53         * m32r-dis.c: Regenerate.
  54         * mep-dis.c: Regenerate.
  55         * mt-dis.c: Regenerate.
  56         * or1k-dis.c: Regenerate.
  57         * xc16x-dis.c: Regenerate.
  58         * xstormy16-dis.c: Regenerate.
  59
  60 2019-12-10  Alan Modra  <amodra@gmail.com>
  61
  62         * ppc-dis.c (private): Delete variable.
  63         (get_powerpc_dialect): Don't segfault on NULL info->private_data.
  64         (powerpc_init_dialect): Don't use global private.
  65
  66 2019-12-10  Alan Modra  <amodra@gmail.com>
  67
  68         * s12z-opc.c: Formatting.
  69
  70 2019-12-08  Alan Modra  <amodra@gmail.com>
  71
  72         * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
  73         registers.
  74
  75 2019-12-05  Jan Beulich  <jbeulich@suse.com>
  76
  77         * aarch64-tbl.h (aarch64_feature_crypto,
  78         aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
  79         CRYPTO_V8_2_INSN): Delete.
  80
  81 2019-12-05  Alan Modra  <amodra@gmail.com>
  82
  83         PR 25249
  84         * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
  85         (struct string_buf): New.
  86         (strbuf): New function.
  87         (get_field): Use strbuf rather than strdup of local temp.
  88         (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
  89         (get_field_rfsl, get_field_imm15): Likewise.
  90         (get_field_rd, get_field_r1, get_field_r2): Update macros.
  91         (get_field_special): Likewise.  Don't strcpy spr.  Formatting.
  92         (print_insn_microblaze): Formatting.  Init and pass string_buf to
  93         get_field functions.
  94
  95 2019-12-04  Jan Beulich  <jbeulich@suse.com>
  96
  97         * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
  98         * i386-tbl.h: Re-generate.
  99
 100 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 101
 102         * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
 103
 104 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 105
 106         * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
 107         forms.
 108         (xbegin): Drop DefaultSize.
 109         * i386-tbl.h: Re-generate.
 110
 111 2019-11-22  Mihail Ionescu  <mihail.ionescu@arm.com>
 112
 113         * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
 114         Change the coproc CRC conditions to use the extension
 115         feature set, second word, base on ARM_EXT2_CRC.
 116
 117 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 118
 119         * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
 120         * i386-tbl.h: Re-generate.
 121
 122 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 123
 124         * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
 125         JumpInterSegment, and JumpAbsolute entries.
 126         * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
 127         JUMP_ABSOLUTE): Define.
 128         (struct i386_opcode_modifier): Extend jump field to 3 bits.
 129         Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
 130         fields.
 131         * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
 132         JumpInterSegment): Define.
 133         * i386-tbl.h: Re-generate.
 134
 135 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 136
 137         * i386-gen.c (operand_type_init): Remove
 138         OPERAND_TYPE_JUMPABSOLUTE entry.
 139         (opcode_modifiers): Add JumpAbsolute entry.
 140         (operand_types): Remove JumpAbsolute entry.
 141         * i386-opc.h (JumpAbsolute): Move between enums.
 142         (struct i386_opcode_modifier): Add jumpabsolute field.
 143         (union i386_operand_type): Remove jumpabsolute field.
 144         * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
 145         * i386-init.h, i386-tbl.h: Re-generate.
 146
 147 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 148
 149         * i386-gen.c (opcode_modifiers): Add AnySize entry.
 150         (operand_types): Remove AnySize entry.
 151         * i386-opc.h (AnySize): Move between enums.
 152         (struct i386_opcode_modifier): Add anysize field.
 153         (OTUnused): Un-comment.
 154         (union i386_operand_type): Remove anysize field.
 155         * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
 156         prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
 157         bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
 158         AnySize.
 159         * i386-tbl.h: Re-generate.
 160
 161 2019-11-12  Nelson Chu  <nelson.chu@sifive.com>
 162
 163         * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
 164         INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
 165         use the floating point register (FPR).
 166
 167 2019-11-12  Mihail Ionescu  <mihail.ionescu@arm.com>
 168
 169         * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
 170         cmode 1101.
 171         (is_mve_encoding_conflict): Update cmode conflict checks for
 172         MVE_VMVN_IMM.
 173
 174 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 175
 176         * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
 177         entry.
 178         (operand_types): Remove EsSeg entry.
 179         (main): Replace stale use of OTMax.
 180         * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
 181         (struct i386_opcode_modifier): Expand isstring field to 2 bits.
 182         (EsSeg): Delete.
 183         (OTUnused): Comment out.
 184         (union i386_operand_type): Remove esseg field.
 185         * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
 186         (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
 187         (ins, movs, smov, movsd): Add IsStringEsOpOp1.
 188         (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
 189         * i386-init.h, i386-tbl.h: Re-generate.
 190
 191 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 192
 193         * i386-gen.c (operand_instances): Add RegB entry.
 194         * i386-opc.h (enum operand_instance): Add RegB.
 195         * i386-opc.tbl (RegC, RegD, RegB): Define.
 196         (Acc, ShiftCount, InOutPortReg): Adjust definitions.
 197         (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
 198         monitorx, mwaitx): Drop ImmExt and convert encodings
 199         accordingly.
 200         * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
 201         (edx, rdx): Add Instance=RegD.
 202         (ebx, rbx): Add Instance=RegB.
 203         * i386-tbl.h: Re-generate.
 204
 205 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 206
 207         * i386-gen.c (operand_type_init): Adjust
 208         OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
 209         OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
 210         OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
 211         (operand_instances): New.
 212         (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
 213         (output_operand_type): New parameter "instance". Process it.
 214         (process_i386_operand_type): New local variable "instance".
 215         (main): Adjust static assertions.
 216         * i386-opc.h (INSTANCE_WIDTH): Define.
 217         (enum operand_instance): New.
 218         (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
 219         (union i386_operand_type): Replace acc, inoutportreg, and
 220         shiftcount by instance.
 221         * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
 222         * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
 223         Add Instance=.
 224         * i386-init.h, i386-tbl.h: Re-generate.
 225
 226 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 227
 228         * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
 229         smaxp/sminp entries' "tied_operand" field to 2.
 230
 231 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 232
 233         * aarch64-opc.c (operand_general_constraint_met_p): Replace
 234         "index" local variable by that of the already existing "num".
 235
 236 2019-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 237
 238         PR gas/25167
 239         * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
 240         * i386-tbl.h: Regenerated.
 241
 242 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 243
 244         * i386-gen.c (operand_type_init): Add Class= to
 245         OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
 246         OPERAND_TYPE_REGBND entry.
 247         (operand_classes): Add RegMask and RegBND entries.
 248         (operand_types): Drop RegMask and RegBND entry.
 249         * i386-opc.h (enum operand_class): Add RegMask and RegBND.
 250         (RegMask, RegBND): Delete.
 251         (union i386_operand_type): Remove regmask and regbnd fields.
 252         * i386-opc.tbl (RegMask, RegBND): Define.
 253         * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
 254         Class=RegBND.
 255         * i386-init.h, i386-tbl.h: Re-generate.
 256
 257 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 258
 259         * i386-gen.c (operand_type_init): Add Class= to
 260         OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
 261         OPERAND_TYPE_REGZMM entries.
 262         (operand_classes): Add RegMMX and RegSIMD entries.
 263         (operand_types): Drop RegMMX and RegSIMD entries.
 264         * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
 265         (RegMMX, RegSIMD): Delete.
 266         (union i386_operand_type): Remove regmmx and regsimd fields.
 267         * i386-opc.tbl (RegMMX): Define.
 268         (RegXMM, RegYMM, RegZMM): Add Class=.
 269         * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
 270         Class=RegSIMD.
 271         * i386-init.h, i386-tbl.h: Re-generate.
 272
 273 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 274
 275         * i386-gen.c (operand_type_init): Add Class= to
 276         OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
 277         entries.
 278         (operand_classes): Add RegCR, RegDR, and RegTR entries.
 279         (operand_types): Drop Control, Debug, and Test entries.
 280         * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
 281         (Control, Debug, Test): Delete.
 282         (union i386_operand_type): Remove control, debug, and test
 283         fields.
 284         * i386-opc.tbl (Control, Debug, Test): Define.
 285         * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
 286         Class=RegDR, and Test by Class=RegTR.
 287         * i386-init.h, i386-tbl.h: Re-generate.
 288
 289 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 290
 291         * i386-gen.c (operand_type_init): Add Class= to
 292         OPERAND_TYPE_SREG entry.
 293         (operand_classes): Add SReg entry.
 294         (operand_types): Drop SReg entry.
 295         * i386-opc.h (enum operand_class): Add SReg.
 296         (SReg): Delete.
 297         (union i386_operand_type): Remove sreg field.
 298         * i386-opc.tbl (SReg): Define.
 299         * i386-reg.tbl: Replace SReg by Class=SReg.
 300         * i386-init.h, i386-tbl.h: Re-generate.
 301
 302 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 303
 304         * i386-gen.c (operand_type_init): Add Class=. New
 305         OPERAND_TYPE_ANYIMM entry.
 306         (operand_classes): New.
 307         (operand_types): Drop Reg entry.
 308         (output_operand_type): New parameter "class". Process it.
 309         (process_i386_operand_type): New local variable "class".
 310         (main): Adjust static assertions.
 311         * i386-opc.h (CLASS_WIDTH): Define.
 312         (enum operand_class): New.
 313         (Reg): Replace by Class. Adjust comment.
 314         (union i386_operand_type): Replace reg by class.
 315         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
 316         Class=.
 317         * i386-reg.tbl: Replace Reg by Class=Reg.
 318         * i386-init.h: Re-generate.
 319
 320 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 321
 322         * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
 323         (aarch64_opcode_table): Add data gathering hint mnemonic.
 324         * opcodes/aarch64-dis-2.c: Account for new instruction.
 325
 326 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 327
 328         * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
 329
 330
 331 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 332
 333         * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
 334         aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
 335         aarch64_feature_f64mm): New feature sets.
 336         (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
 337         F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
 338         instructions.
 339         (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
 340         macros.
 341         (QL_MMLA64, OP_SVE_SBB): New qualifiers.
 342         (OP_SVE_QQQ): New qualifier.
 343         (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
 344         F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
 345         the movprfx constraint.
 346         (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
 347         (aarch64_opcode_table): Define new instructions smmla,
 348         ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
 349         uzip{1/2}, trn{1/2}.
 350         * aarch64-opc.c (operand_general_constraint_met_p): Handle
 351         AARCH64_OPND_SVE_ADDR_RI_S4x32.
 352         (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
 353         * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
 354         Account for new instructions.
 355         * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
 356         S4x32 operand.
 357         * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
 358
 359 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 360 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 361
 362         * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
 363         Armv8.6-A.
 364         (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
 365         (neon_opcodes): Add bfloat SIMD instructions.
 366         (print_insn_coprocessor): Add new control character %b to print
 367         condition code without checking cp_num.
 368         (print_insn_neon): Account for BFloat16 instructions that have no
 369         special top-byte handling.
 370
 371 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 372 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 373
 374         * arm-dis.c (print_insn_coprocessor,
 375         print_insn_generic_coprocessor): Create wrapper functions around
 376         the implementation of the print_insn_coprocessor control codes.
 377         (print_insn_coprocessor_1): Original print_insn_coprocessor
 378         function that now takes which array to look at as an argument.
 379         (print_insn_arm): Use both print_insn_coprocessor and
 380         print_insn_generic_coprocessor.
 381         (print_insn_thumb32): As above.
 382
 383 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 384 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 385
 386         * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
 387         in reglane special case.
 388         * aarch64-dis-2.c (aarch64_opcode_lookup_1,
 389         aarch64_find_next_opcode): Account for new instructions.
 390         * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
 391         in reglane special case.
 392         * aarch64-opc.c (struct operand_qualifier_data): Add data for
 393         new AARCH64_OPND_QLF_S_2H qualifier.
 394         * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
 395         QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
 396         (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
 397         sets.
 398         (BFLOAT_SVE, BFLOAT): New feature set macros.
 399         (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
 400         instructions.
 401         (aarch64_opcode_table): Define new instructions bfdot,
 402         bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
 403         bfcvtn2, bfcvt.
 404
 405 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 406 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 407
 408         * aarch64-tbl.h (ARMV8_6): New macro.
 409
 410 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 411
 412         * i386-dis.c (prefix_table): Add mcommit.
 413         (rm_table): Add rdpru.
 414         * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
 415         CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
 416         (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
 417         * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
 418         (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
 419         * i386-opc.tbl (mcommit, rdpru): New.
 420         * i386-init.h, i386-tbl.h: Re-generate.
 421
 422 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 423
 424         * i386-dis.c (OP_Mwait): Drop local variable "names", use
 425         "names32" instead.
 426         (OP_Monitor): Drop local variable "op1_names", re-purpose
 427         "names" for it instead, and replace former "names" uses by
 428         "names32" ones.
 429
 430 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 431
 432         PR/gas 25167
 433         * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
 434         operand-less forms.
 435         * opcodes/i386-tbl.h: Re-generate.
 436
 437 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 438
 439         * i386-dis.c (OP_Mwaitx): Delete.
 440         (prefix_table): Use OP_Mwait for mwaitx entry.
 441         (OP_Mwait): Also handle mwaitx.
 442
 443 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 444
 445         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
 446         PREFIX_0F01_REG_7_MOD_3_RM_3): New.
 447         (prefix_table): Add respective entries.
 448         (rm_table): Link to those entries.
 449
 450 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 451
 452         * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
 453         (REG_0F1C_P_0_MOD_0): ... this.
 454         (REG_0F1E_MOD_3): Rename to ...
 455         (REG_0F1E_P_1_MOD_3): ... this.
 456         (RM_0F01_REG_5): Rename to ...
 457         (RM_0F01_REG_5_MOD_3): ... this.
 458         (RM_0F01_REG_7): Rename to ...
 459         (RM_0F01_REG_7_MOD_3): ... this.
 460         (RM_0F1E_MOD_3_REG_7): Rename to ...
 461         (RM_0F1E_P_1_MOD_3_REG_7): ... this.
 462         (RM_0FAE_REG_6): Rename to ...
 463         (RM_0FAE_REG_6_MOD_3_P_0): ... this.
 464         (RM_0FAE_REG_7): Rename to ...
 465         (RM_0FAE_REG_7_MOD_3): ... this.
 466         (PREFIX_MOD_0_0F01_REG_5): Rename to ...
 467         (PREFIX_0F01_REG_5_MOD_0): ... this.
 468         (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
 469         (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
 470         (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
 471         (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
 472         (PREFIX_0FAE_REG_0): Rename to ...
 473         (PREFIX_0FAE_REG_0_MOD_3): ... this.
 474         (PREFIX_0FAE_REG_1): Rename to ...
 475         (PREFIX_0FAE_REG_1_MOD_3): ... this.
 476         (PREFIX_0FAE_REG_2): Rename to ...
 477         (PREFIX_0FAE_REG_2_MOD_3): ... this.
 478         (PREFIX_0FAE_REG_3): Rename to ...
 479         (PREFIX_0FAE_REG_3_MOD_3): ... this.
 480         (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
 481         (PREFIX_0FAE_REG_4_MOD_0): ... this.
 482         (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
 483         (PREFIX_0FAE_REG_4_MOD_3): ... this.
 484         (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
 485         (PREFIX_0FAE_REG_5_MOD_0): ... this.
 486         (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
 487         (PREFIX_0FAE_REG_5_MOD_3): ... this.
 488         (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
 489         (PREFIX_0FAE_REG_6_MOD_0): ... this.
 490         (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
 491         (PREFIX_0FAE_REG_6_MOD_3): ... this.
 492         (PREFIX_0FAE_REG_7): Rename to ...
 493         (PREFIX_0FAE_REG_7_MOD_0): ... this.
 494         (PREFIX_MOD_0_0FC3): Rename to ...
 495         (PREFIX_0FC3_MOD_0): ... this.
 496         (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
 497         (PREFIX_0FC7_REG_6_MOD_0): ... this.
 498         (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
 499         (PREFIX_0FC7_REG_6_MOD_3): ... this.
 500         (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
 501         (PREFIX_0FC7_REG_7_MOD_3): ... this.
 502         (reg_table, prefix_table, mod_table, rm_table): Adjust
 503         accordingly.
 504
 505 2019-11-04  Nick Clifton  <nickc@redhat.com>
 506
 507         * v850-dis.c (get_v850_sreg_name): New function.  Returns the name
 508         of a v850 system register.  Move the v850_sreg_names array into
 509         this function.
 510         (get_v850_reg_name): Likewise for ordinary register names.
 511         (get_v850_vreg_name): Likewise for vector register names.
 512         (get_v850_cc_name): Likewise for condition codes.
 513         * get_v850_float_cc_name): Likewise for floating point condition
 514         codes.
 515         (get_v850_cacheop_name): Likewise for cache-ops.
 516         (get_v850_prefop_name): Likewise for pref-ops.
 517         (disassemble): Use the new accessor functions.
 518
 519 2019-10-30  Delia Burduv   <delia.burduv@arm.com>
 520
 521         * aarch64-opc.c (print_immediate_offset_address): Don't print the
 522         immediate for the writeback form of ldraa/ldrab if it is 0.
 523         * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
 524         * aarch64-opc-2.c: Regenerated.
 525
 526 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 527
 528         * i386-gen.c (operand_type_shorthands): Delete.
 529         (operand_type_init): Expand previous shorthands.
 530         (set_bitfield_from_shorthand): Rename back to ...
 531         (set_bitfield_from_cpu_flag_init): ... this.  Drop processing
 532         of operand_type_init[].
 533         (set_bitfield): Adjust call to the above function.
 534         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
 535         RegXMM, RegYMM, RegZMM): Define.
 536         * i386-reg.tbl: Expand prior shorthands.
 537
 538 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 539
 540         * i386-gen.c (output_i386_opcode): Change order of fields
 541         emitted to output.
 542         * i386-opc.h (struct insn_template): Move operands field.
 543         Convert extension_opcode field to unsigned short.
 544         * i386-tbl.h: Re-generate.
 545
 546 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 547
 548         * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
 549         of W.
 550         * i386-opc.h (W): Extend comment.
 551         * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
 552         general purpose variants not allowing for byte operands.
 553         * i386-tbl.h: Re-generate.
 554
 555 2019-10-29  Nick Clifton  <nickc@redhat.com>
 556
 557         * tic30-dis.c (print_branch): Correct size of operand array.
 558
 559 2019-10-29  Nick Clifton  <nickc@redhat.com>
 560
 561         * d30v-dis.c (print_insn): Check that operand index is valid
 562         before attempting to access the operands array.
 563
 564 2019-10-29  Nick Clifton  <nickc@redhat.com>
 565
 566         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
 567         locating the bit to be tested.
 568
 569 2019-10-29  Nick Clifton  <nickc@redhat.com>
 570
 571         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
 572         values.
 573         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
 574         (print_insn_s12z):  Check for illegal size values.
 575
 576 2019-10-28  Nick Clifton  <nickc@redhat.com>
 577
 578         * csky-dis.c (csky_chars_to_number): Check for a negative
 579         count. Use an unsigned integer to construct the return value.
 580
 581 2019-10-28  Nick Clifton  <nickc@redhat.com>
 582
 583         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
 584         operand buffer.  Set value to 15 not 13.
 585         (get_register_operand): Use OPERAND_BUFFER_LEN.
 586         (get_indirect_operand): Likewise.
 587         (print_two_operand): Likewise.
 588         (print_three_operand): Likewise.
 589         (print_oar_insn): Likewise.
 590
 591 2019-10-28  Nick Clifton  <nickc@redhat.com>
 592
 593         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
 594         (bit_extract_simple): Likewise.
 595         (bit_copy): Likewise.
 596         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
 597         index_offset array are not accessed.
 598
 599 2019-10-28  Nick Clifton  <nickc@redhat.com>
 600
 601         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
 602         operand.
 603
 604 2019-10-25  Nick Clifton  <nickc@redhat.com>
 605
 606         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
 607         access to opcodes.op array element.
 608
 609 2019-10-23  Nick Clifton  <nickc@redhat.com>
 610
 611         * rx-dis.c (get_register_name): Fix spelling typo in error
 612         message.
 613         (get_condition_name, get_flag_name, get_double_register_name)
 614         (get_double_register_high_name, get_double_register_low_name)
 615         (get_double_control_register_name, get_double_condition_name)
 616         (get_opsize_name, get_size_name): Likewise.
 617
 618 2019-10-22  Nick Clifton  <nickc@redhat.com>
 619
 620         * rx-dis.c (get_size_name): New function.  Provides safe
 621         access to name array.
 622         (get_opsize_name): Likewise.
 623         (print_insn_rx): Use the accessor functions.
 624
 625 2019-10-16  Nick Clifton  <nickc@redhat.com>
 626
 627         * rx-dis.c (get_register_name): New function.  Provides safe
 628         access to name array.
 629         (get_condition_name, get_flag_name, get_double_register_name)
 630         (get_double_register_high_name, get_double_register_low_name)
 631         (get_double_control_register_name, get_double_condition_name):
 632         Likewise.
 633         (print_insn_rx): Use the accessor functions.
 634
 635 2019-10-09  Nick Clifton  <nickc@redhat.com>
 636
 637         PR 25041
 638         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
 639         instructions.
 640
 641 2019-10-07  Jan Beulich  <jbeulich@suse.com>
 642
 643         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
 644         (cmpsd): Likewise. Move EsSeg to other operand.
 645         * opcodes/i386-tbl.h: Re-generate.
 646
 647 2019-09-23  Alan Modra  <amodra@gmail.com>
 648
 649         * m68k-dis.c: Include cpu-m68k.h
 650
 651 2019-09-23  Alan Modra  <amodra@gmail.com>
 652
 653         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
 654         "elf/mips.h" earlier.
 655
 656 2018-09-20  Jan Beulich  <jbeulich@suse.com>
 657
 658         PR gas/25012
 659         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 660         with SReg operand.
 661         * i386-tbl.h: Re-generate.
 662
 663 2019-09-18  Alan Modra  <amodra@gmail.com>
 664
 665         * arc-ext.c: Update throughout for bfd section macro changes.
 666
 667 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 668
 669         * Makefile.in: Re-generate.
 670         * configure: Re-generate.
 671
 672 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 673
 674         * riscv-opc.c (riscv_opcodes): Change subset field
 675         to insn_class field for all instructions.
 676         (riscv_insn_types): Likewise.
 677
 678 2019-09-16  Phil Blundell  <pb@pbcl.net>
 679
 680         * configure: Regenerated.
 681
 682 2019-09-10  Miod Vallat  <miod@online.fr>
 683
 684         PR 24982
 685         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 686
 687 2019-09-09  Phil Blundell  <pb@pbcl.net>
 688
 689         binutils 2.33 branch created.
 690
 691 2019-09-03  Nick Clifton  <nickc@redhat.com>
 692
 693         PR 24961
 694         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 695         greater than zero before indexing via (bufcnt -1).
 696
 697 2019-09-03  Nick Clifton  <nickc@redhat.com>
 698
 699         PR 24958
 700         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 701         (MAX_SPEC_REG_NAME_LEN): Define.
 702         (struct mmix_dis_info): Use defined constants for array lengths.
 703         (get_reg_name): New function.
 704         (get_sprec_reg_name): New function.
 705         (print_insn_mmix): Use new functions.
 706
 707 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 708
 709         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 710         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 711         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 712
 713 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 714
 715         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 716         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 717         (aarch64_sys_reg_supported_p): Update checks for the above.
 718
 719 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 720
 721         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 722         cases MVE_SQRSHRL and MVE_UQRSHLL.
 723         (print_insn_mve): Add case for specifier 'k' to check
 724         specific bit of the instruction.
 725
 726 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 727
 728         PR 24854
 729         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 730         encountering an unknown machine type.
 731         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 732         cases return -1 rather than calling abort.
 733
 734 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 735
 736         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 737         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 738         IgnoreSize.
 739         * i386-tbl.h: Re-generate.
 740
 741 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 742
 743         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 744         instructions.
 745
 746 2019-07-30  Mel Chen <mel.chen@sifive.com>
 747
 748         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 749         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 750
 751         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 752         fscsr.
 753
 754 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 755
 756         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 757         and MPY class instructions.
 758         (parse_option): Add nps400 option.
 759         (print_arc_disassembler_options): Add nps400 info.
 760
 761 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 762
 763         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 764         (bspop): Likewise.
 765         (modapp): Likewise.
 766         * arc-opc.c (RAD_CHK): Add.
 767         * arc-tbl.h: Regenerate.
 768
 769 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 770
 771         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 772         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 773
 774 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 775
 776         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 777         instructions as UNPREDICTABLE.
 778
 779 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 780
 781         * bpf-desc.c: Regenerated.
 782
 783 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 784
 785         * i386-gen.c (static_assert): Define.
 786         (main): Use it.
 787         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 788         (Opcode_Modifier_Num): ... this.
 789         (Mem): Delete.
 790
 791 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 792
 793         * i386-gen.c (operand_types): Move RegMem ...
 794         (opcode_modifiers): ... here.
 795         * i386-opc.h (RegMem): Move to opcode modifer enum.
 796         (union i386_operand_type): Move regmem field ...
 797         (struct i386_opcode_modifier): ... here.
 798         * i386-opc.tbl (RegMem): Define.
 799         (mov, movq): Move RegMem on segment, control, debug, and test
 800         register flavors.
 801         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 802         to non-SSE2AVX flavor.
 803         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 804         Move RegMem on register only flavors. Drop IgnoreSize from
 805         legacy encoding flavors.
 806         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 807         flavors.
 808         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 809         register only flavors.
 810         (vmovd): Move RegMem and drop IgnoreSize on register only
 811         flavor. Change opcode and operand order to store form.
 812         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 813
 814 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 815
 816         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 817         entries.
 818         * i386-opc.h (SReg2, SReg3): Replace by ...
 819         (SReg): ... this.
 820         (union i386_operand_type): Replace sreg fields.
 821         * i386-opc.tbl (mov, ): Use SReg.
 822         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 823         register flavors.
 824         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 825         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 826
 827 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 828
 829         * bpf-desc.c: Regenerate.
 830         * bpf-opc.c: Likewise.
 831         * bpf-opc.h: Likewise.
 832
 833 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 834
 835         * bpf-desc.c: Regenerate.
 836         * bpf-opc.c: Likewise.
 837
 838 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 839
 840         * arm-dis.c (print_insn_coprocessor): Rename index to
 841         index_operand.
 842
 843 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 844
 845         * riscv-opc.c (riscv_insn_types): Add r4 type.
 846
 847         * riscv-opc.c (riscv_insn_types): Add b and j type.
 848
 849         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 850         format for sb type and correct s type.
 851
 852 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 853
 854         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 855         SVE FMOV alias of FCPY.
 856
 857 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 858
 859         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 860         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 861
 862 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 863
 864         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 865         registers in an instruction prefixed by MOVPRFX.
 866
 867 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 868
 869         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 870         sve_size_13 icode to account for variant behaviour of
 871         pmull{t,b}.
 872         * aarch64-dis-2.c: Regenerate.
 873         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 874         sve_size_13 icode to account for variant behaviour of
 875         pmull{t,b}.
 876         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 877         (OP_SVE_VVV_Q_D): Add new qualifier.
 878         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 879         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 880         AES and those not.
 881
 882 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 883
 884         * opcodes/i386-gen.c (operand_type_init): Remove
 885         OPERAND_TYPE_VEC_IMM4 entry.
 886         (operand_types): Remove Vec_Imm4.
 887         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 888         (union i386_operand_type): Remove vec_imm4.
 889         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 890         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 891
 892 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 893
 894         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 895         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 896         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 897         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 898         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 899         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 900         * i386-tbl.h: Re-generate.
 901
 902 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 903
 904         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 905         register operands.
 906         * i386-tbl.h: Re-generate.
 907
 908 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 909
 910         * i386-opc.tbl (C): New.
 911         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 912         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 913         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 914         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 915         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 916         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 917         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 918         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 919         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 920         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 921         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 922         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 923         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 924         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 925         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 926         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 927         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 928         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 929         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 930         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 931         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 932         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 933         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 934         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 935         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 936         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 937         flavors.
 938         * i386-tbl.h: Re-generate.
 939
 940 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 941
 942         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 943         register operands.
 944         * i386-tbl.h: Re-generate.
 945
 946 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 947
 948         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 949         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 950         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 951         * i386-tbl.h: Re-generate.
 952
 953 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 954
 955         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 956         Disp8MemShift from register only templates.
 957         * i386-tbl.h: Re-generate.
 958
 959 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 960
 961         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 962         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 963         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 964         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 965         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 966         EVEX_W_0F11_P_3_M_1): Delete.
 967         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 968         EVEX_W_0F11_P_3): New.
 969         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 970         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 971         MOD_EVEX_0F11_PREFIX_3 table entries.
 972         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 973         PREFIX_EVEX_0F11 table entries.
 974         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 975         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 976         EVEX_W_0F11_P_3_M_{0,1} table entries.
 977
 978 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 979
 980         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 981         Delete.
 982
 983 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 984
 985         PR binutils/24719
 986         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 987         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 988         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 989         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 990         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 991         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 992         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 993         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 994         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 995         PREFIX_EVEX_0F38C6_REG_6 entries.
 996         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 997         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 998         EVEX_W_0F38C7_R_6_P_2 entries.
 999         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1000         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1001         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1002         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1003         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1004         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1005         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1006
1007 2019-06-27  Jan Beulich  <jbeulich@suse.com>
1008
1009         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1010         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1011         VEX_LEN_0F2D_P_3): Delete.
1012         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1013         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1014         (prefix_table): ... here.
1015
1016 2019-06-27  Jan Beulich  <jbeulich@suse.com>
1017
1018         * i386-dis.c (Iq): Delete.
1019         (Id): New.
1020         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1021         TBM insns.
1022         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1023         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1024         (OP_E_memory): Also honor needindex when deciding whether an
1025         address size prefix needs printing.
1026         (OP_I): Remove handling of q_mode. Add handling of d_mode.
1027
1028 2019-06-26  Jim Wilson  <jimw@sifive.com>
1029
1030         PR binutils/24739
1031         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1032         Set info->display_endian to info->endian_code.
1033
1034 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1035
1036         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1037         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1038         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1039         OPERAND_TYPE_ACC64 entries.
1040         * i386-init.h: Re-generate.
1041
1042 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1043
1044         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1045         Delete.
1046         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1047         of dqa_mode.
1048         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1049         entries here.
1050         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1051         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1052
1053 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1054
1055         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1056         variables.
1057
1058 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1059
1060         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1061         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1062         movnti.
1063         * i386-opc.tbl (movnti): Add IgnoreSize.
1064         * i386-tbl.h: Re-generate.
1065
1066 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1067
1068         * i386-opc.tbl (and): Mark Imm8S form for optimization.
1069         * i386-tbl.h: Re-generate.
1070
1071 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
1072
1073         * i386-dis-evex.h: Break into ...
1074         * i386-dis-evex-len.h: New file.
1075         * i386-dis-evex-mod.h: Likewise.
1076         * i386-dis-evex-prefix.h: Likewise.
1077         * i386-dis-evex-reg.h: Likewise.
1078         * i386-dis-evex-w.h: Likewise.
1079         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1080         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1081         i386-dis-evex-mod.h.
1082
1083 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
1084
1085         PR binutils/24700
1086         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1087         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1088         EVEX_W_0F385B_P_2.
1089         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1090         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1091         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1092         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1093         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1094         EVEX_LEN_0F385B_P_2_W_1.
1095         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1096         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1097         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1098         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1099         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1100         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1101         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1102         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1103         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1104         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1105
1106 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
1107
1108         PR binutils/24691
1109         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1110         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1111         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1112         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1113         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1114         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1115         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1116         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1117         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1118         EVEX_LEN_0F3A43_P_2_W_1.
1119         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1120         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1121         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1122         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1123         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1124         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1125         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1126         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1127         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1128         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1129         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1130         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1131
1132 2019-06-14  Nick Clifton  <nickc@redhat.com>
1133
1134         * po/fr.po; Updated French translation.
1135
1136 2019-06-13  Stafford Horne  <shorne@gmail.com>
1137
1138         * or1k-asm.c: Regenerated.
1139         * or1k-desc.c: Regenerated.
1140         * or1k-desc.h: Regenerated.
1141         * or1k-dis.c: Regenerated.
1142         * or1k-ibld.c: Regenerated.
1143         * or1k-opc.c: Regenerated.
1144         * or1k-opc.h: Regenerated.
1145         * or1k-opinst.c: Regenerated.
1146
1147 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
1148
1149         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1150
1151 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
1152
1153         PR binutils/24633
1154         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1155         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1156         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1157         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1158         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1159         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1160         EVEX_LEN_0F3A1B_P_2_W_1.
1161         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1162         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1163         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1164         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1165         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1166         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1167         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1168         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1169
1170 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
1171
1172         PR binutils/24626
1173         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1174         EVEX.vvvv when disassembling VEX and EVEX instructions.
1175         (OP_VEX): Set vex.register_specifier to 0 after readding
1176         vex.register_specifier.
1177         (OP_Vex_2src_1): Likewise.
1178         (OP_Vex_2src_2): Likewise.
1179         (OP_LWP_E): Likewise.
1180         (OP_EX_Vex): Don't check vex.register_specifier.
1181         (OP_XMM_Vex): Likewise.
1182
1183 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1184             Lili Cui  <lili.cui@intel.com>
1185
1186         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1187         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1188         instructions.
1189         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1190         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1191         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1192         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1193         (i386_cpu_flags): Add cpuavx512_vp2intersect.
1194         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1195         * i386-init.h: Regenerated.
1196         * i386-tbl.h: Likewise.
1197
1198 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
1199             Lili Cui  <lili.cui@intel.com>
1200
1201         * doc/c-i386.texi: Document enqcmd.
1202         * testsuite/gas/i386/enqcmd-intel.d: New file.
1203         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1204         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1205         * testsuite/gas/i386/enqcmd.d: Likewise.
1206         * testsuite/gas/i386/enqcmd.s: Likewise.
1207         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1208         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1209         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1210         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1211         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1212         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1213         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1214         and x86-64-enqcmd.
1215
1216 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
1217
1218         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1219
1220 2019-06-03  Alan Modra  <amodra@gmail.com>
1221
1222         * ppc-dis.c (prefix_opcd_indices): Correct size.
1223
1224 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
1225
1226         PR gas/24625
1227         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1228         Disp8ShiftVL.
1229         * i386-tbl.h: Regenerated.
1230
1231 2019-05-24  Alan Modra  <amodra@gmail.com>
1232
1233         * po/POTFILES.in: Regenerate.
1234
1235 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1236             Alan Modra  <amodra@gmail.com>
1237
1238         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1239         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1240         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1241         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1242         XTOP>): Define and add entries.
1243         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1244         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1245         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1246         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1247
1248 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1249             Alan Modra  <amodra@gmail.com>
1250
1251         * ppc-dis.c (ppc_opts): Add "future" entry.
1252         (PREFIX_OPCD_SEGS): Define.
1253         (prefix_opcd_indices): New array.
1254         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1255         (lookup_prefix): New function.
1256         (print_insn_powerpc): Handle 64-bit prefix instructions.
1257         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1258         (PMRR, POWERXX): Define.
1259         (prefix_opcodes): New instruction table.
1260         (prefix_num_opcodes): New constant.
1261
1262 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
1263
1264         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1265         * configure: Regenerated.
1266         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1267         and cpu/bpf.opc.
1268         (HFILES): Add bpf-desc.h and bpf-opc.h.
1269         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1270         bpf-ibld.c and bpf-opc.c.
1271         (BPF_DEPS): Define.
1272         * Makefile.in: Regenerated.
1273         * disassemble.c (ARCH_bpf): Define.
1274         (disassembler): Add case for bfd_arch_bpf.
1275         (disassemble_init_for_target): Likewise.
1276         (enum epbf_isa_attr): Define.
1277         * disassemble.h: extern print_insn_bpf.
1278         * bpf-asm.c: Generated.
1279         * bpf-opc.h: Likewise.
1280         * bpf-opc.c: Likewise.
1281         * bpf-ibld.c: Likewise.
1282         * bpf-dis.c: Likewise.
1283         * bpf-desc.h: Likewise.
1284         * bpf-desc.c: Likewise.
1285
1286 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1287
1288         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1289         and VMSR with the new operands.
1290
1291 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1292
1293         * arm-dis.c (enum mve_instructions): New enum
1294         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1295         and cneg.
1296         (mve_opcodes): New instructions as above.
1297         (is_mve_encoding_conflict): Add cases for csinc, csinv,
1298         csneg and csel.
1299         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1300
1301 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1302
1303         * arm-dis.c (emun mve_instructions): Updated for new instructions.
1304         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1305         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1306         uqshl, urshrl and urshr.
1307         (is_mve_okay_in_it): Add new instructions to TRUE list.
1308         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1309         (print_insn_mve): Updated to accept new %j,
1310         %<bitfield>m and %<bitfield>n patterns.
1311
1312 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1313
1314         * mips-opc.c (mips_builtin_opcodes): Change source register
1315         constraint for DAUI.
1316
1317 2019-05-20  Nick Clifton  <nickc@redhat.com>
1318
1319         * po/fr.po: Updated French translation.
1320
1321 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1322             Michael Collison <michael.collison@arm.com>
1323
1324         * arm-dis.c (thumb32_opcodes): Add new instructions.
1325         (enum mve_instructions): Likewise.
1326         (enum mve_undefined): Add new reasons.
1327         (is_mve_encoding_conflict): Handle new instructions.
1328         (is_mve_undefined): Likewise.
1329         (is_mve_unpredictable): Likewise.
1330         (print_mve_undefined): Likewise.
1331         (print_mve_size): Likewise.
1332
1333 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1334             Michael Collison <michael.collison@arm.com>
1335
1336         * arm-dis.c (thumb32_opcodes): Add new instructions.
1337         (enum mve_instructions): Likewise.
1338         (is_mve_encoding_conflict): Handle new instructions.
1339         (is_mve_undefined): Likewise.
1340         (is_mve_unpredictable): Likewise.
1341         (print_mve_size): Likewise.
1342
1343 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1344             Michael Collison <michael.collison@arm.com>
1345
1346         * arm-dis.c (thumb32_opcodes): Add new instructions.
1347         (enum mve_instructions): Likewise.
1348         (is_mve_encoding_conflict): Likewise.
1349         (is_mve_unpredictable): Likewise.
1350         (print_mve_size): Likewise.
1351
1352 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1353             Michael Collison <michael.collison@arm.com>
1354
1355         * arm-dis.c (thumb32_opcodes): Add new instructions.
1356         (enum mve_instructions): Likewise.
1357         (is_mve_encoding_conflict): Handle new instructions.
1358         (is_mve_undefined): Likewise.
1359         (is_mve_unpredictable): Likewise.
1360         (print_mve_size): Likewise.
1361
1362 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1363             Michael Collison <michael.collison@arm.com>
1364
1365         * arm-dis.c (thumb32_opcodes): Add new instructions.
1366         (enum mve_instructions): Likewise.
1367         (is_mve_encoding_conflict): Handle new instructions.
1368         (is_mve_undefined): Likewise.
1369         (is_mve_unpredictable): Likewise.
1370         (print_mve_size): Likewise.
1371         (print_insn_mve): Likewise.
1372
1373 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1374             Michael Collison <michael.collison@arm.com>
1375
1376         * arm-dis.c (thumb32_opcodes): Add new instructions.
1377         (print_insn_thumb32): Handle new instructions.
1378
1379 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1380             Michael Collison <michael.collison@arm.com>
1381
1382         * arm-dis.c (enum mve_instructions): Add new instructions.
1383         (enum mve_undefined): Add new reasons.
1384         (is_mve_encoding_conflict): Handle new instructions.
1385         (is_mve_undefined): Likewise.
1386         (is_mve_unpredictable): Likewise.
1387         (print_mve_undefined): Likewise.
1388         (print_mve_size): Likewise.
1389         (print_mve_shift_n): Likewise.
1390         (print_insn_mve): Likewise.
1391
1392 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1393             Michael Collison <michael.collison@arm.com>
1394
1395         * arm-dis.c (enum mve_instructions): Add new instructions.
1396         (is_mve_encoding_conflict): Handle new instructions.
1397         (is_mve_unpredictable): Likewise.
1398         (print_mve_rotate): Likewise.
1399         (print_mve_size): Likewise.
1400         (print_insn_mve): Likewise.
1401
1402 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1403             Michael Collison <michael.collison@arm.com>
1404
1405         * arm-dis.c (enum mve_instructions): Add new instructions.
1406         (is_mve_encoding_conflict): Handle new instructions.
1407         (is_mve_unpredictable): Likewise.
1408         (print_mve_size): Likewise.
1409         (print_insn_mve): Likewise.
1410
1411 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1412             Michael Collison <michael.collison@arm.com>
1413
1414         * arm-dis.c (enum mve_instructions): Add new instructions.
1415         (enum mve_undefined): Add new reasons.
1416         (is_mve_encoding_conflict): Handle new instructions.
1417         (is_mve_undefined): Likewise.
1418         (is_mve_unpredictable): Likewise.
1419         (print_mve_undefined): Likewise.
1420         (print_mve_size): Likewise.
1421         (print_insn_mve): Likewise.
1422
1423 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1424             Michael Collison <michael.collison@arm.com>
1425
1426         * arm-dis.c (enum mve_instructions): Add new instructions.
1427         (is_mve_encoding_conflict): Handle new instructions.
1428         (is_mve_undefined): Likewise.
1429         (is_mve_unpredictable): Likewise.
1430         (print_mve_size): Likewise.
1431         (print_insn_mve): Likewise.
1432
1433 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1434             Michael Collison <michael.collison@arm.com>
1435
1436         * arm-dis.c (enum mve_instructions): Add new instructions.
1437         (enum mve_unpredictable): Add new reasons.
1438         (enum mve_undefined): Likewise.
1439         (is_mve_okay_in_it): Handle new isntructions.
1440         (is_mve_encoding_conflict): Likewise.
1441         (is_mve_undefined): Likewise.
1442         (is_mve_unpredictable): Likewise.
1443         (print_mve_vmov_index): Likewise.
1444         (print_simd_imm8): Likewise.
1445         (print_mve_undefined): Likewise.
1446         (print_mve_unpredictable): Likewise.
1447         (print_mve_size): Likewise.
1448         (print_insn_mve): Likewise.
1449
1450 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1451             Michael Collison <michael.collison@arm.com>
1452
1453         * arm-dis.c (enum mve_instructions): Add new instructions.
1454         (enum mve_unpredictable): Add new reasons.
1455         (enum mve_undefined): Likewise.
1456         (is_mve_encoding_conflict): Handle new instructions.
1457         (is_mve_undefined): Likewise.
1458         (is_mve_unpredictable): Likewise.
1459         (print_mve_undefined): Likewise.
1460         (print_mve_unpredictable): Likewise.
1461         (print_mve_rounding_mode): Likewise.
1462         (print_mve_vcvt_size): Likewise.
1463         (print_mve_size): Likewise.
1464         (print_insn_mve): Likewise.
1465
1466 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1467             Michael Collison <michael.collison@arm.com>
1468
1469         * arm-dis.c (enum mve_instructions): Add new instructions.
1470         (enum mve_unpredictable): Add new reasons.
1471         (enum mve_undefined): Likewise.
1472         (is_mve_undefined): Handle new instructions.
1473         (is_mve_unpredictable): Likewise.
1474         (print_mve_undefined): Likewise.
1475         (print_mve_unpredictable): Likewise.
1476         (print_mve_size): Likewise.
1477         (print_insn_mve): Likewise.
1478
1479 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1480             Michael Collison <michael.collison@arm.com>
1481
1482         * arm-dis.c (enum mve_instructions): Add new instructions.
1483         (enum mve_undefined): Add new reasons.
1484         (insns): Add new instructions.
1485         (is_mve_encoding_conflict):
1486         (print_mve_vld_str_addr): New print function.
1487         (is_mve_undefined): Handle new instructions.
1488         (is_mve_unpredictable): Likewise.
1489         (print_mve_undefined): Likewise.
1490         (print_mve_size): Likewise.
1491         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1492         (print_insn_mve):  Handle new operands.
1493
1494 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1495             Michael Collison <michael.collison@arm.com>
1496
1497         * arm-dis.c (enum mve_instructions): Add new instructions.
1498         (enum mve_unpredictable): Add new reasons.
1499         (is_mve_encoding_conflict): Handle new instructions.
1500         (is_mve_unpredictable): Likewise.
1501         (mve_opcodes): Add new instructions.
1502         (print_mve_unpredictable): Handle new reasons.
1503         (print_mve_register_blocks): New print function.
1504         (print_mve_size): Handle new instructions.
1505         (print_insn_mve): Likewise.
1506
1507 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1508             Michael Collison <michael.collison@arm.com>
1509
1510         * arm-dis.c (enum mve_instructions): Add new instructions.
1511         (enum mve_unpredictable): Add new reasons.
1512         (enum mve_undefined): Likewise.
1513         (is_mve_encoding_conflict): Handle new instructions.
1514         (is_mve_undefined): Likewise.
1515         (is_mve_unpredictable): Likewise.
1516         (coprocessor_opcodes): Move NEON VDUP from here...
1517         (neon_opcodes): ... to here.
1518         (mve_opcodes): Add new instructions.
1519         (print_mve_undefined):  Handle new reasons.
1520         (print_mve_unpredictable): Likewise.
1521         (print_mve_size): Handle new instructions.
1522         (print_insn_neon): Handle vdup.
1523         (print_insn_mve): Handle new operands.
1524
1525 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1526             Michael Collison <michael.collison@arm.com>
1527
1528         * arm-dis.c (enum mve_instructions): Add new instructions.
1529         (enum mve_unpredictable): Add new values.
1530         (mve_opcodes): Add new instructions.
1531         (vec_condnames): New array with vector conditions.
1532         (mve_predicatenames): New array with predicate suffixes.
1533         (mve_vec_sizename): New array with vector sizes.
1534         (enum vpt_pred_state): New enum with vector predication states.
1535         (struct vpt_block): New struct type for vpt blocks.
1536         (vpt_block_state): Global struct to keep track of state.
1537         (mve_extract_pred_mask): New helper function.
1538         (num_instructions_vpt_block): Likewise.
1539         (mark_outside_vpt_block): Likewise.
1540         (mark_inside_vpt_block): Likewise.
1541         (invert_next_predicate_state): Likewise.
1542         (update_next_predicate_state): Likewise.
1543         (update_vpt_block_state): Likewise.
1544         (is_vpt_instruction): Likewise.
1545         (is_mve_encoding_conflict): Add entries for new instructions.
1546         (is_mve_unpredictable): Likewise.
1547         (print_mve_unpredictable): Handle new cases.
1548         (print_instruction_predicate): Likewise.
1549         (print_mve_size): New function.
1550         (print_vec_condition): New function.
1551         (print_insn_mve): Handle vpt blocks and new print operands.
1552
1553 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1554
1555         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1556         8, 14 and 15 for Armv8.1-M Mainline.
1557
1558 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1559             Michael Collison <michael.collison@arm.com>
1560
1561         * arm-dis.c (enum mve_instructions): New enum.
1562         (enum mve_unpredictable): Likewise.
1563         (enum mve_undefined): Likewise.
1564         (struct mopcode32): New struct.
1565         (is_mve_okay_in_it): New function.
1566         (is_mve_architecture): Likewise.
1567         (arm_decode_field): Likewise.
1568         (arm_decode_field_multiple): Likewise.
1569         (is_mve_encoding_conflict): Likewise.
1570         (is_mve_undefined): Likewise.
1571         (is_mve_unpredictable): Likewise.
1572         (print_mve_undefined): Likewise.
1573         (print_mve_unpredictable): Likewise.
1574         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1575         (print_insn_mve): New function.
1576         (print_insn_thumb32): Handle MVE architecture.
1577         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1578
1579 2019-05-10  Nick Clifton  <nickc@redhat.com>
1580
1581         PR 24538
1582         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1583         end of the table prematurely.
1584
1585 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1586
1587         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1588         macros for R6.
1589
1590 2019-05-11  Alan Modra  <amodra@gmail.com>
1591
1592         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1593         when -Mraw is in effect.
1594
1595 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1596
1597         * aarch64-dis-2.c: Regenerate.
1598         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1599         (OP_SVE_BBB): New variant set.
1600         (OP_SVE_DDDD): New variant set.
1601         (OP_SVE_HHH): New variant set.
1602         (OP_SVE_HHHU): New variant set.
1603         (OP_SVE_SSS): New variant set.
1604         (OP_SVE_SSSU): New variant set.
1605         (OP_SVE_SHH): New variant set.
1606         (OP_SVE_SBBU): New variant set.
1607         (OP_SVE_DSS): New variant set.
1608         (OP_SVE_DHHU): New variant set.
1609         (OP_SVE_VMV_HSD_BHS): New variant set.
1610         (OP_SVE_VVU_HSD_BHS): New variant set.
1611         (OP_SVE_VVVU_SD_BH): New variant set.
1612         (OP_SVE_VVVU_BHSD): New variant set.
1613         (OP_SVE_VVV_QHD_DBS): New variant set.
1614         (OP_SVE_VVV_HSD_BHS): New variant set.
1615         (OP_SVE_VVV_HSD_BHS2): New variant set.
1616         (OP_SVE_VVV_BHS_HSD): New variant set.
1617         (OP_SVE_VV_BHS_HSD): New variant set.
1618         (OP_SVE_VVV_SD): New variant set.
1619         (OP_SVE_VVU_BHS_HSD): New variant set.
1620         (OP_SVE_VZVV_SD): New variant set.
1621         (OP_SVE_VZVV_BH): New variant set.
1622         (OP_SVE_VZV_SD): New variant set.
1623         (aarch64_opcode_table): Add sve2 instructions.
1624
1625 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1626
1627         * aarch64-asm-2.c: Regenerated.
1628         * aarch64-dis-2.c: Regenerated.
1629         * aarch64-opc-2.c: Regenerated.
1630         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1631         for SVE_SHLIMM_UNPRED_22.
1632         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1633         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1634         operand.
1635
1636 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1637
1638         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1639         sve_size_tsz_bhs iclass encode.
1640         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1641         sve_size_tsz_bhs iclass decode.
1642
1643 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1644
1645         * aarch64-asm-2.c: Regenerated.
1646         * aarch64-dis-2.c: Regenerated.
1647         * aarch64-opc-2.c: Regenerated.
1648         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1649         for SVE_Zm4_11_INDEX.
1650         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1651         (fields): Handle SVE_i2h field.
1652         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1653         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1654
1655 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1656
1657         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1658         sve_shift_tsz_bhsd iclass encode.
1659         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1660         sve_shift_tsz_bhsd iclass decode.
1661
1662 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1663
1664         * aarch64-asm-2.c: Regenerated.
1665         * aarch64-dis-2.c: Regenerated.
1666         * aarch64-opc-2.c: Regenerated.
1667         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1668         (aarch64_encode_variant_using_iclass): Handle
1669         sve_shift_tsz_hsd iclass encode.
1670         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1671         sve_shift_tsz_hsd iclass decode.
1672         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1673         for SVE_SHRIMM_UNPRED_22.
1674         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1675         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1676         operand.
1677
1678 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1679
1680         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1681         sve_size_013 iclass encode.
1682         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1683         sve_size_013 iclass decode.
1684
1685 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1686
1687         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1688         sve_size_bh iclass encode.
1689         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1690         sve_size_bh iclass decode.
1691
1692 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1693
1694         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1695         sve_size_sd2 iclass encode.
1696         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1697         sve_size_sd2 iclass decode.
1698         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1699         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1700
1701 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1702
1703         * aarch64-asm-2.c: Regenerated.
1704         * aarch64-dis-2.c: Regenerated.
1705         * aarch64-opc-2.c: Regenerated.
1706         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1707         for SVE_ADDR_ZX.
1708         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1709         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1710
1711 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1712
1713         * aarch64-asm-2.c: Regenerated.
1714         * aarch64-dis-2.c: Regenerated.
1715         * aarch64-opc-2.c: Regenerated.
1716         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1717         for SVE_Zm3_11_INDEX.
1718         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1719         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1720         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1721         fields.
1722         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1723
1724 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1725
1726         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1727         sve_size_hsd2 iclass encode.
1728         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1729         sve_size_hsd2 iclass decode.
1730         * aarch64-opc.c (fields): Handle SVE_size field.
1731         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1732
1733 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1734
1735         * aarch64-asm-2.c: Regenerated.
1736         * aarch64-dis-2.c: Regenerated.
1737         * aarch64-opc-2.c: Regenerated.
1738         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1739         for SVE_IMM_ROT3.
1740         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1741         (fields): Handle SVE_rot3 field.
1742         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1743         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1744
1745 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1746
1747         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1748         instructions.
1749
1750 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1751
1752         * aarch64-tbl.h
1753         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1754         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1755         aarch64_feature_sve2bitperm): New feature sets.
1756         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1757         for feature set addresses.
1758         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1759         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1760
1761 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1762             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1763
1764         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1765         argument and set ASE_EVA_R6 appropriately.
1766         (set_default_mips_dis_options): Pass ISA to above.
1767         (parse_mips_dis_option): Likewise.
1768         * mips-opc.c (EVAR6): New macro.
1769         (mips_builtin_opcodes): Add llwpe, scwpe.
1770
1771 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1772
1773         * aarch64-asm-2.c: Regenerated.
1774         * aarch64-dis-2.c: Regenerated.
1775         * aarch64-opc-2.c: Regenerated.
1776         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1777         AARCH64_OPND_TME_UIMM16.
1778         (aarch64_print_operand): Likewise.
1779         * aarch64-tbl.h (QL_IMM_NIL): New.
1780         (TME): New.
1781         (_TME_INSN): New.
1782         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1783
1784 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1785
1786         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1787
1788 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1789             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1790
1791         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1792
1793 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1794
1795         * s12z-opc.h: Add extern "C" bracketing to help
1796         users who wish to use this interface in c++ code.
1797
1798 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1799
1800         * s12z-opc.c (bm_decode): Handle bit map operations with the
1801         "reserved0" mode.
1802
1803 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1804
1805         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1806         specifier.  Add entries for VLDR and VSTR of system registers.
1807         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1808         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1809         of %J and %K format specifier.
1810
1811 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1812
1813         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1814         Add new entries for VSCCLRM instruction.
1815         (print_insn_coprocessor): Handle new %C format control code.
1816
1817 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1818
1819         * arm-dis.c (enum isa): New enum.
1820         (struct sopcode32): New structure.
1821         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1822         set isa field of all current entries to ANY.
1823         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1824         Only match an entry if its isa field allows the current mode.
1825
1826 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1827
1828         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1829         CLRM.
1830         (print_insn_thumb32): Add logic to print %n CLRM register list.
1831
1832 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1833
1834         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1835         and %Q patterns.
1836
1837 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1838
1839         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1840         (print_insn_thumb32): Edit the switch case for %Z.
1841
1842 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1843
1844         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1845
1846 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1847
1848         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1849
1850 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1851
1852         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1853
1854 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1855
1856         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1857         Arm register with r13 and r15 unpredictable.
1858         (thumb32_opcodes): New instructions for bfx and bflx.
1859
1860 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1861
1862         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1863
1864 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1865
1866         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1867
1868 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1869
1870         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1871
1872 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1873
1874         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1875
1876 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1877
1878         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1879         "optr". ("operator" is a reserved word in c++).
1880
1881 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1882
1883         * aarch64-opc.c (aarch64_print_operand): Add case for
1884         AARCH64_OPND_Rt_SP.
1885         (verify_constraints): Likewise.
1886         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1887         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1888         to accept Rt|SP as first operand.
1889         (AARCH64_OPERANDS): Add new Rt_SP.
1890         * aarch64-asm-2.c: Regenerated.
1891         * aarch64-dis-2.c: Regenerated.
1892         * aarch64-opc-2.c: Regenerated.
1893
1894 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1895
1896         * aarch64-asm-2.c: Regenerated.
1897         * aarch64-dis-2.c: Likewise.
1898         * aarch64-opc-2.c: Likewise.
1899         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1900
1901 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1902
1903         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1904
1905 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1906
1907         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1908         * i386-init.h: Regenerated.
1909
1910 2019-04-07  Alan Modra  <amodra@gmail.com>
1911
1912         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1913         op_separator to control printing of spaces, comma and parens
1914         rather than need_comma, need_paren and spaces vars.
1915
1916 2019-04-07  Alan Modra  <amodra@gmail.com>
1917
1918         PR 24421
1919         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1920         (print_insn_neon, print_insn_arm): Likewise.
1921
1922 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1923
1924         * i386-dis-evex.h (evex_table): Updated to support BF16
1925         instructions.
1926         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1927         and EVEX_W_0F3872_P_3.
1928         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1929         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1930         * i386-opc.h (enum): Add CpuAVX512_BF16.
1931         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1932         * i386-opc.tbl: Add AVX512 BF16 instructions.
1933         * i386-init.h: Regenerated.
1934         * i386-tbl.h: Likewise.
1935
1936 2019-04-05  Alan Modra  <amodra@gmail.com>
1937
1938         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1939         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1940         to favour printing of "-" branch hint when using the "y" bit.
1941         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1942
1943 2019-04-05  Alan Modra  <amodra@gmail.com>
1944
1945         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1946         opcode until first operand is output.
1947
1948 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1949
1950         PR gas/24349
1951         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1952         (valid_bo_post_v2): Add support for 'at' branch hints.
1953         (insert_bo): Only error on branch on ctr.
1954         (get_bo_hint_mask): New function.
1955         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1956         for inserting 'at' branch hints.
1957         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1958         for extracting 'at' branch hints.
1959         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1960         (BOE): Delete operand.
1961         (BOM, BOP): New operands.
1962         (RM): Update value.
1963         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1964         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1965         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1966         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1967         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1968         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1969         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1970         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1971         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1972         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1973         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1974         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1975         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1976         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1977         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1978         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1979         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1980         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1981         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1982         bttarl+>: New extended mnemonics.
1983
1984 2019-03-28  Alan Modra  <amodra@gmail.com>
1985
1986         PR 24390
1987         * ppc-opc.c (BTF): Define.
1988         (powerpc_opcodes): Use for mtfsb*.
1989         * ppc-dis.c (print_insn_powerpc): Print fields with both
1990         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1991
1992 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1993
1994         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1995         (mapping_symbol_for_insn): Implement new algorithm.
1996         (print_insn): Remove duplicate code.
1997
1998 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1999
2000         * aarch64-dis.c (print_insn_aarch64):
2001         Implement override.
2002
2003 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2004
2005         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2006         order.
2007
2008 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2009
2010         * aarch64-dis.c (last_stop_offset): New.
2011         (print_insn_aarch64): Use stop_offset.
2012
2013 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
2014
2015         PR gas/24359
2016         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2017         CPU_ANY_AVX2_FLAGS.
2018         * i386-init.h: Regenerated.
2019
2020 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
2021
2022         PR gas/24348
2023         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2024         vmovdqu16, vmovdqu32 and vmovdqu64.
2025         * i386-tbl.h: Regenerated.
2026
2027 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2028
2029         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
2030         from vstrszb, vstrszh, and vstrszf.
2031
2032 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2033
2034         * s390-opc.txt: Add instruction descriptions.
2035
2036 2019-02-08  Jim Wilson  <jimw@sifive.com>
2037
2038         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2039         <bne>: Likewise.
2040
2041 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2042
2043         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2044
2045 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2046
2047         PR binutils/23212
2048         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2049         * aarch64-opc.c (verify_elem_sd): New.
2050         (fields): Add FLD_sz entr.
2051         * aarch64-tbl.h (_SIMD_INSN): New.
2052         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2053         fmulx scalar and vector by element isns.
2054
2055 2019-02-07  Nick Clifton  <nickc@redhat.com>
2056
2057         * po/sv.po: Updated Swedish translation.
2058
2059 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
2060
2061         * s390-mkopc.c (main): Accept arch13 as cpu string.
2062         * s390-opc.c: Add new instruction formats and instruction opcode
2063         masks.
2064         * s390-opc.txt: Add new arch13 instructions.
2065
2066 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2067
2068         * aarch64-tbl.h (QL_LDST_AT): Update macro.
2069         (aarch64_opcode): Change encoding for stg, stzg
2070         st2g and st2zg.
2071         * aarch64-asm-2.c: Regenerated.
2072         * aarch64-dis-2.c: Regenerated.
2073         * aarch64-opc-2.c: Regenerated.
2074
2075 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2076
2077         * aarch64-asm-2.c: Regenerated.
2078         * aarch64-dis-2.c: Likewise.
2079         * aarch64-opc-2.c: Likewise.
2080         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2081
2082 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2083             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
2084
2085         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2086         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2087         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2088         * aarch64-dis.h (ext_addr_simple_2): Likewise.
2089         * aarch64-opc.c (operand_general_constraint_met_p): Remove
2090         case for ldstgv_indexed.
2091         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2092         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2093         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2094         * aarch64-asm-2.c: Regenerated.
2095         * aarch64-dis-2.c: Regenerated.
2096         * aarch64-opc-2.c: Regenerated.
2097
2098 2019-01-23  Nick Clifton  <nickc@redhat.com>
2099
2100         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2101
2102 2019-01-21  Nick Clifton  <nickc@redhat.com>
2103
2104         * po/de.po: Updated German translation.
2105         * po/uk.po: Updated Ukranian translation.
2106
2107 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
2108         * mips-dis.c (mips_arch_choices): Fix typo in
2109         gs464, gs464e and gs264e descriptors.
2110
2111 2019-01-19  Nick Clifton  <nickc@redhat.com>
2112
2113         * configure: Regenerate.
2114         * po/opcodes.pot: Regenerate.
2115
2116 2018-06-24  Nick Clifton  <nickc@redhat.com>
2117
2118         2.32 branch created.
2119
2120 2019-01-09  John Darrington <john@darrington.wattle.id.au>
2121
2122         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
2123         if it is null.
2124         -dis.c (opr_emit_disassembly): Do not omit an index if it is
2125         zero.
2126
2127 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
2128
2129         * configure: Regenerate.
2130
2131 2019-01-07  Alan Modra  <amodra@gmail.com>
2132
2133         * configure: Regenerate.
2134         * po/POTFILES.in: Regenerate.
2135
2136 2019-01-03  John Darrington <john@darrington.wattle.id.au>
2137
2138         * s12z-opc.c: New file.
2139         * s12z-opc.h: New file.
2140         * s12z-dis.c: Removed all code not directly related to display
2141         of instructions.  Used the interface provided by the new files
2142         instead.
2143         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
2144         * Makefile.in: Regenerate.
2145         * configure.ac (bfd_s12z_arch): Correct the dependencies.
2146         * configure: Regenerate.
2147
2148 2019-01-01  Alan Modra  <amodra@gmail.com>
2149
2150         Update year range in copyright notice of all files.
2151
2152 For older changes see ChangeLog-2018
2153 \f
2154 Copyright (C) 2019 Free Software Foundation, Inc.
2155
2156 Copying and distribution of this file, with or without modification,
2157 are permitted in any medium without royalty provided the copyright
2158 notice and this notice are preserved.
2159
2160 Local Variables:
2161 mode: change-log
2162 left-margin: 8
2163 fill-column: 74
2164 version-control: never
2165 End: