opcodes/ChangeLog

   1 2015-12-14  Matthew Wahab  <matthew.wahab@arm.coM>
   2
   3         * aarch64-dis.c (get_vreg_qualifier_from_value): Update comment
   4         and adjust calculation to ignore qualifier for type 2H.
   5         * aarch64-opc.c (aarch64_opnd_qualifier): Add "2H".
   6
   7 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
   8
   9         * aarch64-asm-2.c: Regenerate.
  10         * aarch64-dis-2.c: Regenerate.
  11         * aarch64-opc-2.c: Regenerate.
  12         * aarch64-tbl.h (QL_SIMD_IMM_H): New.
  13         (aarch64_opcode_table): Add fp16 version of fmov to the Adv.SIMD
  14         modified immediate group.
  15
  16 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  17
  18         * aarch64-asm-2.c: Regenerate.
  19         * aarch64-dis-2.c: Regenerate.
  20         * aarch64-opc-2.c: Regenerate.
  21         * aarch64-tbl.h (QL_XLANES_FP_H): New.
  22         (aarch64_opcode_table): Add fp16 versions of fmaxnmv, fmaxv,
  23         fminnmv, fminv to the Adv.SIMD across lanes group.
  24
  25 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  26
  27         * aarch64-asm-2.c: Regenerate.
  28         * aarch64-dis-2.c: Regenerate.
  29         * aarch64-opc-2.c: Regenerate.
  30         * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of fmla,
  31         fmls, fmul and fmulx to the scalar indexed element group.
  32
  33 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  34
  35         * aarch64-asm-2.c: Regenerate.
  36         * aarch64-dis-2.c: Regenerate.
  37         * aarch64-opc-2.c: Regenerate.
  38         * aarch64-tbl.h (QL_ELEMENT_FP_H): New.
  39         (aarch64_opcode_table): Add fp16 versions of fmla, fmls, fmul and
  40         fmulx to the vector indexed element group.
  41
  42 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  43
  44         * aarch64-asm-2.c: Regenerate.
  45         * aarch64-dis-2.c: Regenerate.
  46         * aarch64-opc-2.c: Regenerate.
  47         * aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
  48         (QL_S_2SAMEH): New.
  49         (aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
  50         fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
  51         frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
  52         fcvtzu and frsqrte to the scalar two register misc. group.
  53
  54 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  55
  56         * aarch64-asm-2.c: Regenerate.
  57         * aarch64-dis-2.c: Regenerate.
  58         * aarch64-opc-2.c: Regenerate.
  59         * aarch64-tbl.h (QL_V2SAMEH): New.
  60         (aarch64_opcode_table): Add fp16 versions of frintn, frintm,
  61         fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
  62         frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
  63         fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
  64         and fsqrt to the vector register misc. group.
  65
  66 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  67
  68         * aarch64-asm-2.c: Regenerate.
  69         * aarch64-dis-2.c: Regenerate.
  70         * aarch64-opc-2.c: Regenerate.
  71         * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of
  72         fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and facgt
  73         to the scalar three same group.
  74
  75 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  76
  77         * aarch64-asm-2.c: Regenerate.
  78         * aarch64-dis-2.c: Regenerate.
  79         * aarch64-opc-2.c: Regenerate.
  80         * aarch64-tbl.h (QL_V3SAMEH): New.
  81         (aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
  82         fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
  83         fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
  84         fcmgt, facgt and fminp to the vector three same group.
  85
  86 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  87
  88         * aarch64-tbl.h (aarch64_feature_simd_f16): New.
  89         (SIMD_F16): New.
  90
  91 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
  92
  93         * aarch64-opc.c (aarch64_sys_reg_supported_p): Add mistakenly
  94         removed statement.
  95         (aarch64_pstatefield_supported_p): Move feature checks for AT
  96         registers ..
  97         (aarch64_sys_ins_reg_supported_p): .. to here.
  98
  99 2015-12-12  Alan Modra  <amodra@gmail.com>
 100
 101         PR 19359
 102         * ppc-opc.c (insert_fxm): Remove "ignored" from error message.
 103         (powerpc_opcodes): Remove single-operand mfcr.
 104
 105 2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
 106
 107         * aarch64-asm.c (aarch64_ins_hint): New.
 108         * aarch64-asm.h (aarch64_ins_hint): Declare.
 109         * aarch64-dis.c (aarch64_ext_hint): New.
 110         * aarch64-dis.h (aarch64_ext_hint): Declare.
 111         * aarch64-opc-2.c: Regenerate.
 112         * aarch64-opc.c (aarch64_hint_options): New.
 113         * aarch64-tbl.h (AARCH64_OPERANDS): Fix typos.
 114
 115 2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
 116
 117         * aarch64-gen.c (find_alias_opcode): Set max_num_aliases to 16.
 118
 119 2015-12-11  Matthew Wahab  <matthew.wahab@arm.com>
 120
 121         * aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1,
 122         pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1,
 123         pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and
 124         pmscr_el2.
 125         (aarch64_sys_reg_supported_p): Add architecture feature tests for
 126         the new registers.
 127
 128 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
 129
 130         * aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".
 131         (aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register
 132         feature test for "s1e1rp" and "s1e1wp".
 133
 134 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
 135
 136         * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
 137         (aarch64_sys_ins_reg_supported_p): New.
 138
 139 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
 140
 141         * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
 142         with aarch64_sys_ins_reg_has_xt.
 143         (aarch64_ext_sysins_op): Likewise.
 144         * aarch64-opc.c (operand_general_constraint_met_p): Likewise.
 145         (F_HASXT): New.
 146         (aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
 147         (aarch64_sys_regs_dc): Likewise.
 148         (aarch64_sys_regs_at): Likewise.
 149         (aarch64_sys_regs_tlbi): Likewise.
 150         (aarch64_sys_ins_reg_has_xt): New.
 151
 152 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
 153
 154         * aarch64-opc.c (aarch64_sys_regs): Add "uao".
 155         (aarch64_sys_reg_supported_p): Add comment.  Add checks for "uao".
 156         (aarch64_pstatefields): Add "uao".
 157         (aarch64_pstatefield_supported_p): Add checks for "uao".
 158
 159 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
 160
 161         * aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
 162         "errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
 163         "erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
 164         (aarch64_sys_reg_supported_p): Add architecture feature tests for
 165         new registers.
 166
 167 2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>
 168
 169         * aarch64-asm-2.c: Regenerate.
 170         * aarch64-dis-2.c: Regenerate.
 171         * aarch64-tbl.h (aarch64_feature_ras): New.
 172         (RAS): New.
 173         (aarch64_opcode_table): Add "esb".
 174
 175 2015-12-09  H.J. Lu  <hongjiu.lu@intel.com>
 176
 177         * i386-dis.c (MOD_0F01_REG_5): New.
 178         (RM_0F01_REG_5): Likewise.
 179         (reg_table): Use MOD_0F01_REG_5.
 180         (mod_table): Add MOD_0F01_REG_5.
 181         (rm_table): Add RM_0F01_REG_5.
 182         * i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
 183         (cpu_flags): Add CpuOSPKE.
 184         * i386-opc.h (CpuOSPKE): New.
 185         (i386_cpu_flags): Add cpuospke.
 186         * i386-opc.tbl: Add rdpkru and wrpkru instructions.
 187         * i386-init.h: Regenerated.
 188         * i386-tbl.h: Likewise.
 189
 190 2015-12-07  DJ Delorie  <dj@redhat.com>
 191
 192         * rl78-decode.opc: Enable MULU for all ISAs.
 193         * rl78-decode.c: Regenerate.
 194
 195 2015-12-07  Alan Modra  <amodra@gmail.com>
 196
 197         * opcodes/ppc-opc.c (powerpc_opcodes): Sort power9 insns by
 198         major opcode/xop.
 199
 200 2015-12-04  Claudiu Zissulescu  <claziss@synopsys.com>
 201
 202         * arc-dis.c (special_flag_p): Match full mnemonic.
 203         * arc-opc.c (print_insn_arc): Check section size to read
 204         appropriate number of bytes. Fix printing.
 205         * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
 206         arguments.
 207
 208 2015-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 209
 210         * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
 211         <ldah>: ... to this.
 212
 213 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 214
 215         * aarch64-asm-2.c: Regenerate.
 216         * aarch64-dis-2.c: Regenerate.
 217         * aarch64-opc-2.c: Regenerate.
 218         * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New.
 219         (QL_INT2FP_H, QL_FP2INT_H): New.
 220         (QL_FP2_H, QL_FP3_H, QL_FP4_H): New
 221         (QL_DST_H): New.
 222         (QL_FCCMP_H): New.
 223         (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf,
 224         fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau,
 225         fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp,
 226         fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm,
 227         frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax,
 228         fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and
 229         fcsel.
 230
 231 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 232
 233         * aarch64-opc.c (half_conv_t): New.
 234         (expand_fp_imm): Replace is_dp flag with the parameter size to
 235         specify the number of bytes for the required expansion.  Treat
 236         a 16-bit expansion like a 32-bit expansion.  Add check for an
 237         unsupported size request.  Update comment.
 238         (aarch64_print_operand): Update to support 16-bit floating point
 239         values.  Update for changes to expand_fp_imm.
 240
 241 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 242
 243         * aarch64-tbl.h (aarch64_feature_fp_f16): New.
 244         (FP_F16): New.
 245
 246 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 247
 248         * aarch64-asm-2.c: Regenerate.
 249         * aarch64-dis-2.c: Regenerate.
 250         * aarch64-opc-2.c: Regenerate.
 251         * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
 252         "rev64".
 253
 254 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 255
 256         * aarch64-asm-2.c: Regenerate.
 257         * aarch64-asm.c (convert_bfc_to_bfm): New.
 258         (convert_to_real): Add case for OP_BFC.
 259         * aarch64-dis-2.c: Regenerate.
 260         * aarch64-dis.c: (convert_bfm_to_bfc): New.
 261         (convert_to_alias): Add case for OP_BFC.
 262         * aarch64-opc-2.c: Regenerate.
 263         * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
 264         to allow width operand in three-operand instructions.
 265         * aarch64-tbl.h (QL_BF1): New.
 266         (aarch64_feature_v8_2): New.
 267         (ARMV8_2): New.
 268         (aarch64_opcode_table): Add "bfc".
 269
 270 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 271
 272         * aarch64-asm-2.c: Regenerate.
 273         * aarch64-dis-2.c: Regenerate.
 274         * aarch64-dis.c: Weaken assert.
 275         * aarch64-gen.c: Include the instruction in the list of its
 276         possible aliases.
 277
 278 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 279
 280         * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
 281         (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
 282         feature test.
 283
 284 2015-11-23  Tristan Gingold  <gingold@adacore.com>
 285
 286         * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
 287
 288 2015-11-20  Matthew Wahab  <matthew.wahab@arm.com>
 289
 290         * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
 291         sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
 292         tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
 293         amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
 294         cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
 295         cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
 296         cnthv_ctl_el2, cnthv_cval_el2.
 297         (aarch64_sys_reg_supported_p): Update for the new system
 298         registers.
 299
 300 2015-11-20  Nick Clifton  <nickc@redhat.com>
 301
 302         PR binutils/19224
 303         * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
 304
 305 2015-11-20  Nick Clifton  <nickc@redhat.com>
 306
 307         * po/zh_CN.po: Updated simplified Chinese translation.
 308
 309 2015-11-19  Matthew Wahab  <matthew.wahab@arm.com>
 310
 311         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
 312         of MSR PAN immediate operand.
 313
 314 2015-11-16  Nick Clifton  <nickc@redhat.com>
 315
 316         * rx-dis.c (condition_names): Replace always and never with
 317         invalid, since the always/never conditions can never be legal.
 318
 319 2015-11-13  Tristan Gingold  <gingold@adacore.com>
 320
 321         * configure: Regenerate.
 322
 323 2015-11-11  Alan Modra  <amodra@gmail.com>
 324             Peter Bergner <bergner@vnet.ibm.com>
 325
 326         * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
 327         Add PPC_OPCODE_VSX3 to the vsx entry.
 328         (powerpc_init_dialect): Set default dialect to power9.
 329         * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
 330         insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
 331         extract_l1 insert_xtq6, extract_xtq6): New static functions.
 332         (insert_esync): Test for illegal L operand value.
 333         (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
 334         XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
 335         XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
 336         XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
 337         PPCVSX3): New defines.
 338         (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
 339         fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
 340         <mcrxr>: Use XBFRARB_MASK.
 341         <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
 342         bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
 343         cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
 344         cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
 345         lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
 346         lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
 347         modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
 348         rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
 349         stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
 350         subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
 351         vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
 352         vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
 353         vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
 354         vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
 355         vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
 356         vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
 357         vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
 358         xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
 359         xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
 360         xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
 361         xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
 362         xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
 363         xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
 364         xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
 365         xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
 366         xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
 367         xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
 368         xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
 369         xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
 370         xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
 371         <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
 372         <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
 373
 374 2015-11-02  Nick Clifton  <nickc@redhat.com>
 375
 376         * rx-decode.opc (rx_decode_opcode): Decode extra NOP
 377         instructions.
 378         * rx-decode.c: Regenerate.
 379
 380 2015-11-02  Nick Clifton  <nickc@redhat.com>
 381
 382         * rx-decode.opc (rx_disp): If the displacement is zero, set the
 383         type to RX_Operand_Zero_Indirect.
 384         * rx-decode.c: Regenerate.
 385         * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
 386
 387 2015-10-28  Yao Qi  <yao.qi@linaro.org>
 388
 389         * aarch64-dis.c (aarch64_decode_insn): Add one argument
 390         noaliases_p.  Update comments.  Pass noaliases_p rather than
 391         no_aliases to aarch64_opcode_decode.
 392         (print_insn_aarch64_word): Pass no_aliases to
 393         aarch64_decode_insn.
 394
 395 2015-10-27  Vinay  <Vinay.G@kpit.com>
 396
 397         PR binutils/19159
 398         * rl78-decode.opc (MOV): Added offset to DE register in index
 399         addressing mode.
 400         * rl78-decode.c: Regenerate.
 401
 402 2015-10-27  Vinay Kumar  <vinay.g@kpit.com>
 403
 404         PR binutils/19158
 405         * rl78-decode.opc: Add 's' print operator to instructions that
 406         access system registers.
 407         * rl78-decode.c: Regenerate.
 408         * rl78-dis.c (print_insn_rl78_common): Decode all system
 409         registers.
 410
 411 2015-10-27  Vinay Kumar  <vinay.g@kpit.com>
 412
 413         PR binutils/19157
 414         * rl78-decode.opc: Add 'a' print operator to mov instructions
 415         using stack pointer plus index addressing.
 416         * rl78-decode.c: Regenerate.
 417
 418 2015-10-14  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 419
 420         * s390-opc.c: Fix comment.
 421         * s390-opc.txt: Change instruction type for troo, trot, trto, and
 422         trtt to RRF_U0RER since the second parameter does not need to be a
 423         register pair.
 424
 425 2015-10-08  Nick Clifton  <nickc@redhat.com>
 426
 427         * arc-dis.c (print_insn_arc): Initiallise insn array.
 428
 429 2015-10-07  Yao Qi  <yao.qi@linaro.org>
 430
 431         * aarch64-dis.c (aarch64_ext_sysins_op): Access field
 432         'name' rather than 'template'.
 433         * aarch64-opc.c (aarch64_print_operand): Likewise.
 434
 435 2015-10-07  Claudiu Zissulescu <claziss@synopsys.com>
 436
 437         * arc-dis.c: Revamped file for ARC support
 438         * arc-dis.h: Likewise.
 439         * arc-ext.c: Likewise.
 440         * arc-ext.h: Likewise.
 441         * arc-opc.c: Likewise.
 442         * arc-fxi.h: New file.
 443         * arc-regs.h: Likewise.
 444         * arc-tbl.h: Likewise.
 445
 446 2015-10-02  Yao Qi  <yao.qi@linaro.org>
 447
 448         * aarch64-dis.c (disas_aarch64_insn): Remove static.  Change
 449         argument insn type to aarch64_insn.  Rename to ...
 450         (aarch64_decode_insn): ... it.
 451         (print_insn_aarch64_word): Caller updated.
 452
 453 2015-10-02  Yao Qi  <yao.qi@linaro.org>
 454
 455         * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
 456         (print_insn_aarch64_word): Caller updated.
 457
 458 2015-09-29  Dominik Vogt  <vogt@linux.vnet.ibm.com>
 459
 460         * s390-mkopc.c (main): Parse htm and vx flag.
 461         * s390-opc.txt: Mark instructions from the hardware transactional
 462         memory and vector facilities with the "htm"/"vx" flag.
 463
 464 2015-09-28  Nick Clifton  <nickc@redhat.com>
 465
 466         * po/de.po: Updated German translation.
 467
 468 2015-09-28  Tom Rix  <tom@bumblecow.com>
 469
 470         * ppc-opc.c (PPC500): Mark some opcodes as invalid
 471
 472 2015-09-23  Nick Clifton  <nickc@redhat.com>
 473
 474         * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
 475         function.
 476         * tic30-dis.c (print_branch): Likewise.
 477         * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
 478         value before left shifting.
 479         * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
 480         * hppa-dis.c (print_insn_hppa): Likewise.
 481         * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
 482         array.
 483         * msp430-dis.c (msp430_singleoperand): Likewise.
 484         (msp430_doubleoperand): Likewise.
 485         (print_insn_msp430): Likewise.
 486         * nds32-asm.c (parse_operand): Likewise.
 487         * sh-opc.h (MASK): Likewise.
 488         * v850-dis.c (get_operand_value): Likewise.
 489
 490 2015-09-22  Nick Clifton  <nickc@redhat.com>
 491
 492         * rx-decode.opc (bwl): Use RX_Bad_Size.
 493         (sbwl): Likewise.
 494         (ubwl): Likewise.  Rename to ubw.
 495         (uBWL): Rename to uBW.
 496         Replace all references to uBWL with uBW.
 497         * rx-decode.c: Regenerate.
 498         * rx-dis.c (size_names): Add entry for RX_Bad_Size.
 499         (opsize_names): Likewise.
 500         (print_insn_rx): Detect and report RX_Bad_Size.
 501
 502 2015-09-22  Anton Blanchard  <anton@samba.org>
 503
 504         * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
 505
 506 2015-08-25  Jose E. Marchesi  <jose.marchesi@oracle.com>
 507
 508         * sparc-dis.c (print_insn_sparc): Handle the privileged register
 509         %pmcdper.
 510
 511 2015-08-24  Jan Stancek  <jstancek@redhat.com>
 512
 513         * i386-dis.c (print_insn): Fix decoding of three byte operands.
 514
 515 2015-08-21  Alexander Fomin  <alexander.fomin@intel.com>
 516
 517         PR binutils/18257
 518         * i386-dis.c: Use MOD_TABLE for most of mask instructions.
 519         (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
 520         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 521         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 522         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 523         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 524         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 525         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 526         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 527         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 528         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 529         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 530         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 531         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 532         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 533         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 534         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 535         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 536         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 537         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 538         MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
 539         MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
 540         MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
 541         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 542         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 543         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 544         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 545         MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 546         MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 547         MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 548         MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
 549         (vex_w_table): Replace terminals with MOD_TABLE entries for
 550         most of mask instructions.
 551
 552 2015-08-17  Alan Modra  <amodra@gmail.com>
 553
 554         * cgen.sh: Trim trailing space from cgen output.
 555         * ia64-gen.c (print_dependency_table): Don't generate trailing space.
 556         (print_dis_table): Likewise.
 557         * opc2c.c (dump_lines): Likewise.
 558         (orig_filename): Warning fix.
 559         * ia64-asmtab.c: Regenerate.
 560
 561 2015-08-13  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 562
 563         * arm-dis.c (print_insn_arm): Disassembling for all targets V6
 564         and higher with ARM instruction set will now mark the 26-bit
 565         versions of teq,tst,cmn and cmp as UNPREDICTABLE.
 566         (arm_opcodes): Fix for unpredictable nop being recognized as a
 567         teq.
 568
 569 2015-08-12  Simon Dardis  <simon.dardis@imgtec.com>
 570
 571         * micromips-opc.c (micromips_opcodes): Re-order table so that move
 572         based on 'or' is first.
 573         * mips-opc.c (mips_builtin_opcodes): Ditto.
 574
 575 2015-08-11  Nick Clifton  <nickc@redhat.com>
 576
 577         PR 18800
 578         * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
 579         instruction.
 580
 581 2015-08-10  Robert Suchanek  <robert.suchanek@imgtec.com>
 582
 583         * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
 584
 585 2015-08-07  Amit Pawar <Amit.Pawar@amd.com>
 586
 587         * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
 588         * i386-init.h: Regenerated.
 589
 590 2015-07-30  H.J. Lu  <hongjiu.lu@intel.com>
 591
 592         PR binutils/13571
 593         * i386-dis.c (MOD_0FC3): New.
 594         (PREFIX_0FC3): Renamed to ...
 595         (PREFIX_MOD_0_0FC3): This.
 596         (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
 597         (prefix_table): Replace Ma with Ev on movntiS.
 598         (mod_table): Add MOD_0FC3.
 599
 600 2015-07-27  H.J. Lu  <hongjiu.lu@intel.com>
 601
 602         * configure: Regenerated.
 603
 604 2015-07-23  Alan Modra  <amodra@gmail.com>
 605
 606         PR 18708
 607         * i386-dis.c (get64): Avoid signed integer overflow.
 608
 609 2015-07-22  Alexander Fomin  <alexander.fomin@intel.com>
 610
 611         PR binutils/18631
 612         * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
 613         "EXEvexHalfBcstXmmq" for the second operand.
 614         (EVEX_W_0F79_P_2): Likewise.
 615         (EVEX_W_0F7A_P_2): Likewise.
 616         (EVEX_W_0F7B_P_2): Likewise.
 617
 618 2015-07-16  Alessandro Marzocchi  <alessandro.marzocchi@gmail.com>
 619
 620         * arm-dis.c (print_insn_coprocessor): Added support for quarter
 621         float bitfield format.
 622         (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
 623         quarter float bitfield format.
 624
 625 2015-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 626
 627         * configure: Regenerated.
 628
 629 2015-07-03  Alan Modra  <amodra@gmail.com>
 630
 631         * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
 632         * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries.  Add
 633         PPC_OPCODE_7450 to 7450 entry.  Add PPC_OPCODE_750 to 750cl entry.
 634
 635 2015-07-01  Sandra Loosemore  <sandra@codesourcery.com>
 636             Cesar Philippidis  <cesar@codesourcery.com>
 637
 638         * nios2-dis.c (nios2_extract_opcode): New.
 639         (nios2_disassembler_state): New.
 640         (nios2_find_opcode_hash): Use mach parameter to select correct
 641         disassembler state.
 642         (nios2_print_insn_arg): Extend to support new R2 argument letters
 643         and formats.
 644         (print_insn_nios2): Check for 16-bit instruction at end of memory.
 645         * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
 646         (NIOS2_NUM_OPCODES): Rename to...
 647         (NIOS2_NUM_R1_OPCODES): This.
 648         (nios2_r2_opcodes): New.
 649         (NIOS2_NUM_R2_OPCODES): New.
 650         (nios2_num_r2_opcodes): New.
 651         (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
 652         (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
 653         (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
 654         (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
 655         (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
 656
 657 2015-06-30  Amit Pawar  <Amit.Pawar@amd.com>
 658
 659         * i386-dis.c (OP_Mwaitx): New.
 660         (rm_table): Add monitorx/mwaitx.
 661         * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
 662         and CPU_ZNVER1_FLAGS.  Add CPU_MWAITX_FLAGS.
 663         (operand_type_init): Add CpuMWAITX.
 664         * i386-opc.h (CpuMWAITX): New.
 665         (i386_cpu_flags): Add cpumwaitx.
 666         * i386-opc.tbl: Add monitorx and mwaitx.
 667         * i386-init.h: Regenerated.
 668         * i386-tbl.h: Likewise.
 669
 670 2015-06-22  Peter Bergner  <bergner@vnet.ibm.com>
 671
 672         * ppc-opc.c (insert_ls): Test for invalid LS operands.
 673         (insert_esync): New function.
 674         (LS, WC): Use insert_ls.
 675         (ESYNC): Use insert_esync.
 676
 677 2015-06-22  Nick Clifton  <nickc@redhat.com>
 678
 679         * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
 680         requested region lies beyond it.
 681         * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
 682         looking for 32-bit insns.
 683         * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
 684         data.
 685         * sh-dis.c (print_insn_sh): Likewise.
 686         * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
 687         blocks of instructions.
 688         * vax-dis.c (print_insn_vax): Check that the requested address
 689         does not clash with the stop_vma.
 690
 691 2015-06-19  Peter Bergner  <bergner@vnet.ibm.com>
 692
 693         * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
 694         * ppc-opc.c (FXM4): Add non-zero optional value.
 695         (TBR): Likewise.
 696         (SXL): Likewise.
 697         (insert_fxm): Handle new default operand value.
 698         (extract_fxm): Likewise.
 699         (insert_tbr): Likewise.
 700         (extract_tbr): Likewise.
 701
 702 2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
 703
 704         * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
 705
 706 2015-06-16  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 707
 708         * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
 709
 710 2015-06-12  Peter Bergner  <bergner@vnet.ibm.com>
 711
 712         * ppc-opc.c: Add comment accidentally removed by old commit.
 713         (MTMSRD_L): Delete.
 714
 715 2015-06-04  Peter Bergner  <bergner@vnet.ibm.com>
 716
 717         * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
 718
 719 2015-06-04  Nick Clifton  <nickc@redhat.com>
 720
 721         PR 18474
 722         * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
 723
 724 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 725
 726         * arm-dis.c (arm_opcodes): Add "setpan".
 727         (thumb_opcodes): Add "setpan".
 728
 729 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 730
 731         * arm-dis.c (select_arm_features): Rework to avoid used of redefined
 732         macros.
 733
 734 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 735
 736         * aarch64-tbl.h (aarch64_feature_rdma): New.
 737         (RDMA): New.
 738         (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
 739         * aarch64-asm-2.c: Regenerate.
 740         * aarch64-dis-2.c: Regenerate.
 741         * aarch64-opc-2.c: Regenerate.
 742
 743 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 744
 745         * aarch64-tbl.h (aarch64_feature_lor): New.
 746         (LOR): New.
 747         (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
 748         "stllrb", "stllrh".
 749         * aarch64-asm-2.c: Regenerate.
 750         * aarch64-dis-2.c: Regenerate.
 751         * aarch64-opc-2.c: Regenerate.
 752
 753 2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
 754
 755         * aarch64-opc.c (F_ARCHEXT): New.
 756         (aarch64_sys_regs): Add "pan".
 757         (aarch64_sys_reg_supported_p): New.
 758         (aarch64_pstatefields): Add "pan".
 759         (aarch64_pstatefield_supported_p): New.
 760
 761 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 762
 763         * i386-tbl.h: Regenerate.
 764
 765 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 766
 767         * i386-dis.c (print_insn): Swap rounding mode specifier and
 768         general purpose register in Intel mode.
 769
 770 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 771
 772         * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
 773         * i386-tbl.h: Regenerate.
 774
 775 2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>
 776
 777         * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
 778         * i386-init.h: Regenerated.
 779
 780 2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>
 781
 782         PR binutis/18386
 783         * i386-dis.c: Add comments for '@'.
 784         (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
 785         (enum x86_64_isa): New.
 786         (isa64): Likewise.
 787         (print_i386_disassembler_options): Add amd64 and intel64.
 788         (print_insn): Handle amd64 and intel64.
 789         (putop): Handle '@'.
 790         (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
 791         * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
 792         * i386-opc.h (AMD64): New.
 793         (CpuIntel64): Likewise.
 794         (i386_cpu_flags): Add cpuamd64 and cpuintel64.
 795         * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
 796         Mark direct call/jmp without Disp16|Disp32 as Intel64.
 797         * i386-init.h: Regenerated.
 798         * i386-tbl.h: Likewise.
 799
 800 2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>
 801
 802         * ppc-opc.c (IH) New define.
 803         (powerpc_opcodes) <wait>: Do not enable for POWER7.
 804         <tlbie>: Add RS operand for POWER7.
 805         <slbia>: Add IH operand for POWER6.
 806
 807 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 808
 809         * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
 810         direct branch.
 811         (jmp): Likewise.
 812         * i386-tbl.h: Regenerated.
 813
 814 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 815
 816         * configure.ac: Support bfd_iamcu_arch.
 817         * disassemble.c (disassembler): Support bfd_iamcu_arch.
 818         * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
 819         CPU_IAMCU_COMPAT_FLAGS.
 820         (cpu_flags): Add CpuIAMCU.
 821         * i386-opc.h (CpuIAMCU): New.
 822         (i386_cpu_flags): Add cpuiamcu.
 823         * configure: Regenerated.
 824         * i386-init.h: Likewise.
 825         * i386-tbl.h: Likewise.
 826
 827 2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>
 828
 829         PR binutis/18386
 830         * i386-dis.c (X86_64_E8): New.
 831         (X86_64_E9): Likewise.
 832         Update comments on 'T', 'U', 'V'.  Add comments for '^'.
 833         (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
 834         (x86_64_table): Add X86_64_E8 and X86_64_E9.
 835         (mod_table): Replace {T|} with ^ on Jcall/Jmp.
 836         (putop): Handle '^'.
 837         (OP_J): Ignore the operand size prefix in 64-bit.  Don't check
 838         REX_W.
 839
 840 2015-04-30  DJ Delorie  <dj@redhat.com>
 841
 842         * disassemble.c (disassembler): Choose suitable disassembler based
 843         on E_ABI.
 844         * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
 845         it to decode mul/div insns.
 846         * rl78-decode.c: Regenerate.
 847         * rl78-dis.c (print_insn_rl78): Rename to...
 848         (print_insn_rl78_common): ...this, take ISA parameter.
 849         (print_insn_rl78): New.
 850         (print_insn_rl78_g10): New.
 851         (print_insn_rl78_g13): New.
 852         (print_insn_rl78_g14): New.
 853         (rl78_get_disassembler): New.
 854
 855 2015-04-29  Nick Clifton  <nickc@redhat.com>
 856
 857         * po/fr.po: Updated French translation.
 858
 859 2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>
 860
 861         * ppc-opc.c (DCBT_EO): New define.
 862         (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
 863         <lharx>: Likewise.
 864         <stbcx.>: Likewise.
 865         <sthcx.>: Likewise.
 866         <waitrsv>: Do not enable for POWER7 and later.
 867         <waitimpl>: Likewise.
 868         <dcbt>: Default to the two operand form of the instruction for all
 869         "old" cpus.  For "new" cpus, use the operand ordering that matches
 870         whether the cpu is server or embedded.
 871         <dcbtst>: Likewise.
 872
 873 2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 874
 875         * s390-opc.c: New instruction type VV0UU2.
 876         * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
 877         and WFC.
 878
 879 2015-04-23  Jan Beulich  <jbeulich@suse.com>
 880
 881         * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
 882         * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
 883         vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
 884         (vfpclasspd, vfpclassps): Add %XZ.
 885
 886 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 887
 888         * i386-dis.c (PREFIX_UD_SHIFT): Removed.
 889         (PREFIX_UD_REPZ): Likewise.
 890         (PREFIX_UD_REPNZ): Likewise.
 891         (PREFIX_UD_DATA): Likewise.
 892         (PREFIX_UD_ADDR): Likewise.
 893         (PREFIX_UD_LOCK): Likewise.
 894
 895 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 896
 897         * i386-dis.c (prefix_requirement): Removed.
 898         (print_insn): Don't set prefix_requirement.  Check
 899         dp->prefix_requirement instead of prefix_requirement.
 900
 901 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 902
 903         PR binutils/17898
 904         * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
 905         (PREFIX_MOD_0_0FC7_REG_6): This.
 906         (PREFIX_MOD_3_0FC7_REG_6): New.
 907         (PREFIX_MOD_3_0FC7_REG_7): Likewise.
 908         (prefix_table): Replace PREFIX_0FC7_REG_6 with
 909         PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
 910         PREFIX_MOD_3_0FC7_REG_7.
 911         (mod_table): Replace PREFIX_0FC7_REG_6 with
 912         PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
 913         PREFIX_MOD_3_0FC7_REG_7.
 914
 915 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 916
 917         * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
 918         (PREFIX_MANDATORY_REPNZ): Likewise.
 919         (PREFIX_MANDATORY_DATA): Likewise.
 920         (PREFIX_MANDATORY_ADDR): Likewise.
 921         (PREFIX_MANDATORY_LOCK): Likewise.
 922         (PREFIX_MANDATORY): Likewise.
 923         (PREFIX_UD_SHIFT): Set to 8
 924         (PREFIX_UD_REPZ): Updated.
 925         (PREFIX_UD_REPNZ): Likewise.
 926         (PREFIX_UD_DATA): Likewise.
 927         (PREFIX_UD_ADDR): Likewise.
 928         (PREFIX_UD_LOCK): Likewise.
 929         (PREFIX_IGNORED_SHIFT): New.
 930         (PREFIX_IGNORED_REPZ): Likewise.
 931         (PREFIX_IGNORED_REPNZ): Likewise.
 932         (PREFIX_IGNORED_DATA): Likewise.
 933         (PREFIX_IGNORED_ADDR): Likewise.
 934         (PREFIX_IGNORED_LOCK): Likewise.
 935         (PREFIX_OPCODE): Likewise.
 936         (PREFIX_IGNORED): Likewise.
 937         (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
 938         (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 939         (three_byte_table): Likewise.
 940         (mod_table): Likewise.
 941         (mandatory_prefix): Renamed to ...
 942         (prefix_requirement): This.
 943         (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 944         Update PREFIX_90 entry.
 945         (get_valid_dis386): Check prefix_requirement to see if a prefix
 946         should be ignored.
 947         (print_insn): Replace mandatory_prefix with prefix_requirement.
 948
 949 2015-04-15  Renlin Li  <renlin.li@arm.com>
 950
 951         * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
 952         use it for ssat and ssat16.
 953         (print_insn_thumb32): Add handle case for 'D' control code.
 954
 955 2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
 956             H.J. Lu  <hongjiu.lu@intel.com>
 957
 958         * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
 959         * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
 960         PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
 961         PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
 962         PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
 963         (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
 964         Fill prefix_requirement field.
 965         (struct dis386): Add prefix_requirement field.
 966         (dis386): Fill prefix_requirement field.
 967         (dis386_twobyte): Ditto.
 968         (twobyte_has_mandatory_prefix_: Remove.
 969         (reg_table): Fill prefix_requirement field.
 970         (prefix_table): Ditto.
 971         (x86_64_table): Ditto.
 972         (three_byte_table): Ditto.
 973         (xop_table): Ditto.
 974         (vex_table): Ditto.
 975         (vex_len_table): Ditto.
 976         (vex_w_table): Ditto.
 977         (mod_table): Ditto.
 978         (bad_opcode): Ditto.
 979         (print_insn): Use prefix_requirement.
 980         (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
 981         FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
 982         (float_reg): Ditto.
 983
 984 2015-03-30  Mike Frysinger  <vapier@gentoo.org>
 985
 986         * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
 987
 988 2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 989
 990         * Makefile.in: Regenerated.
 991
 992 2015-03-25  Anton Blanchard  <anton@samba.org>
 993
 994         * ppc-dis.c (disassemble_init_powerpc): Only initialise
 995         powerpc_opcd_indices and vle_opcd_indices once.
 996
 997 2015-03-25  Anton Blanchard  <anton@samba.org>
 998
 999         * ppc-opc.c (powerpc_opcodes): Add slbfee.
1000
1001 2015-03-24  Terry Guo  <terry.guo@arm.com>
1002
1003         * arm-dis.c (opcode32): Updated to use new arm feature struct.
1004         (opcode16): Likewise.
1005         (coprocessor_opcodes): Replace bit with feature struct.
1006         (neon_opcodes): Likewise.
1007         (arm_opcodes): Likewise.
1008         (thumb_opcodes): Likewise.
1009         (thumb32_opcodes): Likewise.
1010         (print_insn_coprocessor): Likewise.
1011         (print_insn_arm): Likewise.
1012         (select_arm_features): Follow new feature struct.
1013
1014 2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
1015
1016         * i386-dis.c (rm_table): Add clzero.
1017         * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
1018         Add CPU_CLZERO_FLAGS.
1019         (cpu_flags): Add CpuCLZERO.
1020         * i386-opc.h: Add CpuCLZERO.
1021         * i386-opc.tbl: Add clzero.
1022         * i386-init.h: Re-generated.
1023         * i386-tbl.h: Re-generated.
1024
1025 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
1026
1027         * mips-opc.c (decode_mips_operand): Fix constraint issues
1028         with u and y operands.
1029
1030 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
1031
1032         * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
1033
1034 2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1035
1036         * s390-opc.c: Add new IBM z13 instructions.
1037         * s390-opc.txt: Likewise.
1038
1039 2015-03-10  Renlin Li  <renlin.li@arm.com>
1040
1041         * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
1042         stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
1043         related alias.
1044         * aarch64-asm-2.c: Regenerate.
1045         * aarch64-dis-2.c: Likewise.
1046         * aarch64-opc-2.c: Likewise.
1047
1048 2015-03-03  Jiong Wang  <jiong.wang@arm.com>
1049
1050         * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
1051
1052 2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>
1053
1054         * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
1055         arch_sh_up.
1056         (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
1057         arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
1058
1059 2015-02-23  Vinay  <Vinay.G@kpit.com>
1060
1061         * rl78-decode.opc (MOV): Added space between two operands for
1062         'mov' instruction in index addressing mode.
1063         * rl78-decode.c: Regenerate.
1064
1065 2015-02-19  Pedro Alves  <palves@redhat.com>
1066
1067         * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
1068
1069 2015-02-10  Pedro Alves  <palves@redhat.com>
1070             Tom Tromey  <tromey@redhat.com>
1071
1072         * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
1073         microblaze_and, microblaze_xor.
1074         * microblaze-opc.h (opcodes): Adjust.
1075
1076 2015-01-28  James Bowman  <james.bowman@ftdichip.com>
1077
1078         * Makefile.am: Add FT32 files.
1079         * configure.ac: Handle FT32.
1080         * disassemble.c (disassembler): Call print_insn_ft32.
1081         * ft32-dis.c: New file.
1082         * ft32-opc.c: New file.
1083         * Makefile.in: Regenerate.
1084         * configure: Regenerate.
1085         * po/POTFILES.in: Regenerate.
1086
1087 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
1088
1089         * nds32-asm.c (keyword_sr): Add new system registers.
1090
1091 2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1092
1093         * s390-dis.c (s390_extract_operand): Support vector register
1094         operands.
1095         (s390_print_insn_with_opcode): Support new operands types and add
1096         new handling of optional operands.
1097         * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
1098         and include opcode/s390.h instead.
1099         (struct op_struct): New field `flags'.
1100         (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
1101         (dumpTable): Dump flags.
1102         (main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
1103         string.
1104         * s390-opc.c: Add new operands types, instruction formats, and
1105         instruction masks.
1106         (s390_opformats): Add new formats for .insn.
1107         * s390-opc.txt: Add new instructions.
1108
1109 2015-01-01  Alan Modra  <amodra@gmail.com>
1110
1111         Update year range in copyright notice of all files.
1112
1113 For older changes see ChangeLog-2014
1114 \f
1115 Copyright (C) 2015 Free Software Foundation, Inc.
1116
1117 Copying and distribution of this file, with or without modification,
1118 are permitted in any medium without royalty provided the copyright
1119 notice and this notice are preserved.
1120
1121 Local Variables:
1122 mode: change-log
1123 left-margin: 8
1124 fill-column: 74
1125 version-control: never
1126 End: