opcodes/ChangeLog

   1 2020-05-11  Alan Modra  <amodra@gmail.com>
   2
   3         * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
   4         xsmaxcqp, xsmincqp.
   5
   6 2020-05-11  Alan Modra  <amodra@gmail.com>
   7
   8         * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
   9         stxvrbx, stxvrhx, stxvrwx, stxvrdx.
  10
  11 2020-05-11  Alan Modra  <amodra@gmail.com>
  12
  13         * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
  14
  15 2020-05-11  Alan Modra  <amodra@gmail.com>
  16
  17         * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
  18         vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
  19
  20 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
  21
  22         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
  23         mnemonics.
  24
  25 2020-05-11  Alan Modra  <amodra@gmail.com>
  26
  27         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
  28         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
  29         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
  30         (prefix_opcodes): Add xxeval.
  31
  32 2020-05-11  Alan Modra  <amodra@gmail.com>
  33
  34         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
  35         xxgenpcvwm, xxgenpcvdm.
  36
  37 2020-05-11  Alan Modra  <amodra@gmail.com>
  38
  39         * ppc-opc.c (MP, VXVAM_MASK): Define.
  40         (VXVAPS_MASK): Use VXVA_MASK.
  41         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
  42         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
  43         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
  44         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
  45
  46 2020-05-11  Alan Modra  <amodra@gmail.com>
  47             Peter Bergner  <bergner@linux.ibm.com>
  48
  49         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
  50         New functions.
  51         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
  52         YMSK2, XA6a, XA6ap, XB6a entries.
  53         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
  54         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
  55         (PPCVSX4): Define.
  56         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
  57         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
  58         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
  59         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
  60         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
  61         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
  62         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
  63         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
  64         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
  65         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
  66         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
  67         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
  68         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
  69         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
  70
  71 2020-05-11  Alan Modra  <amodra@gmail.com>
  72
  73         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
  74         (insert_xts, extract_xts): New functions.
  75         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
  76         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
  77         (VXRC_MASK, VXSH_MASK): Define.
  78         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
  79         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
  80         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
  81         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
  82         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
  83         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
  84         xxblendvh, xxblendvw, xxblendvd, xxpermx.
  85
  86 2020-05-11  Alan Modra  <amodra@gmail.com>
  87
  88         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
  89         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
  90         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
  91         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
  92         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
  93
  94 2020-05-11  Alan Modra  <amodra@gmail.com>
  95
  96         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
  97         (XTP, DQXP, DQXP_MASK): Define.
  98         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
  99         (prefix_opcodes): Add plxvp and pstxvp.
 100
 101 2020-05-11  Alan Modra  <amodra@gmail.com>
 102
 103         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
 104         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
 105         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
 106
 107 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 108
 109         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
 110
 111 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 112
 113         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
 114         (L1OPT): Define.
 115         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
 116
 117 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 118
 119         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
 120
 121 2020-05-11  Alan Modra  <amodra@gmail.com>
 122
 123         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
 124
 125 2020-05-11  Alan Modra  <amodra@gmail.com>
 126
 127         * ppc-dis.c (ppc_opts): Add "power10" entry.
 128         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
 129         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
 130
 131 2020-05-11  Nick Clifton  <nickc@redhat.com>
 132
 133         * po/fr.po: Updated French translation.
 134
 135 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
 136
 137         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
 138         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
 139         (operand_general_constraint_met_p): validate
 140         AARCH64_OPND_UNDEFINED.
 141         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
 142         for FLD_imm16_2.
 143         * aarch64-asm-2.c: Regenerated.
 144         * aarch64-dis-2.c: Regenerated.
 145         * aarch64-opc-2.c: Regenerated.
 146
 147 2020-04-29  Nick Clifton  <nickc@redhat.com>
 148
 149         PR 22699
 150         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
 151         and SETRC insns.
 152
 153 2020-04-29  Nick Clifton  <nickc@redhat.com>
 154
 155         * po/sv.po: Updated Swedish translation.
 156
 157 2020-04-29  Nick Clifton  <nickc@redhat.com>
 158
 159         PR 22699
 160         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
 161         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
 162         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
 163         IMM0_8U case.
 164
 165 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
 166
 167         PR 25848
 168         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
 169         cmpi only on m68020up and cpu32.
 170
 171 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 172
 173         * aarch64-asm.c (aarch64_ins_none): New.
 174         * aarch64-asm.h (ins_none): New declaration.
 175         * aarch64-dis.c (aarch64_ext_none): New.
 176         * aarch64-dis.h (ext_none): New declaration.
 177         * aarch64-opc.c (aarch64_print_operand): Update case for
 178         AARCH64_OPND_BARRIER_PSB.
 179         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
 180         (AARCH64_OPERANDS): Update inserter/extracter for
 181         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
 182         * aarch64-asm-2.c: Regenerated.
 183         * aarch64-dis-2.c: Regenerated.
 184         * aarch64-opc-2.c: Regenerated.
 185
 186 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 187
 188         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
 189         (aarch64_feature_ras, RAS): Likewise.
 190         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
 191         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
 192         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
 193         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
 194         * aarch64-asm-2.c: Regenerated.
 195         * aarch64-dis-2.c: Regenerated.
 196         * aarch64-opc-2.c: Regenerated.
 197
 198 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
 199
 200         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
 201         (print_insn_neon): Support disassembly of conditional
 202         instructions.
 203
 204 2020-02-16  David Faust  <david.faust@oracle.com>
 205
 206         * bpf-desc.c: Regenerate.
 207         * bpf-desc.h: Likewise.
 208         * bpf-opc.c: Regenerate.
 209         * bpf-opc.h: Likewise.
 210
 211 2020-04-07  Lili Cui  <lili.cui@intel.com>
 212
 213         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
 214         (prefix_table): New instructions (see prefixes above).
 215         (rm_table): Likewise
 216         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
 217         CPU_ANY_TSXLDTRK_FLAGS.
 218         (cpu_flags): Add CpuTSXLDTRK.
 219         * i386-opc.h (enum): Add CpuTSXLDTRK.
 220         (i386_cpu_flags): Add cputsxldtrk.
 221         * i386-opc.tbl: Add XSUSPLDTRK insns.
 222         * i386-init.h: Regenerate.
 223         * i386-tbl.h: Likewise.
 224
 225 2020-04-02  Lili Cui  <lili.cui@intel.com>
 226
 227         * i386-dis.c (prefix_table): New instructions serialize.
 228         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
 229         CPU_ANY_SERIALIZE_FLAGS.
 230         (cpu_flags): Add CpuSERIALIZE.
 231         * i386-opc.h (enum): Add CpuSERIALIZE.
 232         (i386_cpu_flags): Add cpuserialize.
 233         * i386-opc.tbl: Add SERIALIZE insns.
 234         * i386-init.h: Regenerate.
 235         * i386-tbl.h: Likewise.
 236
 237 2020-03-26  Alan Modra  <amodra@gmail.com>
 238
 239         * disassemble.h (opcodes_assert): Declare.
 240         (OPCODES_ASSERT): Define.
 241         * disassemble.c: Don't include assert.h.  Include opintl.h.
 242         (opcodes_assert): New function.
 243         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 244         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 245         calculate maxlen.  Omit insn decoding when insn length exceeds
 246         maxlen.  Exit from nibble loop when looking for E, before
 247         accessing next data byte.  Move processing of E outside loop.
 248         Replace tests of maxlen in loop with assertions.
 249
 250 2020-03-26  Alan Modra  <amodra@gmail.com>
 251
 252         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 253
 254 2020-03-25  Alan Modra  <amodra@gmail.com>
 255
 256         * z80-dis.c (suffix): Init mybuf.
 257
 258 2020-03-22  Alan Modra  <amodra@gmail.com>
 259
 260         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 261         successflly read from section.
 262
 263 2020-03-22  Alan Modra  <amodra@gmail.com>
 264
 265         * arc-dis.c (find_format): Use ISO C string concatenation rather
 266         than line continuation within a string.  Don't access needs_limm
 267         before testing opcode != NULL.
 268
 269 2020-03-22  Alan Modra  <amodra@gmail.com>
 270
 271         * ns32k-dis.c (print_insn_arg): Update comment.
 272         (print_insn_ns32k): Reduce size of index_offset array, and
 273         initialize, passing -1 to print_insn_arg for args that are not
 274         an index.  Don't exit arg loop early.  Abort on bad arg number.
 275
 276 2020-03-22  Alan Modra  <amodra@gmail.com>
 277
 278         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 279         * s12z-opc.c: Formatting.
 280         (operands_f): Return an int.
 281         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 282         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 283         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 284         (exg_sex_discrim): Likewise.
 285         (create_immediate_operand, create_bitfield_operand),
 286         (create_register_operand_with_size, create_register_all_operand),
 287         (create_register_all16_operand, create_simple_memory_operand),
 288         (create_memory_operand, create_memory_auto_operand): Don't
 289         segfault on malloc failure.
 290         (z_ext24_decode): Return an int status, negative on fail, zero
 291         on success.
 292         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 293         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 294         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 295         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 296         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 297         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 298         (loop_primitive_decode, shift_decode, psh_pul_decode),
 299         (bit_field_decode): Similarly.
 300         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 301         to return value, update callers.
 302         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 303         Don't segfault on NULL operand.
 304         (decode_operation): Return OP_INVALID on first fail.
 305         (decode_s12z): Check all reads, returning -1 on fail.
 306
 307 2020-03-20  Alan Modra  <amodra@gmail.com>
 308
 309         * metag-dis.c (print_insn_metag): Don't ignore status from
 310         read_memory_func.
 311
 312 2020-03-20  Alan Modra  <amodra@gmail.com>
 313
 314         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 315         Initialize parts of buffer not written when handling a possible
 316         2-byte insn at end of section.  Don't attempt decoding of such
 317         an insn by the 4-byte machinery.
 318
 319 2020-03-20  Alan Modra  <amodra@gmail.com>
 320
 321         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 322         partially filled buffer.  Prevent lookup of 4-byte insns when
 323         only VLE 2-byte insns are possible due to section size.  Print
 324         ".word" rather than ".long" for 2-byte leftovers.
 325
 326 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 327
 328         PR 25641
 329         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 330
 331 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 332
 333         * i386-dis.c (X86_64_0D): Rename to ...
 334         (X86_64_0E): ... this.
 335
 336 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 337
 338         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 339         * Makefile.in: Regenerated.
 340
 341 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 342
 343         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 344         3-operand pseudos.
 345         * i386-tbl.h: Re-generate.
 346
 347 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 348
 349         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 350         vprot*, vpsha*, and vpshl*.
 351         * i386-tbl.h: Re-generate.
 352
 353 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 354
 355         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 356         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 357         * i386-tbl.h: Re-generate.
 358
 359 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 360
 361         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 362         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 363         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 364         * i386-tbl.h: Re-generate.
 365
 366 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 367
 368         * i386-gen.c (struct template_arg, struct template_instance,
 369         struct template_param, struct template, templates,
 370         parse_template, expand_templates): New.
 371         (process_i386_opcodes): Various local variables moved to
 372         expand_templates. Call parse_template and expand_templates.
 373         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 374         * i386-tbl.h: Re-generate.
 375
 376 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 377
 378         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 379         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 380         register and memory source templates. Replace VexW= by VexW*
 381         where applicable.
 382         * i386-tbl.h: Re-generate.
 383
 384 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 385
 386         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 387         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 388         * i386-tbl.h: Re-generate.
 389
 390 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 391
 392         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 393         * i386-tbl.h: Re-generate.
 394
 395 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 396
 397         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 398         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 399         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 400         VexW0 on SSE2AVX variants.
 401         (vmovq): Drop NoRex64 from XMM/XMM variants.
 402         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 403         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 404         applicable use VexW0.
 405         * i386-tbl.h: Re-generate.
 406
 407 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 408
 409         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 410         * i386-opc.h (Rex64): Delete.
 411         (struct i386_opcode_modifier): Remove rex64 field.
 412         * i386-opc.tbl (crc32): Drop Rex64.
 413         Replace Rex64 with Size64 everywhere else.
 414         * i386-tbl.h: Re-generate.
 415
 416 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 417
 418         * i386-dis.c (OP_E_memory): Exclude recording of used address
 419         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 420         addressed memory operands for MPX insns.
 421
 422 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 423
 424         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 425         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 426         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 427         (ptwrite): Split into non-64-bit and 64-bit forms.
 428         * i386-tbl.h: Re-generate.
 429
 430 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 431
 432         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 433         template.
 434         * i386-tbl.h: Re-generate.
 435
 436 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 437
 438         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 439         (prefix_table): Move vmmcall here. Add vmgexit.
 440         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 441         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 442         (cpu_flags): Add CpuSEV_ES entry.
 443         * i386-opc.h (CpuSEV_ES): New.
 444         (union i386_cpu_flags): Add cpusev_es field.
 445         * i386-opc.tbl (vmgexit): New.
 446         * i386-init.h, i386-tbl.h: Re-generate.
 447
 448 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 449
 450         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 451         with MnemonicSize.
 452         * i386-opc.h (IGNORESIZE): New.
 453         (DEFAULTSIZE): Likewise.
 454         (IgnoreSize): Removed.
 455         (DefaultSize): Likewise.
 456         (MnemonicSize): New.
 457         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 458         mnemonicsize.
 459         * i386-opc.tbl (IgnoreSize): New.
 460         (DefaultSize): Likewise.
 461         * i386-tbl.h: Regenerated.
 462
 463 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 464
 465         PR 25627
 466         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 467         instructions.
 468
 469 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 470
 471         PR gas/25622
 472         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 473         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 474         * i386-tbl.h: Regenerated.
 475
 476 2020-02-26  Alan Modra  <amodra@gmail.com>
 477
 478         * aarch64-asm.c: Indent labels correctly.
 479         * aarch64-dis.c: Likewise.
 480         * aarch64-gen.c: Likewise.
 481         * aarch64-opc.c: Likewise.
 482         * alpha-dis.c: Likewise.
 483         * i386-dis.c: Likewise.
 484         * nds32-asm.c: Likewise.
 485         * nfp-dis.c: Likewise.
 486         * visium-dis.c: Likewise.
 487
 488 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 489
 490         * arc-regs.h (int_vector_base): Make it available for all ARC
 491         CPUs.
 492
 493 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 494
 495         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 496         changed.
 497
 498 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 499
 500         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 501         c.mv/c.li if rs1 is zero.
 502
 503 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 504
 505         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 506         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 507         CPU_POPCNT_FLAGS.
 508         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 509         * i386-opc.h (CpuABM): Removed.
 510         (CpuPOPCNT): New.
 511         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 512         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 513         popcnt.  Remove CpuABM from lzcnt.
 514         * i386-init.h: Regenerated.
 515         * i386-tbl.h: Likewise.
 516
 517 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 518
 519         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 520         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 521         VexW1 instead of open-coding them.
 522         * i386-tbl.h: Re-generate.
 523
 524 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 525
 526         * i386-opc.tbl (AddrPrefixOpReg): Define.
 527         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 528         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 529         templates. Drop NoRex64.
 530         * i386-tbl.h: Re-generate.
 531
 532 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 533
 534         PR gas/6518
 535         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 536         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 537         into Intel syntax instance (with Unpsecified) and AT&T one
 538         (without).
 539         (vcvtneps2bf16): Likewise, along with folding the two so far
 540         separate ones.
 541         * i386-tbl.h: Re-generate.
 542
 543 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 544
 545         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 546         CPU_ANY_SSE4A_FLAGS.
 547
 548 2020-02-17  Alan Modra  <amodra@gmail.com>
 549
 550         * i386-gen.c (cpu_flag_init): Correct last change.
 551
 552 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 553
 554         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 555         CPU_ANY_SSE4_FLAGS.
 556
 557 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 558
 559         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 560         (movzx): Likewise.
 561
 562 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 563
 564         PR gas/25438
 565         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 566         destination for Cpu64-only variant.
 567         (movzx): Fold patterns.
 568         * i386-tbl.h: Re-generate.
 569
 570 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 571
 572         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 573         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 574         CPU_ANY_SSE4_FLAGS entry.
 575         * i386-init.h: Re-generate.
 576
 577 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 578
 579         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 580         with Unspecified, making the present one AT&T syntax only.
 581         * i386-tbl.h: Re-generate.
 582
 583 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 584
 585         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 586         * i386-tbl.h: Re-generate.
 587
 588 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 589
 590         PR gas/24546
 591         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 592         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 593         Amd64 and Intel64 templates.
 594         (call, jmp): Likewise for far indirect variants. Dro
 595         Unspecified.
 596         * i386-tbl.h: Re-generate.
 597
 598 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 599
 600         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 601         * i386-opc.h (ShortForm): Delete.
 602         (struct i386_opcode_modifier): Remove shortform field.
 603         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 604         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 605         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 606         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 607         Drop ShortForm.
 608         * i386-tbl.h: Re-generate.
 609
 610 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 611
 612         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 613         fucompi): Drop ShortForm from operand-less templates.
 614         * i386-tbl.h: Re-generate.
 615
 616 2020-02-11  Alan Modra  <amodra@gmail.com>
 617
 618         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 619         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 620         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 621         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 622         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 623
 624 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 625
 626         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 627         (cde_opcodes): Add VCX* instructions.
 628
 629 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 630             Matthew Malcomson  <matthew.malcomson@arm.com>
 631
 632         * arm-dis.c (struct cdeopcode32): New.
 633         (CDE_OPCODE): New macro.
 634         (cde_opcodes): New disassembly table.
 635         (regnames): New option to table.
 636         (cde_coprocs): New global variable.
 637         (print_insn_cde): New
 638         (print_insn_thumb32): Use print_insn_cde.
 639         (parse_arm_disassembler_options): Parse coprocN args.
 640
 641 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 642
 643         PR gas/25516
 644         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 645         with ISA64.
 646         * i386-opc.h (AMD64): Removed.
 647         (Intel64): Likewose.
 648         (AMD64): New.
 649         (INTEL64): Likewise.
 650         (INTEL64ONLY): Likewise.
 651         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 652         * i386-opc.tbl (Amd64): New.
 653         (Intel64): Likewise.
 654         (Intel64Only): Likewise.
 655         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 656         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 657         * i386-tbl.h: Regenerated.
 658
 659 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 660
 661         PR 25469
 662         * z80-dis.c: Add support for GBZ80 opcodes.
 663
 664 2020-02-04  Alan Modra  <amodra@gmail.com>
 665
 666         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 667
 668 2020-02-03  Alan Modra  <amodra@gmail.com>
 669
 670         * m32c-ibld.c: Regenerate.
 671
 672 2020-02-01  Alan Modra  <amodra@gmail.com>
 673
 674         * frv-ibld.c: Regenerate.
 675
 676 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 677
 678         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 679         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 680         (OP_E_memory): Replace xmm_mdq_mode case label by
 681         vex_scalar_w_dq_mode one.
 682         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 683
 684 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 685
 686         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 687         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 688         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 689         (intel_operand_size): Drop vex_w_dq_mode case label.
 690
 691 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 692
 693         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 694         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 695
 696 2020-01-30  Alan Modra  <amodra@gmail.com>
 697
 698         * m32c-ibld.c: Regenerate.
 699
 700 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 701
 702         * bpf-opc.c: Regenerate.
 703
 704 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 705
 706         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 707         (dis386): Use them to replace C2/C3 table entries.
 708         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 709         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 710         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 711         * i386-tbl.h: Re-generate.
 712
 713 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 714
 715         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 716         forms.
 717         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 718         DefaultSize.
 719         * i386-tbl.h: Re-generate.
 720
 721 2020-01-30  Alan Modra  <amodra@gmail.com>
 722
 723         * tic4x-dis.c (tic4x_dp): Make unsigned.
 724
 725 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 726             Jan Beulich  <jbeulich@suse.com>
 727
 728         PR binutils/25445
 729         * i386-dis.c (MOVSXD_Fixup): New function.
 730         (movsxd_mode): New enum.
 731         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 732         (intel_operand_size): Handle movsxd_mode.
 733         (OP_E_register): Likewise.
 734         (OP_G): Likewise.
 735         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 736         register on movsxd.  Add movsxd with 16-bit destination register
 737         for AMD64 and Intel64 ISAs.
 738         * i386-tbl.h: Regenerated.
 739
 740 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 741
 742         PR 25403
 743         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 744         * aarch64-asm-2.c: Regenerate
 745         * aarch64-dis-2.c: Likewise.
 746         * aarch64-opc-2.c: Likewise.
 747
 748 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 749
 750         * i386-opc.tbl (sysret): Drop DefaultSize.
 751         * i386-tbl.h: Re-generate.
 752
 753 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 754
 755         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 756         Dword.
 757         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 758         * i386-tbl.h: Re-generate.
 759
 760 2020-01-20  Nick Clifton  <nickc@redhat.com>
 761
 762         * po/de.po: Updated German translation.
 763         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 764         * po/uk.po: Updated Ukranian translation.
 765
 766 2020-01-20  Alan Modra  <amodra@gmail.com>
 767
 768         * hppa-dis.c (fput_const): Remove useless cast.
 769
 770 2020-01-20  Alan Modra  <amodra@gmail.com>
 771
 772         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 773
 774 2020-01-18  Nick Clifton  <nickc@redhat.com>
 775
 776         * configure: Regenerate.
 777         * po/opcodes.pot: Regenerate.
 778
 779 2020-01-18  Nick Clifton  <nickc@redhat.com>
 780
 781         Binutils 2.34 branch created.
 782
 783 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 784
 785         * opintl.h: Fix spelling error (seperate).
 786
 787 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 788
 789         * i386-opc.tbl: Add {vex} pseudo prefix.
 790         * i386-tbl.h: Regenerated.
 791
 792 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 793
 794         PR 25376
 795         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 796         (neon_opcodes): Likewise.
 797         (select_arm_features): Make sure we enable MVE bits when selecting
 798         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 799         any architecture.
 800
 801 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 802
 803         * i386-opc.tbl: Drop stale comment from XOP section.
 804
 805 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 806
 807         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 808         (extractps): Add VexWIG to SSE2AVX forms.
 809         * i386-tbl.h: Re-generate.
 810
 811 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 812
 813         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 814         Size64 from and use VexW1 on SSE2AVX forms.
 815         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 816         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 817         * i386-tbl.h: Re-generate.
 818
 819 2020-01-15  Alan Modra  <amodra@gmail.com>
 820
 821         * tic4x-dis.c (tic4x_version): Make unsigned long.
 822         (optab, optab_special, registernames): New file scope vars.
 823         (tic4x_print_register): Set up registernames rather than
 824         malloc'd registertable.
 825         (tic4x_disassemble): Delete optable and optable_special.  Use
 826         optab and optab_special instead.  Throw away old optab,
 827         optab_special and registernames when info->mach changes.
 828
 829 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 830
 831         PR 25377
 832         * z80-dis.c (suffix): Use .db instruction to generate double
 833         prefix.
 834
 835 2020-01-14  Alan Modra  <amodra@gmail.com>
 836
 837         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 838         values to unsigned before shifting.
 839
 840 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 841
 842         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 843         flow instructions.
 844         (print_insn_thumb16, print_insn_thumb32): Likewise.
 845         (print_insn): Initialize the insn info.
 846         * i386-dis.c (print_insn): Initialize the insn info fields, and
 847         detect jumps.
 848
 849 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 850
 851         * arc-opc.c (C_NE): Make it required.
 852
 853 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 854
 855         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 856         reserved register name.
 857
 858 2020-01-13  Alan Modra  <amodra@gmail.com>
 859
 860         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 861         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 862
 863 2020-01-13  Alan Modra  <amodra@gmail.com>
 864
 865         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 866         result of wasm_read_leb128 in a uint64_t and check that bits
 867         are not lost when copying to other locals.  Use uint32_t for
 868         most locals.  Use PRId64 when printing int64_t.
 869
 870 2020-01-13  Alan Modra  <amodra@gmail.com>
 871
 872         * score-dis.c: Formatting.
 873         * score7-dis.c: Formatting.
 874
 875 2020-01-13  Alan Modra  <amodra@gmail.com>
 876
 877         * score-dis.c (print_insn_score48): Use unsigned variables for
 878         unsigned values.  Don't left shift negative values.
 879         (print_insn_score32): Likewise.
 880         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 881
 882 2020-01-13  Alan Modra  <amodra@gmail.com>
 883
 884         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 885
 886 2020-01-13  Alan Modra  <amodra@gmail.com>
 887
 888         * fr30-ibld.c: Regenerate.
 889
 890 2020-01-13  Alan Modra  <amodra@gmail.com>
 891
 892         * xgate-dis.c (print_insn): Don't left shift signed value.
 893         (ripBits): Formatting, use 1u.
 894
 895 2020-01-10  Alan Modra  <amodra@gmail.com>
 896
 897         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 898         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 899
 900 2020-01-10  Alan Modra  <amodra@gmail.com>
 901
 902         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 903         and XRREG value earlier to avoid a shift with negative exponent.
 904         * m10200-dis.c (disassemble): Similarly.
 905
 906 2020-01-09  Nick Clifton  <nickc@redhat.com>
 907
 908         PR 25224
 909         * z80-dis.c (ld_ii_ii): Use correct cast.
 910
 911 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 912
 913         PR 25224
 914         * z80-dis.c (ld_ii_ii): Use character constant when checking
 915         opcode byte value.
 916
 917 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 918
 919         * i386-dis.c (SEP_Fixup): New.
 920         (SEP): Define.
 921         (dis386_twobyte): Use it for sysenter/sysexit.
 922         (enum x86_64_isa): Change amd64 enumerator to value 1.
 923         (OP_J): Compare isa64 against intel64 instead of amd64.
 924         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 925         forms.
 926         * i386-tbl.h: Re-generate.
 927
 928 2020-01-08  Alan Modra  <amodra@gmail.com>
 929
 930         * z8k-dis.c: Include libiberty.h
 931         (instr_data_s): Make max_fetched unsigned.
 932         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 933         Don't exceed byte_info bounds.
 934         (output_instr): Make num_bytes unsigned.
 935         (unpack_instr): Likewise for nibl_count and loop.
 936         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 937         idx unsigned.
 938         * z8k-opc.h: Regenerate.
 939
 940 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 941
 942         * arc-tbl.h (llock): Use 'LLOCK' as class.
 943         (llockd): Likewise.
 944         (scond): Use 'SCOND' as class.
 945         (scondd): Likewise.
 946         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 947         (scondd): Likewise.
 948
 949 2020-01-06  Alan Modra  <amodra@gmail.com>
 950
 951         * m32c-ibld.c: Regenerate.
 952
 953 2020-01-06  Alan Modra  <amodra@gmail.com>
 954
 955         PR 25344
 956         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 957         Peek at next byte to prevent recursion on repeated prefix bytes.
 958         Ensure uninitialised "mybuf" is not accessed.
 959         (print_insn_z80): Don't zero n_fetch and n_used here,..
 960         (print_insn_z80_buf): ..do it here instead.
 961
 962 2020-01-04  Alan Modra  <amodra@gmail.com>
 963
 964         * m32r-ibld.c: Regenerate.
 965
 966 2020-01-04  Alan Modra  <amodra@gmail.com>
 967
 968         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 969
 970 2020-01-04  Alan Modra  <amodra@gmail.com>
 971
 972         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 973
 974 2020-01-04  Alan Modra  <amodra@gmail.com>
 975
 976         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 977
 978 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 979
 980         * aarch64-tbl.h (aarch64_opcode_table): Use
 981         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 982
 983 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 984
 985         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 986         forms of SUDOT and USDOT.
 987
 988 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 989
 990         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 991         uzip{1,2}.
 992         * opcodes/aarch64-dis-2.c: Re-generate.
 993
 994 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 995
 996         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 997         FMMLA encoding.
 998         * opcodes/aarch64-dis-2.c: Re-generate.
 999
1000 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
1001
1002         * z80-dis.c: Add support for eZ80 and Z80 instructions.
1003
1004 2020-01-01  Alan Modra  <amodra@gmail.com>
1005
1006         Update year range in copyright notice of all files.
1007
1008 For older changes see ChangeLog-2019
1009 \f
1010 Copyright (C) 2020 Free Software Foundation, Inc.
1011
1012 Copying and distribution of this file, with or without modification,
1013 are permitted in any medium without royalty provided the copyright
1014 notice and this notice are preserved.
1015
1016 Local Variables:
1017 mode: change-log
1018 left-margin: 8
1019 fill-column: 74
1020 version-control: never
1021 End: