opcodes/ChangeLog

   1 2020-03-09  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
   4         vprot*, vpsha*, and vpshl*.
   5         * i386-tbl.h: Re-generate.
   6
   7 2020-03-09  Jan Beulich  <jbeulich@suse.com>
   8
   9         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
  10         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
  11         * i386-tbl.h: Re-generate.
  12
  13 2020-03-09  Jan Beulich  <jbeulich@suse.com>
  14
  15         * i386-gen.c (set_bitfield): Ignore zero-length field names.
  16         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
  17         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
  18         * i386-tbl.h: Re-generate.
  19
  20 2020-03-09  Jan Beulich  <jbeulich@suse.com>
  21
  22         * i386-gen.c (struct template_arg, struct template_instance,
  23         struct template_param, struct template, templates,
  24         parse_template, expand_templates): New.
  25         (process_i386_opcodes): Various local variables moved to
  26         expand_templates. Call parse_template and expand_templates.
  27         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
  28         * i386-tbl.h: Re-generate.
  29
  30 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  31
  32         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
  33         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
  34         register and memory source templates. Replace VexW= by VexW*
  35         where applicable.
  36         * i386-tbl.h: Re-generate.
  37
  38 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  39
  40         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
  41         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
  42         * i386-tbl.h: Re-generate.
  43
  44 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  45
  46         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
  47         * i386-tbl.h: Re-generate.
  48
  49 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  50
  51         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
  52         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
  53         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
  54         VexW0 on SSE2AVX variants.
  55         (vmovq): Drop NoRex64 from XMM/XMM variants.
  56         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
  57         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
  58         applicable use VexW0.
  59         * i386-tbl.h: Re-generate.
  60
  61 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  62
  63         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
  64         * i386-opc.h (Rex64): Delete.
  65         (struct i386_opcode_modifier): Remove rex64 field.
  66         * i386-opc.tbl (crc32): Drop Rex64.
  67         Replace Rex64 with Size64 everywhere else.
  68         * i386-tbl.h: Re-generate.
  69
  70 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  71
  72         * i386-dis.c (OP_E_memory): Exclude recording of used address
  73         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
  74         addressed memory operands for MPX insns.
  75
  76 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  77
  78         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
  79         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
  80         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
  81         (ptwrite): Split into non-64-bit and 64-bit forms.
  82         * i386-tbl.h: Re-generate.
  83
  84 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  85
  86         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
  87         template.
  88         * i386-tbl.h: Re-generate.
  89
  90 2020-03-04  Jan Beulich  <jbeulich@suse.com>
  91
  92         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
  93         (prefix_table): Move vmmcall here. Add vmgexit.
  94         (rm_table): Replace vmmcall entry by prefix_table[] escape.
  95         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
  96         (cpu_flags): Add CpuSEV_ES entry.
  97         * i386-opc.h (CpuSEV_ES): New.
  98         (union i386_cpu_flags): Add cpusev_es field.
  99         * i386-opc.tbl (vmgexit): New.
 100         * i386-init.h, i386-tbl.h: Re-generate.
 101
 102 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 103
 104         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 105         with MnemonicSize.
 106         * i386-opc.h (IGNORESIZE): New.
 107         (DEFAULTSIZE): Likewise.
 108         (IgnoreSize): Removed.
 109         (DefaultSize): Likewise.
 110         (MnemonicSize): New.
 111         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 112         mnemonicsize.
 113         * i386-opc.tbl (IgnoreSize): New.
 114         (DefaultSize): Likewise.
 115         * i386-tbl.h: Regenerated.
 116
 117 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 118
 119         PR 25627
 120         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 121         instructions.
 122
 123 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 124
 125         PR gas/25622
 126         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 127         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 128         * i386-tbl.h: Regenerated.
 129
 130 2020-02-26  Alan Modra  <amodra@gmail.com>
 131
 132         * aarch64-asm.c: Indent labels correctly.
 133         * aarch64-dis.c: Likewise.
 134         * aarch64-gen.c: Likewise.
 135         * aarch64-opc.c: Likewise.
 136         * alpha-dis.c: Likewise.
 137         * i386-dis.c: Likewise.
 138         * nds32-asm.c: Likewise.
 139         * nfp-dis.c: Likewise.
 140         * visium-dis.c: Likewise.
 141
 142 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 143
 144         * arc-regs.h (int_vector_base): Make it available for all ARC
 145         CPUs.
 146
 147 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 148
 149         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 150         changed.
 151
 152 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 153
 154         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 155         c.mv/c.li if rs1 is zero.
 156
 157 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 158
 159         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 160         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 161         CPU_POPCNT_FLAGS.
 162         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 163         * i386-opc.h (CpuABM): Removed.
 164         (CpuPOPCNT): New.
 165         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 166         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 167         popcnt.  Remove CpuABM from lzcnt.
 168         * i386-init.h: Regenerated.
 169         * i386-tbl.h: Likewise.
 170
 171 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 172
 173         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 174         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 175         VexW1 instead of open-coding them.
 176         * i386-tbl.h: Re-generate.
 177
 178 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 179
 180         * i386-opc.tbl (AddrPrefixOpReg): Define.
 181         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 182         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 183         templates. Drop NoRex64.
 184         * i386-tbl.h: Re-generate.
 185
 186 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 187
 188         PR gas/6518
 189         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 190         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 191         into Intel syntax instance (with Unpsecified) and AT&T one
 192         (without).
 193         (vcvtneps2bf16): Likewise, along with folding the two so far
 194         separate ones.
 195         * i386-tbl.h: Re-generate.
 196
 197 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 198
 199         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 200         CPU_ANY_SSE4A_FLAGS.
 201
 202 2020-02-17  Alan Modra  <amodra@gmail.com>
 203
 204         * i386-gen.c (cpu_flag_init): Correct last change.
 205
 206 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 207
 208         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 209         CPU_ANY_SSE4_FLAGS.
 210
 211 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 212
 213         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 214         (movzx): Likewise.
 215
 216 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 217
 218         PR gas/25438
 219         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 220         destination for Cpu64-only variant.
 221         (movzx): Fold patterns.
 222         * i386-tbl.h: Re-generate.
 223
 224 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 225
 226         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 227         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 228         CPU_ANY_SSE4_FLAGS entry.
 229         * i386-init.h: Re-generate.
 230
 231 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 232
 233         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 234         with Unspecified, making the present one AT&T syntax only.
 235         * i386-tbl.h: Re-generate.
 236
 237 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 238
 239         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 240         * i386-tbl.h: Re-generate.
 241
 242 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 243
 244         PR gas/24546
 245         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 246         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 247         Amd64 and Intel64 templates.
 248         (call, jmp): Likewise for far indirect variants. Dro
 249         Unspecified.
 250         * i386-tbl.h: Re-generate.
 251
 252 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 253
 254         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 255         * i386-opc.h (ShortForm): Delete.
 256         (struct i386_opcode_modifier): Remove shortform field.
 257         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 258         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 259         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 260         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 261         Drop ShortForm.
 262         * i386-tbl.h: Re-generate.
 263
 264 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 265
 266         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 267         fucompi): Drop ShortForm from operand-less templates.
 268         * i386-tbl.h: Re-generate.
 269
 270 2020-02-11  Alan Modra  <amodra@gmail.com>
 271
 272         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 273         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 274         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 275         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 276         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 277
 278 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 279
 280         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 281         (cde_opcodes): Add VCX* instructions.
 282
 283 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 284             Matthew Malcomson  <matthew.malcomson@arm.com>
 285
 286         * arm-dis.c (struct cdeopcode32): New.
 287         (CDE_OPCODE): New macro.
 288         (cde_opcodes): New disassembly table.
 289         (regnames): New option to table.
 290         (cde_coprocs): New global variable.
 291         (print_insn_cde): New
 292         (print_insn_thumb32): Use print_insn_cde.
 293         (parse_arm_disassembler_options): Parse coprocN args.
 294
 295 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 296
 297         PR gas/25516
 298         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 299         with ISA64.
 300         * i386-opc.h (AMD64): Removed.
 301         (Intel64): Likewose.
 302         (AMD64): New.
 303         (INTEL64): Likewise.
 304         (INTEL64ONLY): Likewise.
 305         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 306         * i386-opc.tbl (Amd64): New.
 307         (Intel64): Likewise.
 308         (Intel64Only): Likewise.
 309         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 310         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 311         * i386-tbl.h: Regenerated.
 312
 313 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 314
 315         PR 25469
 316         * z80-dis.c: Add support for GBZ80 opcodes.
 317
 318 2020-02-04  Alan Modra  <amodra@gmail.com>
 319
 320         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 321
 322 2020-02-03  Alan Modra  <amodra@gmail.com>
 323
 324         * m32c-ibld.c: Regenerate.
 325
 326 2020-02-01  Alan Modra  <amodra@gmail.com>
 327
 328         * frv-ibld.c: Regenerate.
 329
 330 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 331
 332         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 333         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 334         (OP_E_memory): Replace xmm_mdq_mode case label by
 335         vex_scalar_w_dq_mode one.
 336         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 337
 338 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 339
 340         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 341         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 342         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 343         (intel_operand_size): Drop vex_w_dq_mode case label.
 344
 345 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 346
 347         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 348         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 349
 350 2020-01-30  Alan Modra  <amodra@gmail.com>
 351
 352         * m32c-ibld.c: Regenerate.
 353
 354 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 355
 356         * bpf-opc.c: Regenerate.
 357
 358 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 359
 360         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 361         (dis386): Use them to replace C2/C3 table entries.
 362         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 363         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 364         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 365         * i386-tbl.h: Re-generate.
 366
 367 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 368
 369         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 370         forms.
 371         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 372         DefaultSize.
 373         * i386-tbl.h: Re-generate.
 374
 375 2020-01-30  Alan Modra  <amodra@gmail.com>
 376
 377         * tic4x-dis.c (tic4x_dp): Make unsigned.
 378
 379 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 380             Jan Beulich  <jbeulich@suse.com>
 381
 382         PR binutils/25445
 383         * i386-dis.c (MOVSXD_Fixup): New function.
 384         (movsxd_mode): New enum.
 385         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 386         (intel_operand_size): Handle movsxd_mode.
 387         (OP_E_register): Likewise.
 388         (OP_G): Likewise.
 389         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 390         register on movsxd.  Add movsxd with 16-bit destination register
 391         for AMD64 and Intel64 ISAs.
 392         * i386-tbl.h: Regenerated.
 393
 394 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 395
 396         PR 25403
 397         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 398         * aarch64-asm-2.c: Regenerate
 399         * aarch64-dis-2.c: Likewise.
 400         * aarch64-opc-2.c: Likewise.
 401
 402 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 403
 404         * i386-opc.tbl (sysret): Drop DefaultSize.
 405         * i386-tbl.h: Re-generate.
 406
 407 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 408
 409         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 410         Dword.
 411         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 412         * i386-tbl.h: Re-generate.
 413
 414 2020-01-20  Nick Clifton  <nickc@redhat.com>
 415
 416         * po/de.po: Updated German translation.
 417         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 418         * po/uk.po: Updated Ukranian translation.
 419
 420 2020-01-20  Alan Modra  <amodra@gmail.com>
 421
 422         * hppa-dis.c (fput_const): Remove useless cast.
 423
 424 2020-01-20  Alan Modra  <amodra@gmail.com>
 425
 426         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 427
 428 2020-01-18  Nick Clifton  <nickc@redhat.com>
 429
 430         * configure: Regenerate.
 431         * po/opcodes.pot: Regenerate.
 432
 433 2020-01-18  Nick Clifton  <nickc@redhat.com>
 434
 435         Binutils 2.34 branch created.
 436
 437 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 438
 439         * opintl.h: Fix spelling error (seperate).
 440
 441 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 442
 443         * i386-opc.tbl: Add {vex} pseudo prefix.
 444         * i386-tbl.h: Regenerated.
 445
 446 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 447
 448         PR 25376
 449         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 450         (neon_opcodes): Likewise.
 451         (select_arm_features): Make sure we enable MVE bits when selecting
 452         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 453         any architecture.
 454
 455 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 456
 457         * i386-opc.tbl: Drop stale comment from XOP section.
 458
 459 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 460
 461         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 462         (extractps): Add VexWIG to SSE2AVX forms.
 463         * i386-tbl.h: Re-generate.
 464
 465 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 466
 467         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 468         Size64 from and use VexW1 on SSE2AVX forms.
 469         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 470         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 471         * i386-tbl.h: Re-generate.
 472
 473 2020-01-15  Alan Modra  <amodra@gmail.com>
 474
 475         * tic4x-dis.c (tic4x_version): Make unsigned long.
 476         (optab, optab_special, registernames): New file scope vars.
 477         (tic4x_print_register): Set up registernames rather than
 478         malloc'd registertable.
 479         (tic4x_disassemble): Delete optable and optable_special.  Use
 480         optab and optab_special instead.  Throw away old optab,
 481         optab_special and registernames when info->mach changes.
 482
 483 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 484
 485         PR 25377
 486         * z80-dis.c (suffix): Use .db instruction to generate double
 487         prefix.
 488
 489 2020-01-14  Alan Modra  <amodra@gmail.com>
 490
 491         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 492         values to unsigned before shifting.
 493
 494 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 495
 496         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 497         flow instructions.
 498         (print_insn_thumb16, print_insn_thumb32): Likewise.
 499         (print_insn): Initialize the insn info.
 500         * i386-dis.c (print_insn): Initialize the insn info fields, and
 501         detect jumps.
 502
 503 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 504
 505         * arc-opc.c (C_NE): Make it required.
 506
 507 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 508
 509         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 510         reserved register name.
 511
 512 2020-01-13  Alan Modra  <amodra@gmail.com>
 513
 514         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 515         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 516
 517 2020-01-13  Alan Modra  <amodra@gmail.com>
 518
 519         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 520         result of wasm_read_leb128 in a uint64_t and check that bits
 521         are not lost when copying to other locals.  Use uint32_t for
 522         most locals.  Use PRId64 when printing int64_t.
 523
 524 2020-01-13  Alan Modra  <amodra@gmail.com>
 525
 526         * score-dis.c: Formatting.
 527         * score7-dis.c: Formatting.
 528
 529 2020-01-13  Alan Modra  <amodra@gmail.com>
 530
 531         * score-dis.c (print_insn_score48): Use unsigned variables for
 532         unsigned values.  Don't left shift negative values.
 533         (print_insn_score32): Likewise.
 534         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 535
 536 2020-01-13  Alan Modra  <amodra@gmail.com>
 537
 538         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 539
 540 2020-01-13  Alan Modra  <amodra@gmail.com>
 541
 542         * fr30-ibld.c: Regenerate.
 543
 544 2020-01-13  Alan Modra  <amodra@gmail.com>
 545
 546         * xgate-dis.c (print_insn): Don't left shift signed value.
 547         (ripBits): Formatting, use 1u.
 548
 549 2020-01-10  Alan Modra  <amodra@gmail.com>
 550
 551         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 552         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 553
 554 2020-01-10  Alan Modra  <amodra@gmail.com>
 555
 556         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 557         and XRREG value earlier to avoid a shift with negative exponent.
 558         * m10200-dis.c (disassemble): Similarly.
 559
 560 2020-01-09  Nick Clifton  <nickc@redhat.com>
 561
 562         PR 25224
 563         * z80-dis.c (ld_ii_ii): Use correct cast.
 564
 565 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 566
 567         PR 25224
 568         * z80-dis.c (ld_ii_ii): Use character constant when checking
 569         opcode byte value.
 570
 571 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 572
 573         * i386-dis.c (SEP_Fixup): New.
 574         (SEP): Define.
 575         (dis386_twobyte): Use it for sysenter/sysexit.
 576         (enum x86_64_isa): Change amd64 enumerator to value 1.
 577         (OP_J): Compare isa64 against intel64 instead of amd64.
 578         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 579         forms.
 580         * i386-tbl.h: Re-generate.
 581
 582 2020-01-08  Alan Modra  <amodra@gmail.com>
 583
 584         * z8k-dis.c: Include libiberty.h
 585         (instr_data_s): Make max_fetched unsigned.
 586         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 587         Don't exceed byte_info bounds.
 588         (output_instr): Make num_bytes unsigned.
 589         (unpack_instr): Likewise for nibl_count and loop.
 590         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 591         idx unsigned.
 592         * z8k-opc.h: Regenerate.
 593
 594 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 595
 596         * arc-tbl.h (llock): Use 'LLOCK' as class.
 597         (llockd): Likewise.
 598         (scond): Use 'SCOND' as class.
 599         (scondd): Likewise.
 600         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 601         (scondd): Likewise.
 602
 603 2020-01-06  Alan Modra  <amodra@gmail.com>
 604
 605         * m32c-ibld.c: Regenerate.
 606
 607 2020-01-06  Alan Modra  <amodra@gmail.com>
 608
 609         PR 25344
 610         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 611         Peek at next byte to prevent recursion on repeated prefix bytes.
 612         Ensure uninitialised "mybuf" is not accessed.
 613         (print_insn_z80): Don't zero n_fetch and n_used here,..
 614         (print_insn_z80_buf): ..do it here instead.
 615
 616 2020-01-04  Alan Modra  <amodra@gmail.com>
 617
 618         * m32r-ibld.c: Regenerate.
 619
 620 2020-01-04  Alan Modra  <amodra@gmail.com>
 621
 622         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 623
 624 2020-01-04  Alan Modra  <amodra@gmail.com>
 625
 626         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 627
 628 2020-01-04  Alan Modra  <amodra@gmail.com>
 629
 630         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 631
 632 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 633
 634         * aarch64-tbl.h (aarch64_opcode_table): Use
 635         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 636
 637 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 638
 639         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 640         forms of SUDOT and USDOT.
 641
 642 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 643
 644         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 645         uzip{1,2}.
 646         * opcodes/aarch64-dis-2.c: Re-generate.
 647
 648 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 649
 650         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 651         FMMLA encoding.
 652         * opcodes/aarch64-dis-2.c: Re-generate.
 653
 654 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 655
 656         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 657
 658 2020-01-01  Alan Modra  <amodra@gmail.com>
 659
 660         Update year range in copyright notice of all files.
 661
 662 For older changes see ChangeLog-2019
 663 \f
 664 Copyright (C) 2020 Free Software Foundation, Inc.
 665
 666 Copying and distribution of this file, with or without modification,
 667 are permitted in any medium without royalty provided the copyright
 668 notice and this notice are preserved.
 669
 670 Local Variables:
 671 mode: change-log
 672 left-margin: 8
 673 fill-column: 74
 674 version-control: never
 675 End: