opcodes/ChangeLog

   1 2014-12-12  Anthony Green  <green@moxielogic.com>
   2
   3         * moxie-opc.c: Define zex instructions.
   4
   5 2014-12-06  Eric Botcazou  <ebotcazou@adacore.com>
   6
   7         * configure.ac: Add Visium support.
   8         * configure: Regenerate.
   9         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add visium-dis.c and
  10         visium-opc.c.
  11         * Makefile.in: Regenerate.
  12         * disassemble.c (ARCH_visium): Define if ARCH_all.
  13         (disassembler): Deal with bfd_arch_visium if ARCH_visium.
  14         * visium-dis.c: New file.
  15         * visium-opc.c: Likewise.
  16         * po/POTFILES.in: Regenerate.
  17
  18 2014-11-30  Alan Modra  <amodra@gmail.com>
  19
  20         * ppc-opc.c (powerpc_opcodes): Make mftb* generate mfspr for
  21         power4 and later.
  22
  23 2014-11-28  Sandra Loosemore  <sandra@codesourcery.com>
  24
  25         * nios2-opc.c (nios2_r1_opcodes): Remove deleted attributes
  26         from descriptors.
  27
  28 2014-11-28  Alan Modra  <amodra@gmail.com>
  29
  30         * ppc-opc.c (powerpc_opcodes <mftb>): Don't deprecate for power7.
  31         (TB): Delete.
  32         (insert_tbr, extract_tbr): Validate tbr number.
  33
  34 2014-11-24  H.J. Lu  <hongjiu.lu@intel.com>
  35
  36         * configure: Regenerated.
  37
  38 2014-11-17  Ilya Tocar  <ilya.tocar@intel.com>
  39
  40         * i386-dis-evex.c (evex_table): Add vpermi2b, vpermt2b, vpermb,
  41         vpmultishiftqb.
  42         * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F3883, EVEX_W_0F3883_P_2.
  43         * i386-gen.c (cpu_flag_init): Add CPU_AVX512VBMI_FLAGS.
  44         (cpu_flags): Add CpuAVX512VBMI.
  45         * i386-opc.h (enum): Add CpuAVX512VBMI.
  46         (i386_cpu_flags): Add cpuavx512vbmi.
  47         * i386-opc.tbl: Add vpmadd52luq, vpmultishiftqb, vpermb, vpermi2b,
  48         vpermt2b.
  49         * i386-init.h: Regenerated.
  50         * i386-tbl.h: Likewise.
  51
  52 2014-11-17  Ilya Tocar  <ilya.tocar@intel.com>
  53
  54         * i386-dis-evex.c (evex_table): Add vpmadd52luq, vpmadd52huq.
  55         * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F38B4,
  56         PREFIX_EVEX_0F38B5.
  57         * i386-gen.c (cpu_flag_init): Add CPU_AVX512IFMA_FLAGS.
  58         (cpu_flags): Add CpuAVX512IFMA.
  59         * i386-opc.h (enum): Add CpuAVX512IFMA.
  60         (i386_cpu_flags): Add cpuavx512ifma.
  61         * i386-opc.tbl: Add vpmadd52huq, vpmadd52luq.
  62         * i386-init.h: Regenerated.
  63         * i386-tbl.h: Likewise.
  64
  65 2014-11-17  Ilya Tocar  <ilya.tocar@intel.com>
  66
  67         * i386-dis.c (PREFIX enum): Add PREFIX_RM_0_0FAE_REG_7.
  68         (prefix_table): Add pcommit.
  69         * i386-gen.c (cpu_flag_init): Add CPU_PCOMMIT_FLAGS.
  70         (cpu_flags): Add CpuPCOMMIT.
  71         * i386-opc.h (enum): Add CpuPCOMMIT.
  72         (i386_cpu_flags): Add cpupcommit.
  73         * i386-opc.tbl: Add pcommit.
  74         * i386-init.h: Regenerated.
  75         * i386-tbl.h: Likewise.
  76
  77 2014-11-17  Ilya Tocar  <ilya.tocar@intel.com>
  78
  79         * i386-dis.c (PREFIX enum): Add PREFIX_0FAE_REG_6.
  80         (prefix_table): Add clwb.
  81         * i386-gen.c (cpu_flag_init): Add CPU_CLWB_FLAGS.
  82         (cpu_flags): Add CpuCLWB.
  83         * i386-opc.h (enum): Add CpuCLWB.
  84         (i386_cpu_flags): Add cpuclwb.
  85         * i386-opc.tbl: Add clwb.
  86         * i386-init.h: Regenerated.
  87         * i386-tbl.h: Likewise.
  88
  89 2014-11-06  Sandra Loosemore  <sandra@codesourcery.com>
  90
  91         * nios2-dis.c (nios2_find_opcode_hash): Add mach parameter.
  92         (nios2_disassemble): Adjust call to nios2_find_opcode_hash.
  93
  94 2014-11-03  Nick Clifton  <nickc@redhat.com>
  95
  96         * po/fi.po: Updated Finnish translation.
  97
  98 2014-10-31  Andrew Pinski  <apinski@cavium.com>
  99             Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>
 100
 101         * mips-dis.c (mips_arch_choices): Add octeon3.
 102         * mips-opc.c (IOCT): Include INSN_OCTEON3.
 103         (IOCT2): Likewise.
 104         (IOCT3): New define.
 105         (IVIRT): New define.
 106         (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 107         tlbinv, tlbinvf, tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp, tlti
 108         IVIRT instructions.
 109         Extend mtm0, mtm1, mtm2, mtp0, mtp1, mtp2 instructions to take another
 110         operand for IOCT3.
 111
 112 2014-10-29  Nick Clifton  <nickc@redhat.com>
 113
 114         * po/de.po: Updated German translation.
 115
 116 2014-10-23  Sandra Loosemore  <sandra@codesourcery.com>
 117
 118         * nios2-opc.c (nios2_builtin_regs): Add regtype field initializers.
 119         (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.  Use new
 120         MATCH_R1_<insn> and MASK_R1_<insn> macros in initializers.  Add
 121         size and format initializers.  Merge 'b' arguments into 'j'.
 122         (NIOS2_NUM_OPCODES): Adjust definition.
 123         (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
 124         (nios2_opcodes): Adjust.
 125         (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
 126         * nios2-dis.c (INSNLEN): Update comment.
 127         (nios2_hash_init, nios2_hash): Delete.
 128         (OPCODE_HASH_SIZE): New.
 129         (nios2_r1_extract_opcode): New.
 130         (nios2_disassembler_state): New.
 131         (nios2_r1_disassembler_state): New.
 132         (nios2_init_opcode_hash): Add state parameter.  Adjust to use it.
 133         (nios2_find_opcode_hash): Use state object.
 134         (bad_opcode): New.
 135         (nios2_print_insn_arg): Add op parameter.  Use it to access
 136         format.  Remove 'b' case.
 137         (nios2_disassemble): Remove special case for nop.  Remove
 138         hard-coded instruction size.
 139
 140 2014-10-21  Jan Beulich  <jbeulich@suse.com>
 141
 142         * ppc-opc.c (powerpc_opcodes): Enable msgclr and msgsnd on Power8.
 143
 144 2014-10-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 145
 146         * sparc-opc.c (sparc-opcodes): Fix several misplaced hwcap
 147         entries.
 148         Annotate several instructions with the HWCAP2_VIS3B hwcap.
 149
 150 2014-10-15  Tristan Gingold  <gingold@adacore.com>
 151
 152         * configure: Regenerate.
 153
 154 2014-10-09  Jose E. Marchesi  &lt;jose.marchesi@oracle.com&gt;
 155
 156         * sparc-opc.c (sparc-opcodes): Remove instructions `chkpt',
 157         `commit', `random', `wr r,r,%cps', `wr r,i,%cps' and `rd %cps,r'.
 158         Annotate table with HWCAP2 bits.
 159         Add instructions xmontmul, xmontsqr, xmpmul.
 160         (sparc-opcodes): Add the `mwait',  `wr r,r,%mwait', `wr
 161         r,i,%mwait' and `rd %mwait,r' instructions.
 162         Add rd/wr instructions for accessing the %mcdper ancillary state
 163         register.
 164         (sparc-opcodes): Add sparc5/vis4.0 instructions:
 165         subxc, subxccc, fpadd8, fpadds8, fpaddus8, fpaddus16, fpcmple8,
 166         fpcmpgt8, fpcmpule16, fpcmpugt16, fpcmpule32, fpcmpugt32, fpmax8,
 167         fpmax16, fpmax32, fpmaxu8, fpmaxu16, fpmaxu32, fpmin8, fpmin16,
 168         fpmin32, fpminu8, fpminu16, fpminu32, fpsub8, fpsubs8, fpsubus8,
 169         fpsubus16, and faligndatai.
 170         * sparc-dis.c (v9a_asr_reg_names): Add the %mwait (%asr28)
 171         ancillary state register to the table.
 172         (print_insn_sparc): Handle the %mcdper ancillary state register.
 173         (print_insn_sparc): Handle new operand type '}'.
 174
 175 2014-09-22  H.J. Lu  <hongjiu.lu@intel.com>
 176
 177         * i386-dis.c (MOD_0F20): Removed.
 178         (MOD_0F21): Likewise.
 179         (MOD_0F22): Likewise.
 180         (MOD_0F23): Likewise.
 181         (dis386_twobyte): Replace MOD_0F20, MOD_0F21, MOD_0F22 and
 182         MOD_0F23 with "movZ".
 183         (mod_table): Remove MOD_0F20, MOD_0F21, MOD_0F22 and MOD_0F23.
 184         (OP_R): Check mod/rm byte and call OP_E_register.
 185
 186 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
 187
 188         * nds32-asm.c (nds32_opcodes, operand_fields, keyword_im5_i,
 189         keyword_im5_m, keyword_accumulator, keyword_aridx, keyword_aridx2,
 190         keyword_aridxi): Add audio ISA extension.
 191         (keyword_gpr, keyword_usr, keyword_sr, keyword_cp, keyword_cpr,
 192         keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm, keyword_dpref_st,
 193         keyword_cctl_lv, keyword_standby_st, keyword_msync_st): Adjust scrope
 194         for nds32-dis.c using.
 195         (build_opcode_syntax): Remove dead code.
 196         (parse_re, parse_a30b20, parse_rt21, parse_rte_start, parse_rte_end,
 197         parse_rte69_start, parse_rte69_end, parse_im5_ip, parse_im5_mr,
 198         parse_im6_ip, parse_im6_iq, parse_im6_mr, parse_im6_ms): Add audio ISA
 199         operand parser.
 200         * nds32-asm.h: Declare.
 201         * nds32-dis.c: Use array nds32_opcodes to disassemble instead of
 202         decoding by switch.
 203
 204 2014-09-15  Andrew Bennett  <andrew.bennett@imgtec.com>
 205             Matthew Fortune  <matthew.fortune@imgtec.com>
 206
 207         * mips-dis.c (mips_arch_choices): Add entries for mips32r6 and
 208         mips64r6.
 209         (parse_mips_dis_option): Allow MSA and virtualization support for
 210         mips64r6.
 211         (mips_print_arg_state): Add fields dest_regno and seen_dest.
 212         (mips_seen_register): New function.
 213         (print_insn_arg): Refactored code to use mips_seen_register
 214         function.  Add support for OP_SAME_RS_RT, OP_CHECK_PREV and
 215         OP_NON_ZERO_REG.  Changed OP_REPEAT_DEST_REG case to print out
 216         the register rather than aborting.
 217         (print_insn_args): Add length argument.  Add code to correctly
 218         calculate the instruction address for pc relative instructions.
 219         (validate_insn_args): New static function.
 220         (print_insn_mips): Prevent jalx disassembling for r6.  Use
 221         validate_insn_args.
 222         (print_insn_micromips): Use validate_insn_args.
 223         all the arguments are valid.
 224         * mips-formats.h (PREV_CHECK): New define.
 225         * mips-opc.c (decode_mips_operand): Add support for -a, -b, -d, -s,
 226         -t, -u, -v, -w, -x, -y, -A, -B, +I, +O, +R, +:, +\, +", +;
 227         (RD_pc): New define.
 228         (FS): New define.
 229         (I37): New define.
 230         (I69): New define.
 231         (mips_builtin_opcodes): Add MIPS R6 instructions.  Exclude recoded
 232         MIPS R6 instructions from MIPS R2 instructions.
 233
 234 2014-09-10  H.J. Lu  <hongjiu.lu@intel.com>
 235
 236         * i386-dis.c (dis386): Replace "P" with "%LP" for iret and sysret.
 237         (putop): Handle "%LP".
 238
 239 2014-09-03  Jiong Wang  <jiong.wang@arm.com>
 240
 241         * aarch64-tbl.h (aarch64_opcode_table): Update encoding for mrs/msr.
 242         * aarch64-dis-2.c: Update auto-generated file.
 243
 244 2014-09-03  Jiong Wang  <jiong.wang@arm.com>
 245
 246         * aarch64-tbl.h (QL_R4NIL): New qualifiers.
 247         (aarch64_feature_lse): New feature added.
 248         (LSE): New Added.
 249         (aarch64_opcode_table): New LSE instructions added.  Improve
 250         descriptions for ldarb/ldarh/ldar.
 251         (aarch64_opcode_table): Describe PAIRREG.
 252         * aarch64-opc.h (aarch64_field_kind): Add FLD_lse_sz.
 253         * aarch64-opc.c (fields): Add entry for F_LSE_SZ.
 254         (aarch64_print_operand): Recognize PAIRREG.
 255         (operand_general_constraint_met_p): Check reg pair constraints for CASP
 256         instructions.
 257         * aarch64-dis.c (aarch64_ext_regno_pair): New extractor for paired reg.
 258         (do_special_decoding): Recognize F_LSE_SZ.
 259         * aarch64-asm.c (do_special_encoding): Recognize F_LSE_SZ.
 260
 261 2014-08-26  Maciej W. Rozycki  <macro@codesourcery.com>
 262
 263         * micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'.
 264         (micromips_opcodes): Use "+J" in place of "B" for "hypcall",
 265         "sdbbp", "syscall" and "wait".
 266
 267 2014-08-21  Nathan Sidwell  <nathan@codesourcery.com>
 268             Maciej W. Rozycki  <macro@codesourcery.com>
 269
 270         * arm-dis.c (print_arm_address): Negate the GPR-relative offset
 271         returned if the U bit is set.
 272
 273 2014-08-21  Maciej W. Rozycki  <macro@codesourcery.com>
 274
 275         * micromips-opc.c (micromips_opcodes): Remove #ifdef-ed out
 276         48-bit "li" encoding.
 277
 278 2014-08-19  Andreas Arnez  <arnez@linux.vnet.ibm.com>
 279
 280         * s390-dis.c (s390_insn_length, s390_insn_matches_opcode)
 281         (s390_print_insn_with_opcode, opcode_mask_more_specific): New
 282         static functions, code was moved from...
 283         (print_insn_s390): ...here.
 284         (s390_extract_operand): Adjust comment.  Change type of first
 285         parameter from 'unsigned char *' to 'const bfd_byte *'.
 286         (union operand_value): New.
 287         (s390_extract_operand): Change return type to union operand_value.
 288         Also avoid integer overflow in sign-extension.
 289         (s390_print_insn_with_opcode): Adjust to changed return value from
 290         s390_extract_operand().  Change "%i" printf format to "%u" for
 291         unsigned values.
 292         (init_disasm): Simplify initialization of opc_index[].  This also
 293         fixes an access after the last element of s390_opcodes[].
 294         (print_insn_s390): Simplify the opcode search loop.
 295         Check architecture mask against all searched opcodes, not just the
 296         first matching one.
 297         (s390_print_insn_with_opcode): Drop function pointer dereferences
 298         without effect.
 299         (print_insn_s390): Likewise.
 300         (s390_insn_length): Simplify formula for return value.
 301         (s390_print_insn_with_opcode): Avoid special handling for the
 302         separator before the first operand.  Use new local variable
 303         'flags' in place of 'operand->flags'.
 304
 305 2014-08-14  Mike Frysinger  <vapier@gentoo.org>
 306
 307         * bfin-dis.c (struct private): Change int's to bfd_boolean's.
 308         (decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
 309         decode_dagMODik_0, decode_LDIMMhalf_0, decode_linkage_0):
 310         Change assignment of 1 to priv->comment to TRUE.
 311         (print_insn_bfin): Change legal to a bfd_boolean.  Change
 312         assignment of 0/1 with priv comment and parallel and legal
 313         to FALSE/TRUE.
 314
 315 2014-08-14  Mike Frysinger  <vapier@gentoo.org>
 316
 317         * bfin-dis.c (OUT): Define.
 318         (decode_CC2stat_0): Declare new op_names array.
 319         Replace multiple if statements with a single one.
 320
 321 2014-08-14  Mike Frysinger  <vapier@gentoo.org>
 322
 323         * bfin-dis.c (struct private): Add iw0.
 324         (_print_insn_bfin): Assign iw0 to priv.iw0.
 325         (print_insn_bfin): Drop ifetch and use priv.iw0.
 326
 327 2014-08-13  Mike Frysinger  <vapier@gentoo.org>
 328
 329         * bfin-dis.c (comment, parallel): Move from global scope ...
 330         (struct private): ... to this new struct.
 331         (decode_ProgCtrl_0, decode_CaCTRL_0, decode_PushPopReg_0,
 332         decode_PushPopMultiple_0, decode_ccMV_0, decode_CCflag_0,
 333         decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
 334         decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
 335         decode_dagMODik_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
 336         decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
 337         decode_pseudoOChar_0, decode_pseudodbg_assert_0, _print_insn_bfin,
 338         print_insn_bfin): Declare private struct.  Use priv's comment and
 339         parallel members.
 340
 341 2014-08-13  Mike Frysinger  <vapier@gentoo.org>
 342
 343         * bfin-dis.c (ifetch): Do not align pc to 2 bytes.
 344         (_print_insn_bfin): Add check for unaligned pc.
 345
 346 2014-08-13  Mike Frysinger  <vapier@gentoo.org>
 347
 348         * bfin-dis.c (ifetch): New function.
 349         (_print_insn_bfin, print_insn_bfin): Call new ifetch and return
 350         -1 when it errors.
 351
 352 2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
 353
 354         * micromips-opc.c (COD): Rename throughout to...
 355         (CM): New define, update to use INSN_COPROC_MOVE.
 356         (LCD): Rename throughout to...
 357         (LC): New define, update to use INSN_LOAD_COPROC.
 358         * mips-opc.c: Likewise.
 359
 360 2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
 361
 362         * micromips-opc.c (COD, LCD) New macros.
 363         (cfc1, ctc1): Remove FP_S attribute.
 364         (dmfc1, mfc1, mfhc1): Add LCD attribute.
 365         (dmtc1, mtc1, mthc1): Add COD attribute.
 366         * mips-opc.c (cfc1, cftc1, ctc, cttc1): Remove FP_S attribute.
 367
 368 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 369             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 370             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 371             Sergey Lega  <sergey.s.lega@intel.com>
 372             Anna Tikhonova  <anna.tikhonova@intel.com>
 373             Ilya Tocar  <ilya.tocar@intel.com>
 374             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 375             Ilya Verbin  <ilya.verbin@intel.com>
 376             Kirill Yukhin  <kirill.yukhin@intel.com>
 377             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 378
 379         * i386-dis-evex.h: Updated.
 380         * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
 381         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0F3A16,
 382         PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A50, PREFIX_EVEX_0F3A51,
 383         PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
 384         PREFIX_EVEX_0F3A67.
 385         (VEX_LEN enum): Add VEX_LEN_0F92_P_2, VEX_LEN_0F93_P_2,
 386         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_2_LEN_0.
 387         (VEX_W enum): Add EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
 388         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2, EVEX_W_0F57_P_0,
 389         EVEX_W_0F57_P_2, EVEX_W_0F78_P_2, EVEX_W_0F79_P_2, EVEX_W_0F7A_P_2,
 390         EVEX_W_0F7B_P_2, EVEX_W_0F3838_P_1, EVEX_W_0F3839_P_1,
 391         EVEX_W_0F3A16_P_2, EVEX_W_0F3A22_P_2, EVEX_W_0F3A50_P_2,
 392         EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2, EVEX_W_0F3A57_P_2,
 393         EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2.
 394         (prefix_table): Add entries for new instructions.
 395         (vex_len_table): Ditto.
 396         (vex_w_table): Ditto.
 397         (OP_E_memory): Update xmmq_mode handling.
 398         * i386-gen.c (cpu_flag_init): Add CPU_AVX512DQ_FLAGS.
 399         (cpu_flags): Add CpuAVX512DQ.
 400         * i386-init.h: Regenerared.
 401         * i386-opc.h (CpuAVX512DQ): New.
 402         (i386_cpu_flags): Add cpuavx512dq.
 403         * i386-opc.tbl: Add AVX512DQ instructions.
 404         * i386-tbl.h: Regenerate.
 405
 406 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 407             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 408             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 409             Sergey Lega  <sergey.s.lega@intel.com>
 410             Anna Tikhonova  <anna.tikhonova@intel.com>
 411             Ilya Tocar  <ilya.tocar@intel.com>
 412             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 413             Ilya Verbin  <ilya.verbin@intel.com>
 414             Kirill Yukhin  <kirill.yukhin@intel.com>
 415             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 416
 417         * i386-dis-evex.h: Add new instructions (prefixes bellow).
 418         * i386-dis.c (fetch_data): Add EdqwS, Edb, Edw, MaskBDE.
 419         (enum): Add dqw_swap_mode, db_mode, dw_mode, mask_bd_mode, REG_EVEX_0F71.
 420         (PREFIX enum): Add PREFIX_VEX_0F4A, PREFIX_VEX_0F99, PREFIX_VEX_0F3A31,
 421         PREFIX_VEX_0F3A33, PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, PREFIX_EVEX_0F63,
 422         PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
 423         PREFIX_EVEX_0F69, PREFIX_EVEX_0F6B, PREFIX_EVEX_0F71_REG_2, PREFIX_EVEX_0F71_REG_4,
 424         PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_7,
 425         PREFIX_EVEX_0F74, PREFIX_EVEX_0F75, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
 426         PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9,
 427         PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
 428         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, PREFIX_EVEX_0FE4,
 429         PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA,
 430         PREFIX_EVEX_0FEC, PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
 431         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, PREFIX_EVEX_0FF9,
 432         PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804,
 433         PREFIX_EVEX_0F380B, PREFIX_EVEX_0F3810, PREFIX_EVEX_0F381C, PREFIX_EVEX_0F381D,
 434         PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3826, PREFIX_EVEX_0F382B, PREFIX_EVEX_0F3830,
 435         PREFIX_EVEX_0F3838, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, PREFIX_EVEX_0F3866,
 436         PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, PREFIX_EVEX_0F387A,
 437         PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387D, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3A0F,
 438         PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15, PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A3E,
 439         PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42.
 440         (VEX_LEN enum): Add VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_2,
 441         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 442         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_2,
 443         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_2, VEX_LEN_0F99_P_0,
 444         VEX_LEN_0F99_P_2, VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A33_P_2, VEX_W_0F41_P_2_LEN_1,
 445         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_2_LEN_1,
 446         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 447         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F90_P_2_LEN_0,
 448         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_3_LEN_0,
 449         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0,
 450         VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0.
 451         (VEX_W enum): Add EVEX_W_0F6B_P_2, EVEX_W_0F6F_P_3, EVEX_W_0F7F_P_3,
 452         EVEX_W_0F3810_P_1, EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_2,
 453         EVEX_W_0F3820_P_1, EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2, EVEX_W_0F3828_P_1,
 454         EVEX_W_0F3829_P_1, EVEX_W_0F382B_P_2, EVEX_W_0F3830_P_1, EVEX_W_0F3866_P_2,
 455         EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F387A_P_2,
 456         EVEX_W_0F387B_P_2, EVEX_W_0F387D_P_2, EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2,
 457         EVEX_W_0F3A3F_P_2, EVEX_W_0F3A42_P_2.
 458         (prefix_table): Add entries for new instructions.
 459         (vex_table) : Ditto.
 460         (vex_len_table): Ditto.
 461         (vex_w_table): Ditto.
 462         (intel_operand_size): Add db_mode, dw_mode, dqw_swap_mode,
 463         mask_bd_mode handling.
 464         (OP_E_register): Add dqw_swap_mode, dw_mode, db_mode, mask_bd_mode
 465         handling.
 466         (OP_E_memory): Add dqw_mode, dw_mode, dqw_swap_mode, dqb_mode, db_mode
 467         handling.
 468         (OP_G): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling.
 469         (OP_EX): Add dqw_swap_mode handling.
 470         (OP_VEX): Add mask_bd_mode handling.
 471         (OP_Mask): Add mask_bd_mode handling.
 472         * i386-gen.c (cpu_flag_init): Add CPU_AVX512BW_FLAGS.
 473         (cpu_flags): Add CpuAVX512BW.
 474         * i386-init.h: Regenerated.
 475         * i386-opc.h (CpuAVX512BW): New.
 476         (i386_cpu_flags): Add cpuavx512bw.
 477         * i386-opc.tbl: Add AVX512BW instructions.
 478         * i386-tbl.h: Regenerate.
 479
 480 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 481             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 482             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 483             Sergey Lega  <sergey.s.lega@intel.com>
 484             Anna Tikhonova  <anna.tikhonova@intel.com>
 485             Ilya Tocar  <ilya.tocar@intel.com>
 486             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 487             Ilya Verbin  <ilya.verbin@intel.com>
 488             Kirill Yukhin  <kirill.yukhin@intel.com>
 489             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 490
 491         * i386-opc.tbl: Add AVX512VL and AVX512CD instructions.
 492         * i386-tbl.h: Regenerate.
 493
 494 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 495             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 496             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 497             Sergey Lega  <sergey.s.lega@intel.com>
 498             Anna Tikhonova  <anna.tikhonova@intel.com>
 499             Ilya Tocar  <ilya.tocar@intel.com>
 500             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 501             Ilya Verbin  <ilya.verbin@intel.com>
 502             Kirill Yukhin  <kirill.yukhin@intel.com>
 503             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 504
 505         * i386-dis.c (intel_operand_size): Support 128/256 length in
 506         vex_vsib_q_w_dq_mode.
 507         (OP_E_memory): Add ymmq_mode handling, handle new broadcast.
 508         * i386-gen.c (cpu_flag_init): Add CPU_AVX512VL_FLAGS.
 509         (cpu_flags): Add CpuAVX512VL.
 510         * i386-init.h: Regenerated.
 511         * i386-opc.h (CpuAVX512VL): New.
 512         (i386_cpu_flags): Add cpuavx512vl.
 513         (BROADCAST_1TO4, BROADCAST_1TO2): Define.
 514         * i386-opc.tbl: Add AVX512VL instructions.
 515         * i386-tbl.h: Regenerate.
 516
 517 2014-07-20  Stefan Kristiansson  <stefan.kristiansson@saunalahti.fi>
 518
 519         * or1k-desc.c, * or1k-desc.h, * or1k-opc.c, * or1k-opc.h,
 520         * or1k-opinst.c: Regenerate.
 521
 522 2014-07-08  Ilya Tocar  <ilya.tocar@intel.com>
 523
 524         * i386-dis-evex.h (EVEX_W_0F10_P_1_M_1): Fix vmovss.
 525         (EVEX_W_0F10_P_3_M_1): Fix vmovsd.
 526
 527 2014-07-04  Alan Modra  <amodra@gmail.com>
 528
 529         * configure.ac: Rename from configure.in.
 530         * Makefile.in: Regenerate.
 531         * config.in: Regenerate.
 532
 533 2014-07-04  Alan Modra  <amodra@gmail.com>
 534
 535         * configure.in: Include bfd/version.m4.
 536         (AC_INIT, AM_INIT_AUTOMAKE): Use modern form.
 537         (BFD_VERSION): Delete.
 538         * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Remove bfd/configure.in.
 539         * configure: Regenerate.
 540         * Makefile.in: Regenerate.
 541
 542 2014-07-01  Barney Stratford   <barney_stratford@fastmail.fm>
 543             Senthil Kumar Selvaraj  <senthil_kumar.selvaraj@atmel.com>
 544             Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 545             Soundararajan  <Sounderarajan.D@atmel.com>
 546
 547         * avr-dis.c (avr_operand): Handle constraint j for 16 bit lds/sts.
 548         (print_insn_avr): Do not select opcode if insn ISA is avrtiny and
 549         machine is not avrtiny.
 550
 551 2014-06-26  Philippe De Muyter <phdm@macqel.be>
 552
 553         * or1k-desc.h (spr_field_masks): Add U suffix to the end of long
 554         constants.
 555
 556 2014-06-12  Alan Modra  <amodra@gmail.com>
 557
 558         * or1k-asm.c, * or1k-desc.c, * or1k-desc.h, * or1k-dis.c,
 559         * or1k-ibld.c, * or1k-opc.c, * or1k-opc.h, * or1k-opinst.c: Regenerate.
 560
 561 2014-06-10  H.J. Lu  <hongjiu.lu@intel.com>
 562
 563         * i386-dis.c (fwait_prefix): New.
 564         (ckprefix): Set fwait_prefix.
 565         (print_insn): Properly print prefixes before fwait.
 566
 567 2014-06-07  Alan Modra  <amodra@gmail.com>
 568
 569         * ppc-opc.c (UISIGNOPT): Define and use with cmpli.
 570
 571 2014-06-05  Joel Brobecker  <brobecker@adacore.com>
 572
 573         * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
 574         bfd's development.sh.
 575         * Makefile.in, configure: Regenerate.
 576
 577 2014-06-03  Nick Clifton  <nickc@redhat.com>
 578
 579         * msp430-dis.c (msp430_doubleoperand): Use extension_word to
 580         decide when extended addressing is being used.
 581
 582 2014-06-02  Eric Botcazou  <ebotcazou@adacore.com>
 583
 584         * sparc-opc.c (cas): Disable for LEON.
 585         (casl): Likewise.
 586
 587 2014-05-20  Alan Modra  <amodra@gmail.com>
 588
 589         * m68k-dis.c: Don't include setjmp.h.
 590
 591 2014-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 592
 593         * i386-dis.c (ADDR16_PREFIX): Removed.
 594         (ADDR32_PREFIX): Likewise.
 595         (DATA16_PREFIX): Likewise.
 596         (DATA32_PREFIX): Likewise.
 597         (prefix_name): Updated.
 598         (print_insn): Simplify data and address size prefixes processing.
 599
 600 2014-05-08  Stefan Kristiansson  <stefan.kristiansson@saunalahti.fi>
 601
 602         * or1k-desc.c: Regenerated.
 603         * or1k-desc.h: Likewise.
 604         * or1k-opc.c: Likewise.
 605         * or1k-opc.h: Likewise.
 606         * or1k-opinst.c: Likewise.
 607
 608 2014-05-07  Andrew Bennett  <andrew.bennett@imgtec.com>
 609
 610         * mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
 611         (I34): New define.
 612         (I36): New define.
 613         (I66): New define.
 614         (I68): New define.
 615         * mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and
 616         mips64r5.
 617         (parse_mips_dis_option): Update MSA and virtualization support to
 618         allow mips64r3 and mips64r5.
 619
 620 2014-05-07  Andrew Bennett  <andrew.bennett@imgtec.com>
 621
 622         * mips-opc.c (G3): Remove I4.
 623
 624 2014-05-05  H.J. Lu  <hongjiu.lu@intel.com>
 625
 626         PR binutils/16893
 627         * i386-dis.c (twobyte_has_mandatory_prefix): New variable.
 628         (end_codep): Likewise.
 629         (mandatory_prefix): Likewise.
 630         (active_seg_prefix): Likewise.
 631         (ckprefix): Set active_seg_prefix to the active segment register
 632         prefix.
 633         (seg_prefix): Removed.
 634         (get_valid_dis386): Use the last of PREFIX_REPNZ and PREFIX_REPZ
 635         for prefix index.  Ignore the index if it is invalid and the
 636         mandatory prefix isn't required.
 637         (print_insn): Set mandatory_prefix if the PREFIX_XXX prefix is
 638         mandatory.  Don't set PREFIX_REPZ/PREFIX_REPNZ/PREFIX_LOCK bits
 639         in used_prefixes here.  Don't print unused prefixes.  Check
 640         active_seg_prefix for the active segment register prefix.
 641         Restore the DFLAG bit in sizeflag if the data size prefix is
 642         unused.  Check the unused mandatory PREFIX_XXX prefixes
 643         (append_seg): Only print the segment register which gets used.
 644         (OP_E_memory): Check active_seg_prefix for the segment register
 645         prefix.
 646         (OP_OFF): Likewise.
 647         (OP_OFF64): Likewise.
 648         (OP_DSreg): Set active_seg_prefix to PREFIX_DS if it is unset.
 649
 650 2014-05-02  H.J. Lu  <hongjiu.lu@intel.com>
 651
 652         PR binutils/16886
 653         * config.in: Regenerated.
 654         * configure: Likewise.
 655         * configure.in: Check if sigsetjmp is available.
 656         * h8500-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 657         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 658         (print_insn_h8500): Replace setjmp with OPCODES_SIGSETJMP.
 659         * i386-dis.c (dis_private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 660         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 661         (print_insn): Replace setjmp with OPCODES_SIGSETJMP.
 662         * ns32k-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 663         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 664         (print_insn_ns32k): Replace setjmp with OPCODES_SIGSETJMP.
 665         * sysdep.h (OPCODES_SIGJMP_BUF): New macro.
 666         (OPCODES_SIGSETJMP): Likewise.
 667         (OPCODES_SIGLONGJMP): Likewise.
 668         * vax-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 669         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 670         (print_insn_vax): Replace setjmp with OPCODES_SIGSETJMP.
 671         * xtensa-dis.c (dis_private): Replace jmp_buf with
 672         OPCODES_SIGJMP_BUF.
 673         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 674         (print_insn_xtensa): Replace setjmp with OPCODES_SIGSETJMP.
 675         * z8k-dis.c(instr_data_s): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 676         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 677         (print_insn_z8k): Replace setjmp with OPCODES_SIGSETJMP.
 678
 679 2014-05-01  H.J. Lu  <hongjiu.lu@intel.com>
 680
 681         PR binutils/16891
 682         * i386-dis.c (print_insn): Handle prefixes before fwait.
 683
 684 2014-04-26  Alan Modra  <amodra@gmail.com>
 685
 686         * po/POTFILES.in: Regenerate.
 687
 688 2014-04-23  Andrew Bennett  <andrew.bennett@imgtec.com>
 689
 690         * mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
 691         to allow the MIPS XPA ASE.
 692         (parse_mips_dis_option): Process the -Mxpa option.
 693         * mips-opc.c (XPA): New define.
 694         (mips_builtin_opcodes): Add MIPS XPA instructions and move the
 695         locations of the ctc0 and cfc0 instructions.
 696
 697 2014-04-22  Christian Svensson  <blue@cmd.nu>
 698
 699         * Makefile.am: Remove openrisc and or32 support.  Add support for or1k.
 700         * configure.in: Likewise.
 701         * disassemble.c: Likewise.
 702         * or1k-asm.c: New file.
 703         * or1k-desc.c: New file.
 704         * or1k-desc.h: New file.
 705         * or1k-dis.c: New file.
 706         * or1k-ibld.c: New file.
 707         * or1k-opc.c: New file.
 708         * or1k-opc.h: New file.
 709         * or1k-opinst.c: New file.
 710         * Makefile.in: Regenerate.
 711         * configure: Regenerate.
 712         * openrisc-asm.c: Delete.
 713         * openrisc-desc.c: Delete.
 714         * openrisc-desc.h: Delete.
 715         * openrisc-dis.c: Delete.
 716         * openrisc-ibld.c: Delete.
 717         * openrisc-opc.c: Delete.
 718         * openrisc-opc.h: Delete.
 719         * or32-dis.c: Delete.
 720         * or32-opc.c: Delete.
 721
 722 2014-04-04  Ilya Tocar  <ilya.tocar@intel.com>
 723
 724         * i386-dis.c (rm_table): Add encls, enclu.
 725         * i386-gen.c (cpu_flag_init): Add CPU_SE1_FLAGS,
 726         (cpu_flags): Add CpuSE1.
 727         * i386-opc.h (enum): Add CpuSE1.
 728         (i386_cpu_flags): Add cpuse1.
 729         * i386-opc.tbl: Add encls, enclu.
 730         * i386-init.h: Regenerated.
 731         * i386-tbl.h: Likewise.
 732
 733 2014-04-02  Anthony Green  <green@moxielogic.com>
 734
 735         * moxie-opc.c (moxie_form1_opc_info): Add sign-extension
 736         instructions, sex.b and sex.s.
 737
 738 2014-03-26  Jiong Wang  <jiong.wang@arm.com>
 739
 740         * aarch64-dis.c (aarch64_ext_ldst_elemlist): Check H/S undefined
 741         instructions.
 742
 743 2014-03-20  Ilya Tocar  <ilya.tocar@intel.com>
 744
 745         * i386-opc.tbl: Change memory size for vgatherpf0qps, vgatherpf1qps,
 746         vscatterpf0qps, vscatterpf1qps, vgatherqps, vpgatherqd, vpscatterqd,
 747         vscatterqps.
 748         * i386-tbl.h: Regenerate.
 749
 750 2014-03-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 751
 752         * sparc-dis.c (v9_hpriv_reg_names): Names for %hstick_offset and
 753         %hstick_enable added.
 754
 755 2014-03-19  Nick Clifton  <nickc@redhat.com>
 756
 757         * rx-decode.opc (bwl): Allow for bogus instructions with a size
 758         field of 3.
 759         (sbwl, ubwl, SCALE): Likewise.
 760         * rx-decode.c: Regenerate.
 761
 762 2014-03-12  Alan Modra  <amodra@gmail.com>
 763
 764         * Makefile.in: Regenerate.
 765
 766 2014-03-05  Alan Modra  <amodra@gmail.com>
 767
 768         Update copyright years.
 769
 770 2014-03-04  Heiher  <r@hev.cc>
 771
 772         * mips-dis.c (mips_arch_choices): Usee ISA_MIPS64R2 for Loongson-3A.
 773
 774 2014-03-04  Richard Sandiford  <rdsandiford@googlemail.com>
 775
 776         * mips-opc.c (mips_builtin_opcodes): Move the udi* instructions
 777         so that they come after the Loongson extensions.
 778
 779 2014-03-03  Alan Modra  <amodra@gmail.com>
 780
 781         * i386-gen.c (process_copyright): Emit copyright notice on one line.
 782
 783 2014-02-28  Alan Modra  <amodra@gmail.com>
 784
 785         * msp430-decode.c: Regenerate.
 786
 787 2014-02-27  Jiong Wang  <jiong.wang@arm.com>
 788
 789         * aarch64-tbl.h (aarch64_opcode_table): Replace IMM0 with
 790         FPIMM0 for fcmeq, fcmgt, fcmge, fcmlt and fcmle.
 791
 792 2014-02-27  Yufeng Zhang  <yufeng.zhang@arm.com>
 793
 794         * aarch64-opc.c (print_register_offset_address): Call
 795         get_int_reg_name to prepare the register name.
 796
 797 2014-02-25  Ilya Tocar  <ilya.tocar@intel.com>
 798
 799         * i386-opc.tbl: Remove wrong variant of vcvtps2ph
 800         * i386-tbl.h: Regenerate.
 801
 802 2014-02-20  Ilya Tocar  <ilya.tocar@intel.com>
 803
 804         * i386-gen.c (cpu_flag_init): Add CPU_PREFETCHWT1_FLAGS/
 805         (cpu_flags): Add CpuPREFETCHWT1.
 806         * i386-init.h: Regenerate.
 807         * i386-opc.h (CpuPREFETCHWT1): New.
 808         (i386_cpu_flags): Add cpuprefetchwt1.
 809         * i386-opc.tbl: Cahnge CPU of prefetchwt1 from CpuAVX512PF to CpuPREFETCHWT1.
 810         * i386-tbl.h: Regenerate.
 811
 812 2014-02-20  Ilya Tocar  <ilya.tocar@intel.com>
 813
 814         * i386-opc.tbl: Change CPU of vptestnmq, vptestnmd from CpuAVX512CD,
 815         to CpuAVX512F.
 816         * i386-tbl.h: Regenerate.
 817
 818 2014-02-19  H.J. Lu  <hongjiu.lu@intel.com>
 819
 820         * i386-gen.c (output_cpu_flags): Don't output trailing space.
 821         (output_opcode_modifier): Likewise.
 822         (output_operand_type): Likewise.
 823         * i386-init.h: Regenerated.
 824         * i386-tbl.h: Likewise.
 825
 826 2014-02-12  Ilya Tocar  <ilya.tocar@intel.com>
 827
 828         * i386-dis.c (MOD enum): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4,
 829         MOD_0FC7_REG_5.
 830         (PREFIX enum): Add PREFIX_0FAE_REG_7.
 831         (reg_table): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4 MOD_0FC7_REG_5.
 832         (prefix_table): Add clflusopt.
 833         (mod_table): Add xrstors, xsavec, xsaves.
 834         * i386-gen.c (cpu_flag_init): Add CPU_CLFLUSHOPT_FLAGS,
 835         CPU_XSAVES_FLAGS, CPU_XSAVEC_FLAGS.
 836         (cpu_flags): Add CpuClflushOpt, CpuXSAVES, CpuXSAVEC.
 837         * i386-init.h: Regenerate.
 838         * i386-opc.tbl: Add clflushopt, xrstors, xrstors64, xsaves,
 839         xsaves64, xsavec, xsavec64.
 840         * i386-tbl.h: Regenerate.
 841
 842 2014-02-10  Alan Modra  <amodra@gmail.com>
 843
 844         * po/POTFILES.in: Regenerate.
 845         * po/opcodes.pot: Regenerate.
 846
 847 2014-01-30  Michael Zolotukhin  <michael.v.zolotukhin@gmail.com>
 848             Jan Beulich  <jbeulich@suse.com>
 849
 850         PR binutils/16490
 851         * i386-dis.c (OP_E_memory): Fix shift computation for
 852         vex_vsib_q_w_dq_mode.
 853
 854 2014-01-09  Bradley Nelson  <bradnelson@google.com>
 855             Roland McGrath  <mcgrathr@google.com>
 856
 857         * i386-dis.c (print_insn): Do not touch all_prefixes[-1] when
 858         last_rex_prefix is -1.
 859
 860 2014-01-08  H.J. Lu  <hongjiu.lu@intel.com>
 861
 862         * i386-gen.c (process_copyright): Update copyright year to 2014.
 863
 864 2014-01-03  Maciej W. Rozycki  <macro@codesourcery.com>
 865
 866         * nds32-asm.c (parse_operand): Fix out-of-range integer constant.
 867
 868 For older changes see ChangeLog-2013
 869 \f
 870 Copyright (C) 2014 Free Software Foundation, Inc.
 871
 872 Copying and distribution of this file, with or without modification,
 873 are permitted in any medium without royalty provided the copyright
 874 notice and this notice are preserved.
 875
 876 Local Variables:
 877 mode: change-log
 878 left-margin: 8
 879 fill-column: 74
 880 version-control: never
 881 End: