opcodes/ChangeLog

   1 2020-05-11  Alan Modra  <amodra@gmail.com>
   2             Peter Bergner  <bergner@linux.ibm.com>
   3
   4         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
   5         New functions.
   6         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
   7         YMSK2, XA6a, XA6ap, XB6a entries.
   8         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
   9         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
  10         (PPCVSX4): Define.
  11         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
  12         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
  13         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
  14         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
  15         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
  16         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
  17         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
  18         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
  19         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
  20         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
  21         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
  22         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
  23         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
  24         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
  25
  26 2020-05-11  Alan Modra  <amodra@gmail.com>
  27
  28         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
  29         (insert_xts, extract_xts): New functions.
  30         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
  31         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
  32         (VXRC_MASK, VXSH_MASK): Define.
  33         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
  34         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
  35         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
  36         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
  37         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
  38         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
  39         xxblendvh, xxblendvw, xxblendvd, xxpermx.
  40
  41 2020-05-11  Alan Modra  <amodra@gmail.com>
  42
  43         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
  44         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
  45         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
  46         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
  47         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
  48
  49 2020-05-11  Alan Modra  <amodra@gmail.com>
  50
  51         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
  52         (XTP, DQXP, DQXP_MASK): Define.
  53         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
  54         (prefix_opcodes): Add plxvp and pstxvp.
  55
  56 2020-05-11  Alan Modra  <amodra@gmail.com>
  57
  58         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
  59         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
  60         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
  61
  62 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
  63
  64         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
  65
  66 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
  67
  68         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
  69         (L1OPT): Define.
  70         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
  71
  72 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
  73
  74         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
  75
  76 2020-05-11  Alan Modra  <amodra@gmail.com>
  77
  78         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
  79
  80 2020-05-11  Alan Modra  <amodra@gmail.com>
  81
  82         * ppc-dis.c (ppc_opts): Add "power10" entry.
  83         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
  84         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
  85
  86 2020-05-11  Nick Clifton  <nickc@redhat.com>
  87
  88         * po/fr.po: Updated French translation.
  89
  90 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
  91
  92         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
  93         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
  94         (operand_general_constraint_met_p): validate
  95         AARCH64_OPND_UNDEFINED.
  96         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
  97         for FLD_imm16_2.
  98         * aarch64-asm-2.c: Regenerated.
  99         * aarch64-dis-2.c: Regenerated.
 100         * aarch64-opc-2.c: Regenerated.
 101
 102 2020-04-29  Nick Clifton  <nickc@redhat.com>
 103
 104         PR 22699
 105         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
 106         and SETRC insns.
 107
 108 2020-04-29  Nick Clifton  <nickc@redhat.com>
 109
 110         * po/sv.po: Updated Swedish translation.
 111
 112 2020-04-29  Nick Clifton  <nickc@redhat.com>
 113
 114         PR 22699
 115         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
 116         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
 117         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
 118         IMM0_8U case.
 119
 120 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
 121
 122         PR 25848
 123         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
 124         cmpi only on m68020up and cpu32.
 125
 126 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 127
 128         * aarch64-asm.c (aarch64_ins_none): New.
 129         * aarch64-asm.h (ins_none): New declaration.
 130         * aarch64-dis.c (aarch64_ext_none): New.
 131         * aarch64-dis.h (ext_none): New declaration.
 132         * aarch64-opc.c (aarch64_print_operand): Update case for
 133         AARCH64_OPND_BARRIER_PSB.
 134         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
 135         (AARCH64_OPERANDS): Update inserter/extracter for
 136         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
 137         * aarch64-asm-2.c: Regenerated.
 138         * aarch64-dis-2.c: Regenerated.
 139         * aarch64-opc-2.c: Regenerated.
 140
 141 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 142
 143         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
 144         (aarch64_feature_ras, RAS): Likewise.
 145         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
 146         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
 147         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
 148         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
 149         * aarch64-asm-2.c: Regenerated.
 150         * aarch64-dis-2.c: Regenerated.
 151         * aarch64-opc-2.c: Regenerated.
 152
 153 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
 154
 155         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
 156         (print_insn_neon): Support disassembly of conditional
 157         instructions.
 158
 159 2020-02-16  David Faust  <david.faust@oracle.com>
 160
 161         * bpf-desc.c: Regenerate.
 162         * bpf-desc.h: Likewise.
 163         * bpf-opc.c: Regenerate.
 164         * bpf-opc.h: Likewise.
 165
 166 2020-04-07  Lili Cui  <lili.cui@intel.com>
 167
 168         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
 169         (prefix_table): New instructions (see prefixes above).
 170         (rm_table): Likewise
 171         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
 172         CPU_ANY_TSXLDTRK_FLAGS.
 173         (cpu_flags): Add CpuTSXLDTRK.
 174         * i386-opc.h (enum): Add CpuTSXLDTRK.
 175         (i386_cpu_flags): Add cputsxldtrk.
 176         * i386-opc.tbl: Add XSUSPLDTRK insns.
 177         * i386-init.h: Regenerate.
 178         * i386-tbl.h: Likewise.
 179
 180 2020-04-02  Lili Cui  <lili.cui@intel.com>
 181
 182         * i386-dis.c (prefix_table): New instructions serialize.
 183         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
 184         CPU_ANY_SERIALIZE_FLAGS.
 185         (cpu_flags): Add CpuSERIALIZE.
 186         * i386-opc.h (enum): Add CpuSERIALIZE.
 187         (i386_cpu_flags): Add cpuserialize.
 188         * i386-opc.tbl: Add SERIALIZE insns.
 189         * i386-init.h: Regenerate.
 190         * i386-tbl.h: Likewise.
 191
 192 2020-03-26  Alan Modra  <amodra@gmail.com>
 193
 194         * disassemble.h (opcodes_assert): Declare.
 195         (OPCODES_ASSERT): Define.
 196         * disassemble.c: Don't include assert.h.  Include opintl.h.
 197         (opcodes_assert): New function.
 198         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 199         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 200         calculate maxlen.  Omit insn decoding when insn length exceeds
 201         maxlen.  Exit from nibble loop when looking for E, before
 202         accessing next data byte.  Move processing of E outside loop.
 203         Replace tests of maxlen in loop with assertions.
 204
 205 2020-03-26  Alan Modra  <amodra@gmail.com>
 206
 207         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 208
 209 2020-03-25  Alan Modra  <amodra@gmail.com>
 210
 211         * z80-dis.c (suffix): Init mybuf.
 212
 213 2020-03-22  Alan Modra  <amodra@gmail.com>
 214
 215         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 216         successflly read from section.
 217
 218 2020-03-22  Alan Modra  <amodra@gmail.com>
 219
 220         * arc-dis.c (find_format): Use ISO C string concatenation rather
 221         than line continuation within a string.  Don't access needs_limm
 222         before testing opcode != NULL.
 223
 224 2020-03-22  Alan Modra  <amodra@gmail.com>
 225
 226         * ns32k-dis.c (print_insn_arg): Update comment.
 227         (print_insn_ns32k): Reduce size of index_offset array, and
 228         initialize, passing -1 to print_insn_arg for args that are not
 229         an index.  Don't exit arg loop early.  Abort on bad arg number.
 230
 231 2020-03-22  Alan Modra  <amodra@gmail.com>
 232
 233         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 234         * s12z-opc.c: Formatting.
 235         (operands_f): Return an int.
 236         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 237         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 238         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 239         (exg_sex_discrim): Likewise.
 240         (create_immediate_operand, create_bitfield_operand),
 241         (create_register_operand_with_size, create_register_all_operand),
 242         (create_register_all16_operand, create_simple_memory_operand),
 243         (create_memory_operand, create_memory_auto_operand): Don't
 244         segfault on malloc failure.
 245         (z_ext24_decode): Return an int status, negative on fail, zero
 246         on success.
 247         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 248         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 249         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 250         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 251         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 252         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 253         (loop_primitive_decode, shift_decode, psh_pul_decode),
 254         (bit_field_decode): Similarly.
 255         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 256         to return value, update callers.
 257         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 258         Don't segfault on NULL operand.
 259         (decode_operation): Return OP_INVALID on first fail.
 260         (decode_s12z): Check all reads, returning -1 on fail.
 261
 262 2020-03-20  Alan Modra  <amodra@gmail.com>
 263
 264         * metag-dis.c (print_insn_metag): Don't ignore status from
 265         read_memory_func.
 266
 267 2020-03-20  Alan Modra  <amodra@gmail.com>
 268
 269         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 270         Initialize parts of buffer not written when handling a possible
 271         2-byte insn at end of section.  Don't attempt decoding of such
 272         an insn by the 4-byte machinery.
 273
 274 2020-03-20  Alan Modra  <amodra@gmail.com>
 275
 276         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 277         partially filled buffer.  Prevent lookup of 4-byte insns when
 278         only VLE 2-byte insns are possible due to section size.  Print
 279         ".word" rather than ".long" for 2-byte leftovers.
 280
 281 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 282
 283         PR 25641
 284         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 285
 286 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 287
 288         * i386-dis.c (X86_64_0D): Rename to ...
 289         (X86_64_0E): ... this.
 290
 291 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 292
 293         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 294         * Makefile.in: Regenerated.
 295
 296 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 297
 298         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 299         3-operand pseudos.
 300         * i386-tbl.h: Re-generate.
 301
 302 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 303
 304         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 305         vprot*, vpsha*, and vpshl*.
 306         * i386-tbl.h: Re-generate.
 307
 308 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 309
 310         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 311         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 312         * i386-tbl.h: Re-generate.
 313
 314 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 315
 316         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 317         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 318         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 319         * i386-tbl.h: Re-generate.
 320
 321 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 322
 323         * i386-gen.c (struct template_arg, struct template_instance,
 324         struct template_param, struct template, templates,
 325         parse_template, expand_templates): New.
 326         (process_i386_opcodes): Various local variables moved to
 327         expand_templates. Call parse_template and expand_templates.
 328         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 329         * i386-tbl.h: Re-generate.
 330
 331 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 332
 333         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 334         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 335         register and memory source templates. Replace VexW= by VexW*
 336         where applicable.
 337         * i386-tbl.h: Re-generate.
 338
 339 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 340
 341         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 342         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 343         * i386-tbl.h: Re-generate.
 344
 345 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 346
 347         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 348         * i386-tbl.h: Re-generate.
 349
 350 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 351
 352         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 353         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 354         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 355         VexW0 on SSE2AVX variants.
 356         (vmovq): Drop NoRex64 from XMM/XMM variants.
 357         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 358         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 359         applicable use VexW0.
 360         * i386-tbl.h: Re-generate.
 361
 362 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 363
 364         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 365         * i386-opc.h (Rex64): Delete.
 366         (struct i386_opcode_modifier): Remove rex64 field.
 367         * i386-opc.tbl (crc32): Drop Rex64.
 368         Replace Rex64 with Size64 everywhere else.
 369         * i386-tbl.h: Re-generate.
 370
 371 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 372
 373         * i386-dis.c (OP_E_memory): Exclude recording of used address
 374         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 375         addressed memory operands for MPX insns.
 376
 377 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 378
 379         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 380         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 381         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 382         (ptwrite): Split into non-64-bit and 64-bit forms.
 383         * i386-tbl.h: Re-generate.
 384
 385 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 386
 387         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 388         template.
 389         * i386-tbl.h: Re-generate.
 390
 391 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 392
 393         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 394         (prefix_table): Move vmmcall here. Add vmgexit.
 395         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 396         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 397         (cpu_flags): Add CpuSEV_ES entry.
 398         * i386-opc.h (CpuSEV_ES): New.
 399         (union i386_cpu_flags): Add cpusev_es field.
 400         * i386-opc.tbl (vmgexit): New.
 401         * i386-init.h, i386-tbl.h: Re-generate.
 402
 403 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 404
 405         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 406         with MnemonicSize.
 407         * i386-opc.h (IGNORESIZE): New.
 408         (DEFAULTSIZE): Likewise.
 409         (IgnoreSize): Removed.
 410         (DefaultSize): Likewise.
 411         (MnemonicSize): New.
 412         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 413         mnemonicsize.
 414         * i386-opc.tbl (IgnoreSize): New.
 415         (DefaultSize): Likewise.
 416         * i386-tbl.h: Regenerated.
 417
 418 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 419
 420         PR 25627
 421         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 422         instructions.
 423
 424 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 425
 426         PR gas/25622
 427         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 428         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 429         * i386-tbl.h: Regenerated.
 430
 431 2020-02-26  Alan Modra  <amodra@gmail.com>
 432
 433         * aarch64-asm.c: Indent labels correctly.
 434         * aarch64-dis.c: Likewise.
 435         * aarch64-gen.c: Likewise.
 436         * aarch64-opc.c: Likewise.
 437         * alpha-dis.c: Likewise.
 438         * i386-dis.c: Likewise.
 439         * nds32-asm.c: Likewise.
 440         * nfp-dis.c: Likewise.
 441         * visium-dis.c: Likewise.
 442
 443 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 444
 445         * arc-regs.h (int_vector_base): Make it available for all ARC
 446         CPUs.
 447
 448 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 449
 450         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 451         changed.
 452
 453 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 454
 455         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 456         c.mv/c.li if rs1 is zero.
 457
 458 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 459
 460         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 461         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 462         CPU_POPCNT_FLAGS.
 463         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 464         * i386-opc.h (CpuABM): Removed.
 465         (CpuPOPCNT): New.
 466         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 467         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 468         popcnt.  Remove CpuABM from lzcnt.
 469         * i386-init.h: Regenerated.
 470         * i386-tbl.h: Likewise.
 471
 472 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 473
 474         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 475         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 476         VexW1 instead of open-coding them.
 477         * i386-tbl.h: Re-generate.
 478
 479 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 480
 481         * i386-opc.tbl (AddrPrefixOpReg): Define.
 482         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 483         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 484         templates. Drop NoRex64.
 485         * i386-tbl.h: Re-generate.
 486
 487 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 488
 489         PR gas/6518
 490         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 491         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 492         into Intel syntax instance (with Unpsecified) and AT&T one
 493         (without).
 494         (vcvtneps2bf16): Likewise, along with folding the two so far
 495         separate ones.
 496         * i386-tbl.h: Re-generate.
 497
 498 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 499
 500         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 501         CPU_ANY_SSE4A_FLAGS.
 502
 503 2020-02-17  Alan Modra  <amodra@gmail.com>
 504
 505         * i386-gen.c (cpu_flag_init): Correct last change.
 506
 507 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 508
 509         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 510         CPU_ANY_SSE4_FLAGS.
 511
 512 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 513
 514         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 515         (movzx): Likewise.
 516
 517 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 518
 519         PR gas/25438
 520         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 521         destination for Cpu64-only variant.
 522         (movzx): Fold patterns.
 523         * i386-tbl.h: Re-generate.
 524
 525 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 526
 527         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 528         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 529         CPU_ANY_SSE4_FLAGS entry.
 530         * i386-init.h: Re-generate.
 531
 532 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 533
 534         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 535         with Unspecified, making the present one AT&T syntax only.
 536         * i386-tbl.h: Re-generate.
 537
 538 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 539
 540         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 541         * i386-tbl.h: Re-generate.
 542
 543 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 544
 545         PR gas/24546
 546         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 547         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 548         Amd64 and Intel64 templates.
 549         (call, jmp): Likewise for far indirect variants. Dro
 550         Unspecified.
 551         * i386-tbl.h: Re-generate.
 552
 553 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 554
 555         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 556         * i386-opc.h (ShortForm): Delete.
 557         (struct i386_opcode_modifier): Remove shortform field.
 558         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 559         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 560         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 561         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 562         Drop ShortForm.
 563         * i386-tbl.h: Re-generate.
 564
 565 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 566
 567         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 568         fucompi): Drop ShortForm from operand-less templates.
 569         * i386-tbl.h: Re-generate.
 570
 571 2020-02-11  Alan Modra  <amodra@gmail.com>
 572
 573         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 574         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 575         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 576         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 577         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 578
 579 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 580
 581         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 582         (cde_opcodes): Add VCX* instructions.
 583
 584 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 585             Matthew Malcomson  <matthew.malcomson@arm.com>
 586
 587         * arm-dis.c (struct cdeopcode32): New.
 588         (CDE_OPCODE): New macro.
 589         (cde_opcodes): New disassembly table.
 590         (regnames): New option to table.
 591         (cde_coprocs): New global variable.
 592         (print_insn_cde): New
 593         (print_insn_thumb32): Use print_insn_cde.
 594         (parse_arm_disassembler_options): Parse coprocN args.
 595
 596 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 597
 598         PR gas/25516
 599         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 600         with ISA64.
 601         * i386-opc.h (AMD64): Removed.
 602         (Intel64): Likewose.
 603         (AMD64): New.
 604         (INTEL64): Likewise.
 605         (INTEL64ONLY): Likewise.
 606         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 607         * i386-opc.tbl (Amd64): New.
 608         (Intel64): Likewise.
 609         (Intel64Only): Likewise.
 610         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 611         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 612         * i386-tbl.h: Regenerated.
 613
 614 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 615
 616         PR 25469
 617         * z80-dis.c: Add support for GBZ80 opcodes.
 618
 619 2020-02-04  Alan Modra  <amodra@gmail.com>
 620
 621         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 622
 623 2020-02-03  Alan Modra  <amodra@gmail.com>
 624
 625         * m32c-ibld.c: Regenerate.
 626
 627 2020-02-01  Alan Modra  <amodra@gmail.com>
 628
 629         * frv-ibld.c: Regenerate.
 630
 631 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 632
 633         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 634         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 635         (OP_E_memory): Replace xmm_mdq_mode case label by
 636         vex_scalar_w_dq_mode one.
 637         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 638
 639 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 640
 641         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 642         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 643         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 644         (intel_operand_size): Drop vex_w_dq_mode case label.
 645
 646 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 647
 648         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 649         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 650
 651 2020-01-30  Alan Modra  <amodra@gmail.com>
 652
 653         * m32c-ibld.c: Regenerate.
 654
 655 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 656
 657         * bpf-opc.c: Regenerate.
 658
 659 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 660
 661         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 662         (dis386): Use them to replace C2/C3 table entries.
 663         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 664         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 665         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 666         * i386-tbl.h: Re-generate.
 667
 668 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 669
 670         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 671         forms.
 672         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 673         DefaultSize.
 674         * i386-tbl.h: Re-generate.
 675
 676 2020-01-30  Alan Modra  <amodra@gmail.com>
 677
 678         * tic4x-dis.c (tic4x_dp): Make unsigned.
 679
 680 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 681             Jan Beulich  <jbeulich@suse.com>
 682
 683         PR binutils/25445
 684         * i386-dis.c (MOVSXD_Fixup): New function.
 685         (movsxd_mode): New enum.
 686         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 687         (intel_operand_size): Handle movsxd_mode.
 688         (OP_E_register): Likewise.
 689         (OP_G): Likewise.
 690         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 691         register on movsxd.  Add movsxd with 16-bit destination register
 692         for AMD64 and Intel64 ISAs.
 693         * i386-tbl.h: Regenerated.
 694
 695 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 696
 697         PR 25403
 698         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 699         * aarch64-asm-2.c: Regenerate
 700         * aarch64-dis-2.c: Likewise.
 701         * aarch64-opc-2.c: Likewise.
 702
 703 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 704
 705         * i386-opc.tbl (sysret): Drop DefaultSize.
 706         * i386-tbl.h: Re-generate.
 707
 708 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 709
 710         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 711         Dword.
 712         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 713         * i386-tbl.h: Re-generate.
 714
 715 2020-01-20  Nick Clifton  <nickc@redhat.com>
 716
 717         * po/de.po: Updated German translation.
 718         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 719         * po/uk.po: Updated Ukranian translation.
 720
 721 2020-01-20  Alan Modra  <amodra@gmail.com>
 722
 723         * hppa-dis.c (fput_const): Remove useless cast.
 724
 725 2020-01-20  Alan Modra  <amodra@gmail.com>
 726
 727         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 728
 729 2020-01-18  Nick Clifton  <nickc@redhat.com>
 730
 731         * configure: Regenerate.
 732         * po/opcodes.pot: Regenerate.
 733
 734 2020-01-18  Nick Clifton  <nickc@redhat.com>
 735
 736         Binutils 2.34 branch created.
 737
 738 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 739
 740         * opintl.h: Fix spelling error (seperate).
 741
 742 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 743
 744         * i386-opc.tbl: Add {vex} pseudo prefix.
 745         * i386-tbl.h: Regenerated.
 746
 747 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 748
 749         PR 25376
 750         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 751         (neon_opcodes): Likewise.
 752         (select_arm_features): Make sure we enable MVE bits when selecting
 753         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 754         any architecture.
 755
 756 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 757
 758         * i386-opc.tbl: Drop stale comment from XOP section.
 759
 760 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 761
 762         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 763         (extractps): Add VexWIG to SSE2AVX forms.
 764         * i386-tbl.h: Re-generate.
 765
 766 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 767
 768         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 769         Size64 from and use VexW1 on SSE2AVX forms.
 770         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 771         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 772         * i386-tbl.h: Re-generate.
 773
 774 2020-01-15  Alan Modra  <amodra@gmail.com>
 775
 776         * tic4x-dis.c (tic4x_version): Make unsigned long.
 777         (optab, optab_special, registernames): New file scope vars.
 778         (tic4x_print_register): Set up registernames rather than
 779         malloc'd registertable.
 780         (tic4x_disassemble): Delete optable and optable_special.  Use
 781         optab and optab_special instead.  Throw away old optab,
 782         optab_special and registernames when info->mach changes.
 783
 784 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 785
 786         PR 25377
 787         * z80-dis.c (suffix): Use .db instruction to generate double
 788         prefix.
 789
 790 2020-01-14  Alan Modra  <amodra@gmail.com>
 791
 792         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 793         values to unsigned before shifting.
 794
 795 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 796
 797         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 798         flow instructions.
 799         (print_insn_thumb16, print_insn_thumb32): Likewise.
 800         (print_insn): Initialize the insn info.
 801         * i386-dis.c (print_insn): Initialize the insn info fields, and
 802         detect jumps.
 803
 804 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 805
 806         * arc-opc.c (C_NE): Make it required.
 807
 808 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 809
 810         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 811         reserved register name.
 812
 813 2020-01-13  Alan Modra  <amodra@gmail.com>
 814
 815         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 816         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 817
 818 2020-01-13  Alan Modra  <amodra@gmail.com>
 819
 820         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 821         result of wasm_read_leb128 in a uint64_t and check that bits
 822         are not lost when copying to other locals.  Use uint32_t for
 823         most locals.  Use PRId64 when printing int64_t.
 824
 825 2020-01-13  Alan Modra  <amodra@gmail.com>
 826
 827         * score-dis.c: Formatting.
 828         * score7-dis.c: Formatting.
 829
 830 2020-01-13  Alan Modra  <amodra@gmail.com>
 831
 832         * score-dis.c (print_insn_score48): Use unsigned variables for
 833         unsigned values.  Don't left shift negative values.
 834         (print_insn_score32): Likewise.
 835         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 836
 837 2020-01-13  Alan Modra  <amodra@gmail.com>
 838
 839         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 840
 841 2020-01-13  Alan Modra  <amodra@gmail.com>
 842
 843         * fr30-ibld.c: Regenerate.
 844
 845 2020-01-13  Alan Modra  <amodra@gmail.com>
 846
 847         * xgate-dis.c (print_insn): Don't left shift signed value.
 848         (ripBits): Formatting, use 1u.
 849
 850 2020-01-10  Alan Modra  <amodra@gmail.com>
 851
 852         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 853         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 854
 855 2020-01-10  Alan Modra  <amodra@gmail.com>
 856
 857         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 858         and XRREG value earlier to avoid a shift with negative exponent.
 859         * m10200-dis.c (disassemble): Similarly.
 860
 861 2020-01-09  Nick Clifton  <nickc@redhat.com>
 862
 863         PR 25224
 864         * z80-dis.c (ld_ii_ii): Use correct cast.
 865
 866 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 867
 868         PR 25224
 869         * z80-dis.c (ld_ii_ii): Use character constant when checking
 870         opcode byte value.
 871
 872 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 873
 874         * i386-dis.c (SEP_Fixup): New.
 875         (SEP): Define.
 876         (dis386_twobyte): Use it for sysenter/sysexit.
 877         (enum x86_64_isa): Change amd64 enumerator to value 1.
 878         (OP_J): Compare isa64 against intel64 instead of amd64.
 879         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 880         forms.
 881         * i386-tbl.h: Re-generate.
 882
 883 2020-01-08  Alan Modra  <amodra@gmail.com>
 884
 885         * z8k-dis.c: Include libiberty.h
 886         (instr_data_s): Make max_fetched unsigned.
 887         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 888         Don't exceed byte_info bounds.
 889         (output_instr): Make num_bytes unsigned.
 890         (unpack_instr): Likewise for nibl_count and loop.
 891         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 892         idx unsigned.
 893         * z8k-opc.h: Regenerate.
 894
 895 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 896
 897         * arc-tbl.h (llock): Use 'LLOCK' as class.
 898         (llockd): Likewise.
 899         (scond): Use 'SCOND' as class.
 900         (scondd): Likewise.
 901         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 902         (scondd): Likewise.
 903
 904 2020-01-06  Alan Modra  <amodra@gmail.com>
 905
 906         * m32c-ibld.c: Regenerate.
 907
 908 2020-01-06  Alan Modra  <amodra@gmail.com>
 909
 910         PR 25344
 911         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 912         Peek at next byte to prevent recursion on repeated prefix bytes.
 913         Ensure uninitialised "mybuf" is not accessed.
 914         (print_insn_z80): Don't zero n_fetch and n_used here,..
 915         (print_insn_z80_buf): ..do it here instead.
 916
 917 2020-01-04  Alan Modra  <amodra@gmail.com>
 918
 919         * m32r-ibld.c: Regenerate.
 920
 921 2020-01-04  Alan Modra  <amodra@gmail.com>
 922
 923         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 924
 925 2020-01-04  Alan Modra  <amodra@gmail.com>
 926
 927         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 928
 929 2020-01-04  Alan Modra  <amodra@gmail.com>
 930
 931         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 932
 933 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 934
 935         * aarch64-tbl.h (aarch64_opcode_table): Use
 936         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 937
 938 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 939
 940         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 941         forms of SUDOT and USDOT.
 942
 943 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 944
 945         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 946         uzip{1,2}.
 947         * opcodes/aarch64-dis-2.c: Re-generate.
 948
 949 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 950
 951         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 952         FMMLA encoding.
 953         * opcodes/aarch64-dis-2.c: Re-generate.
 954
 955 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 956
 957         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 958
 959 2020-01-01  Alan Modra  <amodra@gmail.com>
 960
 961         Update year range in copyright notice of all files.
 962
 963 For older changes see ChangeLog-2019
 964 \f
 965 Copyright (C) 2020 Free Software Foundation, Inc.
 966
 967 Copying and distribution of this file, with or without modification,
 968 are permitted in any medium without royalty provided the copyright
 969 notice and this notice are preserved.
 970
 971 Local Variables:
 972 mode: change-log
 973 left-margin: 8
 974 fill-column: 74
 975 version-control: never
 976 End: