opcodes/ChangeLog

   1 2020-03-06  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
   4         * i386-opc.h (Rex64): Delete.
   5         (struct i386_opcode_modifier): Remove rex64 field.
   6         * i386-opc.tbl (crc32): Drop Rex64.
   7         Replace Rex64 with Size64 everywhere else.
   8         * i386-tbl.h: Re-generate.
   9
  10 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  11
  12         * i386-dis.c (OP_E_memory): Exclude recording of used address
  13         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
  14         addressed memory operands for MPX insns.
  15
  16 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  17
  18         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
  19         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
  20         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
  21         (ptwrite): Split into non-64-bit and 64-bit forms.
  22         * i386-tbl.h: Re-generate.
  23
  24 2020-03-06  Jan Beulich  <jbeulich@suse.com>
  25
  26         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
  27         template.
  28         * i386-tbl.h: Re-generate.
  29
  30 2020-03-04  Jan Beulich  <jbeulich@suse.com>
  31
  32         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
  33         (prefix_table): Move vmmcall here. Add vmgexit.
  34         (rm_table): Replace vmmcall entry by prefix_table[] escape.
  35         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
  36         (cpu_flags): Add CpuSEV_ES entry.
  37         * i386-opc.h (CpuSEV_ES): New.
  38         (union i386_cpu_flags): Add cpusev_es field.
  39         * i386-opc.tbl (vmgexit): New.
  40         * i386-init.h, i386-tbl.h: Re-generate.
  41
  42 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
  43
  44         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
  45         with MnemonicSize.
  46         * i386-opc.h (IGNORESIZE): New.
  47         (DEFAULTSIZE): Likewise.
  48         (IgnoreSize): Removed.
  49         (DefaultSize): Likewise.
  50         (MnemonicSize): New.
  51         (i386_opcode_modifier): Replace ignoresize/defaultsize with
  52         mnemonicsize.
  53         * i386-opc.tbl (IgnoreSize): New.
  54         (DefaultSize): Likewise.
  55         * i386-tbl.h: Regenerated.
  56
  57 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
  58
  59         PR 25627
  60         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
  61         instructions.
  62
  63 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
  64
  65         PR gas/25622
  66         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
  67         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
  68         * i386-tbl.h: Regenerated.
  69
  70 2020-02-26  Alan Modra  <amodra@gmail.com>
  71
  72         * aarch64-asm.c: Indent labels correctly.
  73         * aarch64-dis.c: Likewise.
  74         * aarch64-gen.c: Likewise.
  75         * aarch64-opc.c: Likewise.
  76         * alpha-dis.c: Likewise.
  77         * i386-dis.c: Likewise.
  78         * nds32-asm.c: Likewise.
  79         * nfp-dis.c: Likewise.
  80         * visium-dis.c: Likewise.
  81
  82 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
  83
  84         * arc-regs.h (int_vector_base): Make it available for all ARC
  85         CPUs.
  86
  87 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
  88
  89         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
  90         changed.
  91
  92 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
  93
  94         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
  95         c.mv/c.li if rs1 is zero.
  96
  97 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
  98
  99         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 100         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 101         CPU_POPCNT_FLAGS.
 102         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 103         * i386-opc.h (CpuABM): Removed.
 104         (CpuPOPCNT): New.
 105         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 106         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 107         popcnt.  Remove CpuABM from lzcnt.
 108         * i386-init.h: Regenerated.
 109         * i386-tbl.h: Likewise.
 110
 111 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 112
 113         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 114         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 115         VexW1 instead of open-coding them.
 116         * i386-tbl.h: Re-generate.
 117
 118 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 119
 120         * i386-opc.tbl (AddrPrefixOpReg): Define.
 121         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 122         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 123         templates. Drop NoRex64.
 124         * i386-tbl.h: Re-generate.
 125
 126 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 127
 128         PR gas/6518
 129         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 130         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 131         into Intel syntax instance (with Unpsecified) and AT&T one
 132         (without).
 133         (vcvtneps2bf16): Likewise, along with folding the two so far
 134         separate ones.
 135         * i386-tbl.h: Re-generate.
 136
 137 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 138
 139         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 140         CPU_ANY_SSE4A_FLAGS.
 141
 142 2020-02-17  Alan Modra  <amodra@gmail.com>
 143
 144         * i386-gen.c (cpu_flag_init): Correct last change.
 145
 146 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 147
 148         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 149         CPU_ANY_SSE4_FLAGS.
 150
 151 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 152
 153         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 154         (movzx): Likewise.
 155
 156 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 157
 158         PR gas/25438
 159         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 160         destination for Cpu64-only variant.
 161         (movzx): Fold patterns.
 162         * i386-tbl.h: Re-generate.
 163
 164 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 165
 166         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 167         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 168         CPU_ANY_SSE4_FLAGS entry.
 169         * i386-init.h: Re-generate.
 170
 171 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 172
 173         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 174         with Unspecified, making the present one AT&T syntax only.
 175         * i386-tbl.h: Re-generate.
 176
 177 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 178
 179         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 180         * i386-tbl.h: Re-generate.
 181
 182 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 183
 184         PR gas/24546
 185         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 186         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 187         Amd64 and Intel64 templates.
 188         (call, jmp): Likewise for far indirect variants. Dro
 189         Unspecified.
 190         * i386-tbl.h: Re-generate.
 191
 192 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 193
 194         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 195         * i386-opc.h (ShortForm): Delete.
 196         (struct i386_opcode_modifier): Remove shortform field.
 197         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 198         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 199         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 200         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 201         Drop ShortForm.
 202         * i386-tbl.h: Re-generate.
 203
 204 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 205
 206         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 207         fucompi): Drop ShortForm from operand-less templates.
 208         * i386-tbl.h: Re-generate.
 209
 210 2020-02-11  Alan Modra  <amodra@gmail.com>
 211
 212         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 213         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 214         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 215         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 216         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 217
 218 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 219
 220         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 221         (cde_opcodes): Add VCX* instructions.
 222
 223 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 224             Matthew Malcomson  <matthew.malcomson@arm.com>
 225
 226         * arm-dis.c (struct cdeopcode32): New.
 227         (CDE_OPCODE): New macro.
 228         (cde_opcodes): New disassembly table.
 229         (regnames): New option to table.
 230         (cde_coprocs): New global variable.
 231         (print_insn_cde): New
 232         (print_insn_thumb32): Use print_insn_cde.
 233         (parse_arm_disassembler_options): Parse coprocN args.
 234
 235 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 236
 237         PR gas/25516
 238         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 239         with ISA64.
 240         * i386-opc.h (AMD64): Removed.
 241         (Intel64): Likewose.
 242         (AMD64): New.
 243         (INTEL64): Likewise.
 244         (INTEL64ONLY): Likewise.
 245         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 246         * i386-opc.tbl (Amd64): New.
 247         (Intel64): Likewise.
 248         (Intel64Only): Likewise.
 249         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 250         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 251         * i386-tbl.h: Regenerated.
 252
 253 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 254
 255         PR 25469
 256         * z80-dis.c: Add support for GBZ80 opcodes.
 257
 258 2020-02-04  Alan Modra  <amodra@gmail.com>
 259
 260         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 261
 262 2020-02-03  Alan Modra  <amodra@gmail.com>
 263
 264         * m32c-ibld.c: Regenerate.
 265
 266 2020-02-01  Alan Modra  <amodra@gmail.com>
 267
 268         * frv-ibld.c: Regenerate.
 269
 270 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 271
 272         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 273         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 274         (OP_E_memory): Replace xmm_mdq_mode case label by
 275         vex_scalar_w_dq_mode one.
 276         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 277
 278 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 279
 280         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 281         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 282         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 283         (intel_operand_size): Drop vex_w_dq_mode case label.
 284
 285 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 286
 287         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 288         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 289
 290 2020-01-30  Alan Modra  <amodra@gmail.com>
 291
 292         * m32c-ibld.c: Regenerate.
 293
 294 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 295
 296         * bpf-opc.c: Regenerate.
 297
 298 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 299
 300         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 301         (dis386): Use them to replace C2/C3 table entries.
 302         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 303         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 304         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 305         * i386-tbl.h: Re-generate.
 306
 307 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 308
 309         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 310         forms.
 311         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 312         DefaultSize.
 313         * i386-tbl.h: Re-generate.
 314
 315 2020-01-30  Alan Modra  <amodra@gmail.com>
 316
 317         * tic4x-dis.c (tic4x_dp): Make unsigned.
 318
 319 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 320             Jan Beulich  <jbeulich@suse.com>
 321
 322         PR binutils/25445
 323         * i386-dis.c (MOVSXD_Fixup): New function.
 324         (movsxd_mode): New enum.
 325         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 326         (intel_operand_size): Handle movsxd_mode.
 327         (OP_E_register): Likewise.
 328         (OP_G): Likewise.
 329         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 330         register on movsxd.  Add movsxd with 16-bit destination register
 331         for AMD64 and Intel64 ISAs.
 332         * i386-tbl.h: Regenerated.
 333
 334 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 335
 336         PR 25403
 337         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 338         * aarch64-asm-2.c: Regenerate
 339         * aarch64-dis-2.c: Likewise.
 340         * aarch64-opc-2.c: Likewise.
 341
 342 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 343
 344         * i386-opc.tbl (sysret): Drop DefaultSize.
 345         * i386-tbl.h: Re-generate.
 346
 347 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 348
 349         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 350         Dword.
 351         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 352         * i386-tbl.h: Re-generate.
 353
 354 2020-01-20  Nick Clifton  <nickc@redhat.com>
 355
 356         * po/de.po: Updated German translation.
 357         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 358         * po/uk.po: Updated Ukranian translation.
 359
 360 2020-01-20  Alan Modra  <amodra@gmail.com>
 361
 362         * hppa-dis.c (fput_const): Remove useless cast.
 363
 364 2020-01-20  Alan Modra  <amodra@gmail.com>
 365
 366         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 367
 368 2020-01-18  Nick Clifton  <nickc@redhat.com>
 369
 370         * configure: Regenerate.
 371         * po/opcodes.pot: Regenerate.
 372
 373 2020-01-18  Nick Clifton  <nickc@redhat.com>
 374
 375         Binutils 2.34 branch created.
 376
 377 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 378
 379         * opintl.h: Fix spelling error (seperate).
 380
 381 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 382
 383         * i386-opc.tbl: Add {vex} pseudo prefix.
 384         * i386-tbl.h: Regenerated.
 385
 386 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 387
 388         PR 25376
 389         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 390         (neon_opcodes): Likewise.
 391         (select_arm_features): Make sure we enable MVE bits when selecting
 392         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 393         any architecture.
 394
 395 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 396
 397         * i386-opc.tbl: Drop stale comment from XOP section.
 398
 399 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 400
 401         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 402         (extractps): Add VexWIG to SSE2AVX forms.
 403         * i386-tbl.h: Re-generate.
 404
 405 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 406
 407         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 408         Size64 from and use VexW1 on SSE2AVX forms.
 409         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 410         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 411         * i386-tbl.h: Re-generate.
 412
 413 2020-01-15  Alan Modra  <amodra@gmail.com>
 414
 415         * tic4x-dis.c (tic4x_version): Make unsigned long.
 416         (optab, optab_special, registernames): New file scope vars.
 417         (tic4x_print_register): Set up registernames rather than
 418         malloc'd registertable.
 419         (tic4x_disassemble): Delete optable and optable_special.  Use
 420         optab and optab_special instead.  Throw away old optab,
 421         optab_special and registernames when info->mach changes.
 422
 423 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 424
 425         PR 25377
 426         * z80-dis.c (suffix): Use .db instruction to generate double
 427         prefix.
 428
 429 2020-01-14  Alan Modra  <amodra@gmail.com>
 430
 431         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 432         values to unsigned before shifting.
 433
 434 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 435
 436         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 437         flow instructions.
 438         (print_insn_thumb16, print_insn_thumb32): Likewise.
 439         (print_insn): Initialize the insn info.
 440         * i386-dis.c (print_insn): Initialize the insn info fields, and
 441         detect jumps.
 442
 443 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 444
 445         * arc-opc.c (C_NE): Make it required.
 446
 447 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 448
 449         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 450         reserved register name.
 451
 452 2020-01-13  Alan Modra  <amodra@gmail.com>
 453
 454         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 455         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 456
 457 2020-01-13  Alan Modra  <amodra@gmail.com>
 458
 459         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 460         result of wasm_read_leb128 in a uint64_t and check that bits
 461         are not lost when copying to other locals.  Use uint32_t for
 462         most locals.  Use PRId64 when printing int64_t.
 463
 464 2020-01-13  Alan Modra  <amodra@gmail.com>
 465
 466         * score-dis.c: Formatting.
 467         * score7-dis.c: Formatting.
 468
 469 2020-01-13  Alan Modra  <amodra@gmail.com>
 470
 471         * score-dis.c (print_insn_score48): Use unsigned variables for
 472         unsigned values.  Don't left shift negative values.
 473         (print_insn_score32): Likewise.
 474         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 475
 476 2020-01-13  Alan Modra  <amodra@gmail.com>
 477
 478         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 479
 480 2020-01-13  Alan Modra  <amodra@gmail.com>
 481
 482         * fr30-ibld.c: Regenerate.
 483
 484 2020-01-13  Alan Modra  <amodra@gmail.com>
 485
 486         * xgate-dis.c (print_insn): Don't left shift signed value.
 487         (ripBits): Formatting, use 1u.
 488
 489 2020-01-10  Alan Modra  <amodra@gmail.com>
 490
 491         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 492         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 493
 494 2020-01-10  Alan Modra  <amodra@gmail.com>
 495
 496         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 497         and XRREG value earlier to avoid a shift with negative exponent.
 498         * m10200-dis.c (disassemble): Similarly.
 499
 500 2020-01-09  Nick Clifton  <nickc@redhat.com>
 501
 502         PR 25224
 503         * z80-dis.c (ld_ii_ii): Use correct cast.
 504
 505 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 506
 507         PR 25224
 508         * z80-dis.c (ld_ii_ii): Use character constant when checking
 509         opcode byte value.
 510
 511 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 512
 513         * i386-dis.c (SEP_Fixup): New.
 514         (SEP): Define.
 515         (dis386_twobyte): Use it for sysenter/sysexit.
 516         (enum x86_64_isa): Change amd64 enumerator to value 1.
 517         (OP_J): Compare isa64 against intel64 instead of amd64.
 518         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 519         forms.
 520         * i386-tbl.h: Re-generate.
 521
 522 2020-01-08  Alan Modra  <amodra@gmail.com>
 523
 524         * z8k-dis.c: Include libiberty.h
 525         (instr_data_s): Make max_fetched unsigned.
 526         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 527         Don't exceed byte_info bounds.
 528         (output_instr): Make num_bytes unsigned.
 529         (unpack_instr): Likewise for nibl_count and loop.
 530         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 531         idx unsigned.
 532         * z8k-opc.h: Regenerate.
 533
 534 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 535
 536         * arc-tbl.h (llock): Use 'LLOCK' as class.
 537         (llockd): Likewise.
 538         (scond): Use 'SCOND' as class.
 539         (scondd): Likewise.
 540         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 541         (scondd): Likewise.
 542
 543 2020-01-06  Alan Modra  <amodra@gmail.com>
 544
 545         * m32c-ibld.c: Regenerate.
 546
 547 2020-01-06  Alan Modra  <amodra@gmail.com>
 548
 549         PR 25344
 550         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 551         Peek at next byte to prevent recursion on repeated prefix bytes.
 552         Ensure uninitialised "mybuf" is not accessed.
 553         (print_insn_z80): Don't zero n_fetch and n_used here,..
 554         (print_insn_z80_buf): ..do it here instead.
 555
 556 2020-01-04  Alan Modra  <amodra@gmail.com>
 557
 558         * m32r-ibld.c: Regenerate.
 559
 560 2020-01-04  Alan Modra  <amodra@gmail.com>
 561
 562         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 563
 564 2020-01-04  Alan Modra  <amodra@gmail.com>
 565
 566         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 567
 568 2020-01-04  Alan Modra  <amodra@gmail.com>
 569
 570         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 571
 572 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 573
 574         * aarch64-tbl.h (aarch64_opcode_table): Use
 575         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 576
 577 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 578
 579         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 580         forms of SUDOT and USDOT.
 581
 582 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 583
 584         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 585         uzip{1,2}.
 586         * opcodes/aarch64-dis-2.c: Re-generate.
 587
 588 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 589
 590         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 591         FMMLA encoding.
 592         * opcodes/aarch64-dis-2.c: Re-generate.
 593
 594 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 595
 596         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 597
 598 2020-01-01  Alan Modra  <amodra@gmail.com>
 599
 600         Update year range in copyright notice of all files.
 601
 602 For older changes see ChangeLog-2019
 603 \f
 604 Copyright (C) 2020 Free Software Foundation, Inc.
 605
 606 Copying and distribution of this file, with or without modification,
 607 are permitted in any medium without royalty provided the copyright
 608 notice and this notice are preserved.
 609
 610 Local Variables:
 611 mode: change-log
 612 left-margin: 8
 613 fill-column: 74
 614 version-control: never
 615 End: