opcodes/ChangeLog

   1 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
   2             Alan Modra  <amodra@gmail.com>
   3
   4         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
   5         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
   6         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
   7         support disjointed BAT.
   8         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
   9         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
  10         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
  11
  12 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
  13             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
  14
  15         * i386-gen.c (adjust_broadcast_modifier): New function.
  16         (process_i386_opcode_modifier): Add an argument for operands.
  17         Adjust the Broadcast value based on operands.
  18         (output_i386_opcode): Pass operand_types to
  19         process_i386_opcode_modifier.
  20         (process_i386_opcodes): Pass NULL as operands to
  21         process_i386_opcode_modifier.
  22         * i386-opc.h (BYTE_BROADCAST): New.
  23         (WORD_BROADCAST): Likewise.
  24         (DWORD_BROADCAST): Likewise.
  25         (QWORD_BROADCAST): Likewise.
  26         (i386_opcode_modifier): Expand broadcast to 3 bits.
  27         * i386-tbl.h: Regenerated.
  28
  29 2018-07-24  Alan Modra  <amodra@gmail.com>
  30
  31         PR 23430
  32         * or1k-desc.h: Regenerate.
  33
  34 2018-07-24  Jan Beulich  <jbeulich@suse.com>
  35
  36         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
  37         vcvtusi2ss, and vcvtusi2sd.
  38         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
  39         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
  40         * i386-tbl.h: Re-generate.
  41
  42 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
  43
  44         * arc-opc.c (extract_w6): Fix extending the sign.
  45
  46 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
  47
  48         * arc-tbl.h (vewt): Allow it for ARC EM family.
  49
  50 2018-07-23  Alan Modra  <amodra@gmail.com>
  51
  52         PR 23419
  53         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
  54         opcode variants for mtspr/mfspr encodings.
  55
  56 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
  57             Maciej W. Rozycki  <macro@mips.com>
  58
  59         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
  60         loongson3a descriptors.
  61         (parse_mips_ase_option): Handle -M loongson-mmi option.
  62         (print_mips_disassembler_options): Document -M loongson-mmi.
  63         * mips-opc.c (LMMI): New macro.
  64         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
  65         instructions.
  66
  67 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  68
  69         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
  70         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
  71         IgnoreSize and [XYZ]MMword where applicable.
  72         * i386-tbl.h: Re-generate.
  73
  74 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  75
  76         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
  77         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
  78         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
  79         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
  80         * i386-tbl.h: Re-generate.
  81
  82 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  83
  84         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
  85         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
  86         VPCLMULQDQ templates into their respective AVX512VL counterparts
  87         where possible, using Disp8ShiftVL and CheckRegSize instead of
  88         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
  89         * i386-tbl.h: Re-generate.
  90
  91 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  92
  93         * i386-opc.tbl: Fold AVX512DQ templates into their respective
  94         AVX512VL counterparts where possible, using Disp8ShiftVL and
  95         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
  96         IgnoreSize) as appropriate.
  97         * i386-tbl.h: Re-generate.
  98
  99 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 100
 101         * i386-opc.tbl: Fold AVX512BW templates into their respective
 102         AVX512VL counterparts where possible, using Disp8ShiftVL and
 103         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 104         IgnoreSize) as appropriate.
 105         * i386-tbl.h: Re-generate.
 106
 107 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 108
 109         * i386-opc.tbl: Fold AVX512CD templates into their respective
 110         AVX512VL counterparts where possible, using Disp8ShiftVL and
 111         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 112         IgnoreSize) as appropriate.
 113         * i386-tbl.h: Re-generate.
 114
 115 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 116
 117         * i386-opc.h (DISP8_SHIFT_VL): New.
 118         * i386-opc.tbl (Disp8ShiftVL):  Define.
 119         (various): Fold AVX512VL templates into their respective
 120         AVX512F counterparts where possible, using Disp8ShiftVL and
 121         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
 122         IgnoreSize) as appropriate.
 123         * i386-tbl.h: Re-generate.
 124
 125 2018-07-19  Jan Beulich  <jbeulich@suse.com>
 126
 127         * Makefile.am: Change dependencies and rule for
 128         $(srcdir)/i386-init.h.
 129         * Makefile.in: Re-generate.
 130         * i386-gen.c (process_i386_opcodes): New local variable
 131         "marker". Drop opening of input file. Recognize marker and line
 132         number directives.
 133         * i386-opc.tbl (OPCODE_I386_H): Define.
 134         (i386-opc.h): Include it.
 135         (None): Undefine.
 136
 137 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
 138
 139         PR gas/23418
 140         * i386-opc.h (Byte): Update comments.
 141         (Word): Likewise.
 142         (Dword): Likewise.
 143         (Fword): Likewise.
 144         (Qword): Likewise.
 145         (Tbyte): Likewise.
 146         (Xmmword): Likewise.
 147         (Ymmword): Likewise.
 148         (Zmmword): Likewise.
 149         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
 150         vcvttps2uqq.
 151         * i386-tbl.h: Regenerated.
 152
 153 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
 154
 155         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
 156         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
 157         * aarch64-asm-2.c: Regenerate.
 158         * aarch64-dis-2.c: Regenerate.
 159         * aarch64-opc-2.c: Regenerate.
 160
 161 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
 162
 163         PR binutils/23192
 164         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
 165         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
 166         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
 167         sqdmulh, sqrdmulh): Use Em16.
 168
 169 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
 170
 171         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
 172         csdb together with them.
 173         (thumb32_opcodes): Likewise.
 174
 175 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 176
 177         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
 178         requiring 32-bit registers as operands 2 and 3. Improve
 179         comments.
 180         (mwait, mwaitx): Fold templates. Improve comments.
 181         OPERAND_TYPE_INOUTPORTREG.
 182         * i386-tbl.h: Re-generate.
 183
 184 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 185
 186         * i386-gen.c (operand_type_init): Remove
 187         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
 188         OPERAND_TYPE_INOUTPORTREG.
 189         * i386-init.h: Re-generate.
 190
 191 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 192
 193         * i386-opc.tbl (wrssd, wrussd): Add Dword.
 194         (wrssq, wrussq): Add Qword.
 195         * i386-tbl.h: Re-generate.
 196
 197 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 198
 199         * i386-opc.h: Rename OTMax to OTNum.
 200         (OTNumOfUints): Adjust calculation.
 201         (OTUnused): Directly alias to OTNum.
 202
 203 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
 204
 205         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
 206         `reg_xys'.
 207         (lea_reg_xys): Likewise.
 208         (print_insn_loop_primitive): Rename `reg' local variable to
 209         `reg_dxy'.
 210
 211 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 212
 213         PR binutils/23242
 214         * aarch64-tbl.h (ldarh): Fix disassembly mask.
 215
 216 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 217
 218         PR binutils/23369
 219         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
 220         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
 221
 222 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
 223
 224         PR tdep/8282
 225         * mips-dis.c (mips_option_arg_t): New enumeration.
 226         (mips_options): New variable.
 227         (disassembler_options_mips): New function.
 228         (print_mips_disassembler_options): Reimplement in terms of
 229         `disassembler_options_mips'.
 230         * arm-dis.c (disassembler_options_arm): Adapt to using the
 231         `disasm_options_and_args_t' structure.
 232         * ppc-dis.c (disassembler_options_powerpc): Likewise.
 233         * s390-dis.c (disassembler_options_s390): Likewise.
 234
 235 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 236
 237         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
 238         expected result.
 239         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
 240         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
 241         * testsuite/ld-arm/tls-longplt.d: Likewise.
 242
 243 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
 244
 245         PR binutils/23192
 246         * aarch64-asm-2.c: Regenerate.
 247         * aarch64-dis-2.c: Likewise.
 248         * aarch64-opc-2.c: Likewise.
 249         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
 250         * aarch64-opc.c (operand_general_constraint_met_p,
 251         aarch64_print_operand): Likewise.
 252         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
 253         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
 254         fmlal2, fmlsl2.
 255         (AARCH64_OPERANDS): Add Em2.
 256
 257 2018-06-26  Nick Clifton  <nickc@redhat.com>
 258
 259         * po/uk.po: Updated Ukranian translation.
 260         * po/de.po: Updated German translation.
 261         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 262
 263 2018-06-26  Nick Clifton  <nickc@redhat.com>
 264
 265         * nfp-dis.c: Fix spelling mistake.
 266
 267 2018-06-24  Nick Clifton  <nickc@redhat.com>
 268
 269         * configure: Regenerate.
 270         * po/opcodes.pot: Regenerate.
 271
 272 2018-06-24  Nick Clifton  <nickc@redhat.com>
 273
 274         2.31 branch created.
 275
 276 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
 277
 278         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
 279         * aarch64-asm-2.c: Regenerate.
 280         * aarch64-dis-2.c: Likewise.
 281
 282 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
 283
 284         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
 285         `-M ginv' option description.
 286
 287 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
 288
 289         PR gas/23305
 290         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
 291         la and lla.
 292
 293 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
 294
 295         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
 296         * configure.ac: Remove AC_PREREQ.
 297         * Makefile.in: Re-generate.
 298         * aclocal.m4: Re-generate.
 299         * configure: Re-generate.
 300
 301 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 302
 303         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
 304         mips64r6 descriptors.
 305         (parse_mips_ase_option): Handle -Mginv option.
 306         (print_mips_disassembler_options): Document -Mginv.
 307         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
 308         (GINV): New macro.
 309         (mips_opcodes): Define ginvi and ginvt.
 310
 311 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
 312             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 313
 314         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
 315         * mips-opc.c (CRC, CRC64): New macros.
 316         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
 317         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
 318         crc32cd for CRC64.
 319
 320 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
 321
 322         PR 20319
 323         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 324         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 325
 326 2018-06-06  Alan Modra  <amodra@gmail.com>
 327
 328         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
 329         setjmp.  Move init for some other vars later too.
 330
 331 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
 332
 333         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
 334         (dis_private): Add new fields for property section tracking.
 335         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
 336         (xtensa_instruction_fits): New functions.
 337         (fetch_data): Bump minimal fetch size to 4.
 338         (print_insn_xtensa): Make struct dis_private static.
 339         Load and prepare property table on section change.
 340         Don't disassemble literals. Don't disassemble instructions that
 341         cross property table boundaries.
 342
 343 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
 344
 345         * configure: Regenerated.
 346
 347 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 348
 349         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
 350         * i386-tbl.h: Re-generate.
 351
 352 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 353
 354         * i386-opc.tbl (sldt, str): Add NoRex64.
 355         * i386-tbl.h: Re-generate.
 356
 357 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 358
 359         * i386-opc.tbl (invpcid): Add Oword.
 360         * i386-tbl.h: Re-generate.
 361
 362 2018-06-01  Alan Modra  <amodra@gmail.com>
 363
 364         * sysdep.h (_bfd_error_handler): Don't declare.
 365         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
 366         * rl78-decode.opc: Likewise.
 367         * msp430-decode.c: Regenerate.
 368         * rl78-decode.c: Regenerate.
 369
 370 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 371
 372         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
 373         * i386-init.h : Regenerated.
 374
 375 2018-05-25  Alan Modra  <amodra@gmail.com>
 376
 377         * Makefile.in: Regenerate.
 378         * po/POTFILES.in: Regenerate.
 379
 380 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 381
 382         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 383         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 384         (insert_bab, extract_bab, insert_btab, extract_btab,
 385         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 386         (BAT, BBA VBA RBS XB6S): Delete macros.
 387         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 388         (BB, BD, RBX, XC6): Update for new macros.
 389         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 390         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 391         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 392         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 393
 394 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 395
 396         * Makefile.am: Add support for s12z architecture.
 397         * configure.ac: Likewise.
 398         * disassemble.c: Likewise.
 399         * disassemble.h: Likewise.
 400         * Makefile.in: Regenerate.
 401         * configure: Regenerate.
 402         * s12z-dis.c: New file.
 403         * s12z.h: New file.
 404
 405 2018-05-18  Alan Modra  <amodra@gmail.com>
 406
 407         * nfp-dis.c: Don't #include libbfd.h.
 408         (init_nfp3200_priv): Use bfd_get_section_contents.
 409         (nit_nfp6000_mecsr_sec): Likewise.
 410
 411 2018-05-17  Nick Clifton  <nickc@redhat.com>
 412
 413         * po/zh_CN.po: Updated simplified Chinese translation.
 414
 415 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 416
 417         PR binutils/23109
 418         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 419         * aarch64-dis-2.c: Regenerate.
 420
 421 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 422
 423         PR binutils/21446
 424         * aarch64-asm.c (opintl.h): Include.
 425         (aarch64_ins_sysreg): Enforce read/write constraints.
 426         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 427         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 428         (F_REG_READ, F_REG_WRITE): New.
 429         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 430         AARCH64_OPND_SYSREG.
 431         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 432         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 433         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 434         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 435         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 436         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 437         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 438         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 439         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 440         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 441         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 442         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 443         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 444         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 445         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 446         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 447         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 448
 449 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 450
 451         PR binutils/21446
 452         * aarch64-dis.c (no_notes: New.
 453         (parse_aarch64_dis_option): Support notes.
 454         (aarch64_decode_insn, print_operands): Likewise.
 455         (print_aarch64_disassembler_options): Document notes.
 456         * aarch64-opc.c (aarch64_print_operand): Support notes.
 457
 458 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 459
 460         PR binutils/21446
 461         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 462         and take error struct.
 463         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 464         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 465         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 466         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 467         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 468         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 469         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 470         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 471         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 472         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 473         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 474         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 475         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 476         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 477         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 478         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 479         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 480         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 481         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 482         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 483         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 484         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 485         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 486         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 487         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 488         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 489         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 490         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 491         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 492         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 493         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 494         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 495         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 496         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 497         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 498         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 499         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 500         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 501         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 502         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 503         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 504         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 505         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 506         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 507         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 508         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 509         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 510         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 511         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 512         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 513         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 514         (determine_disassembling_preference, aarch64_decode_insn,
 515         print_insn_aarch64_word, print_insn_data): Take errors struct.
 516         (print_insn_aarch64): Use errors.
 517         * aarch64-asm-2.c: Regenerate.
 518         * aarch64-dis-2.c: Regenerate.
 519         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 520         boolean in aarch64_insert_operan.
 521         (print_operand_extractor): Likewise.
 522         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 523
 524 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 525
 526         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 527
 528 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 529
 530         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 531
 532 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 533
 534         * cr16-opc.c (cr16_instruction): Comment typo fix.
 535         * hppa-dis.c (print_insn_hppa): Likewise.
 536
 537 2018-05-08  Jim Wilson  <jimw@sifive.com>
 538
 539         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 540         (match_c_slli64, match_srxi_as_c_srxi): New.
 541         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 542         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 543         <c.slli, c.srli, c.srai>: Use match_s_slli.
 544         <c.slli64, c.srli64, c.srai64>: New.
 545
 546 2018-05-08  Alan Modra  <amodra@gmail.com>
 547
 548         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 549         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 550         partition opcode space for index lookup.
 551
 552 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 553
 554         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 555         <insn_length>: ...with this.  Update usage.
 556         Remove duplicate call to *info->memory_error_func.
 557
 558 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 559             H.J. Lu  <hongjiu.lu@intel.com>
 560
 561         * i386-dis.c (Gva): New.
 562         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 563         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 564         (prefix_table): New instructions (see prefix above).
 565         (mod_table): New instructions (see prefix above).
 566         (OP_G): Handle va_mode.
 567         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 568         CPU_MOVDIR64B_FLAGS.
 569         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 570         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 571         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 572         * i386-opc.tbl: Add movidir{i,64b}.
 573         * i386-init.h: Regenerated.
 574         * i386-tbl.h: Likewise.
 575
 576 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 577
 578         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 579         AddrPrefixOpReg.
 580         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 581         (AddrPrefixOpReg): This.
 582         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 583         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 584
 585 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 586
 587         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 588         (vle_num_opcodes): Likewise.
 589         (spe2_num_opcodes): Likewise.
 590         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 591         initialization loop.
 592         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 593         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 594         only once.
 595
 596 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 597
 598         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 599
 600 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 601
 602         Makefile.am: Added nfp-dis.c.
 603         configure.ac: Added bfd_nfp_arch.
 604         disassemble.h: Added print_insn_nfp prototype.
 605         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 606         nfp-dis.c: New, for NFP support.
 607         po/POTFILES.in: Added nfp-dis.c to the list.
 608         Makefile.in: Regenerate.
 609         configure: Regenerate.
 610
 611 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 612
 613         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 614         templates into their base ones.
 615         * i386-tlb.h: Re-generate.
 616
 617 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 618
 619         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 620         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 621         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 622         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 623         * i386-init.h: Re-generate.
 624
 625 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 626
 627         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 628         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 629         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 630         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 631         comment.
 632         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 633         and CpuRegMask.
 634         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 635         CpuRegMask: Delete.
 636         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 637         cpuregzmm, and cpuregmask.
 638         * i386-init.h: Re-generate.
 639         * i386-tbl.h: Re-generate.
 640
 641 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 642
 643         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 644         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 645         * i386-init.h: Re-generate.
 646
 647 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 648
 649         * i386-gen.c (VexImmExt): Delete.
 650         * i386-opc.h (VexImmExt, veximmext): Delete.
 651         * i386-opc.tbl: Drop all VexImmExt uses.
 652         * i386-tlb.h: Re-generate.
 653
 654 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 655
 656         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 657         register-only forms.
 658         * i386-tlb.h: Re-generate.
 659
 660 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 661
 662         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 663
 664 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 665
 666         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 667         PREFIX_0F1C.
 668         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 669         (cpu_flags): Add CpuCLDEMOTE.
 670         * i386-init.h: Regenerate.
 671         * i386-opc.h (enum): Add CpuCLDEMOTE,
 672         (i386_cpu_flags): Add cpucldemote.
 673         * i386-opc.tbl: Add cldemote.
 674         * i386-tbl.h: Regenerate.
 675
 676 2018-04-16  Alan Modra  <amodra@gmail.com>
 677
 678         * Makefile.am: Remove sh5 and sh64 support.
 679         * configure.ac: Likewise.
 680         * disassemble.c: Likewise.
 681         * disassemble.h: Likewise.
 682         * sh-dis.c: Likewise.
 683         * sh64-dis.c: Delete.
 684         * sh64-opc.c: Delete.
 685         * sh64-opc.h: Delete.
 686         * Makefile.in: Regenerate.
 687         * configure: Regenerate.
 688         * po/POTFILES.in: Regenerate.
 689
 690 2018-04-16  Alan Modra  <amodra@gmail.com>
 691
 692         * Makefile.am: Remove w65 support.
 693         * configure.ac: Likewise.
 694         * disassemble.c: Likewise.
 695         * disassemble.h: Likewise.
 696         * w65-dis.c: Delete.
 697         * w65-opc.h: Delete.
 698         * Makefile.in: Regenerate.
 699         * configure: Regenerate.
 700         * po/POTFILES.in: Regenerate.
 701
 702 2018-04-16  Alan Modra  <amodra@gmail.com>
 703
 704         * configure.ac: Remove we32k support.
 705         * configure: Regenerate.
 706
 707 2018-04-16  Alan Modra  <amodra@gmail.com>
 708
 709         * Makefile.am: Remove m88k support.
 710         * configure.ac: Likewise.
 711         * disassemble.c: Likewise.
 712         * disassemble.h: Likewise.
 713         * m88k-dis.c: Delete.
 714         * Makefile.in: Regenerate.
 715         * configure: Regenerate.
 716         * po/POTFILES.in: Regenerate.
 717
 718 2018-04-16  Alan Modra  <amodra@gmail.com>
 719
 720         * Makefile.am: Remove i370 support.
 721         * configure.ac: Likewise.
 722         * disassemble.c: Likewise.
 723         * disassemble.h: Likewise.
 724         * i370-dis.c: Delete.
 725         * i370-opc.c: Delete.
 726         * Makefile.in: Regenerate.
 727         * configure: Regenerate.
 728         * po/POTFILES.in: Regenerate.
 729
 730 2018-04-16  Alan Modra  <amodra@gmail.com>
 731
 732         * Makefile.am: Remove h8500 support.
 733         * configure.ac: Likewise.
 734         * disassemble.c: Likewise.
 735         * disassemble.h: Likewise.
 736         * h8500-dis.c: Delete.
 737         * h8500-opc.h: Delete.
 738         * Makefile.in: Regenerate.
 739         * configure: Regenerate.
 740         * po/POTFILES.in: Regenerate.
 741
 742 2018-04-16  Alan Modra  <amodra@gmail.com>
 743
 744         * configure.ac: Remove tahoe support.
 745         * configure: Regenerate.
 746
 747 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 748
 749         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
 750         umwait.
 751         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
 752         64-bit mode.
 753         * i386-tbl.h: Regenerated.
 754
 755 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 756
 757         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
 758         PREFIX_MOD_1_0FAE_REG_6.
 759         (va_mode): New.
 760         (OP_E_register): Use va_mode.
 761         * i386-dis-evex.h (prefix_table):
 762         New instructions (see prefixes above).
 763         * i386-gen.c (cpu_flag_init): Add WAITPKG.
 764         (cpu_flags): Likewise.
 765         * i386-opc.h (enum): Likewise.
 766         (i386_cpu_flags): Likewise.
 767         * i386-opc.tbl: Add umonitor, umwait, tpause.
 768         * i386-init.h: Regenerate.
 769         * i386-tbl.h: Likewise.
 770
 771 2018-04-11  Alan Modra  <amodra@gmail.com>
 772
 773         * opcodes/i860-dis.c: Delete.
 774         * opcodes/i960-dis.c: Delete.
 775         * Makefile.am: Remove i860 and i960 support.
 776         * configure.ac: Likewise.
 777         * disassemble.c: Likewise.
 778         * disassemble.h: Likewise.
 779         * Makefile.in: Regenerate.
 780         * configure: Regenerate.
 781         * po/POTFILES.in: Regenerate.
 782
 783 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
 784
 785         PR binutils/23025
 786         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
 787         to 0.
 788         (print_insn): Clear vex instead of vex.evex.
 789
 790 2018-04-04  Nick Clifton  <nickc@redhat.com>
 791
 792         * po/es.po: Updated Spanish translation.
 793
 794 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 795
 796         * i386-gen.c (opcode_modifiers): Delete VecESize.
 797         * i386-opc.h (VecESize): Delete.
 798         (struct i386_opcode_modifier): Delete vecesize.
 799         * i386-opc.tbl: Drop VecESize.
 800         * i386-tlb.h: Re-generate.
 801
 802 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 803
 804         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
 805         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
 806         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
 807         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
 808         * i386-tlb.h: Re-generate.
 809
 810 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 811
 812         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
 813         Fold AVX512 forms
 814         * i386-tlb.h: Re-generate.
 815
 816 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 817
 818         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
 819         (vex_len_table): Drop Y for vcvt*2si.
 820         (putop): Replace plain 'Y' handling by abort().
 821
 822 2018-03-28  Nick Clifton  <nickc@redhat.com>
 823
 824         PR 22988
 825         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
 826         instructions with only a base address register.
 827         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
 828         handle AARHC64_OPND_SVE_ADDR_R.
 829         (aarch64_print_operand): Likewise.
 830         * aarch64-asm-2.c: Regenerate.
 831         * aarch64_dis-2.c: Regenerate.
 832         * aarch64-opc-2.c: Regenerate.
 833
 834 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 835
 836         * i386-opc.tbl: Drop VecESize from register only insn forms and
 837         memory forms not allowing broadcast.
 838         * i386-tlb.h: Re-generate.
 839
 840 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 841
 842         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
 843         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
 844         sha256*): Drop Disp<N>.
 845
 846 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 847
 848         * i386-dis.c (EbndS, bnd_swap_mode): New.
 849         (prefix_table): Use EbndS.
 850         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
 851         * i386-opc.tbl (bndmov): Move misplaced Load.
 852         * i386-tlb.h: Re-generate.
 853
 854 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 855
 856         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
 857         templates allowing memory operands and folded ones for register
 858         only flavors.
 859         * i386-tlb.h: Re-generate.
 860
 861 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 862
 863         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
 864         256-bit templates. Drop redundant leftover Disp<N>.
 865         * i386-tlb.h: Re-generate.
 866
 867 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
 868
 869         * riscv-opc.c (riscv_insn_types): New.
 870
 871 2018-03-13  Nick Clifton  <nickc@redhat.com>
 872
 873         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 874
 875 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 876
 877         * i386-opc.tbl: Add Optimize to clr.
 878         * i386-tbl.h: Regenerated.
 879
 880 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 881
 882         * i386-gen.c (opcode_modifiers): Remove OldGcc.
 883         * i386-opc.h (OldGcc): Removed.
 884         (i386_opcode_modifier): Remove oldgcc.
 885         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
 886         instructions for old (<= 2.8.1) versions of gcc.
 887         * i386-tbl.h: Regenerated.
 888
 889 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 890
 891         * i386-opc.h (EVEXDYN): New.
 892         * i386-opc.tbl: Fold various AVX512VL templates.
 893         * i386-tlb.h: Re-generate.
 894
 895 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 896
 897         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 898         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 899         vpexpandd, vpexpandq): Fold AFX512VF templates.
 900         * i386-tlb.h: Re-generate.
 901
 902 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 903
 904         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
 905         Fold 128- and 256-bit VEX-encoded templates.
 906         * i386-tlb.h: Re-generate.
 907
 908 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 909
 910         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 911         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 912         vpexpandd, vpexpandq): Fold AVX512F templates.
 913         * i386-tlb.h: Re-generate.
 914
 915 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 916
 917         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
 918         64-bit templates. Drop Disp<N>.
 919         * i386-tlb.h: Re-generate.
 920
 921 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 922
 923         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
 924         and 256-bit templates.
 925         * i386-tlb.h: Re-generate.
 926
 927 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 928
 929         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
 930         * i386-tlb.h: Re-generate.
 931
 932 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 933
 934         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
 935         Drop NoAVX.
 936         * i386-tlb.h: Re-generate.
 937
 938 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 939
 940         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
 941         * i386-tlb.h: Re-generate.
 942
 943 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 944
 945         * i386-gen.c (opcode_modifiers): Delete FloatD.
 946         * i386-opc.h (FloatD): Delete.
 947         (struct i386_opcode_modifier): Delete floatd.
 948         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
 949         FloatD by D.
 950         * i386-tlb.h: Re-generate.
 951
 952 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 953
 954         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
 955
 956 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 957
 958         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
 959         * i386-tlb.h: Re-generate.
 960
 961 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 962
 963         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
 964         forms.
 965         * i386-tlb.h: Re-generate.
 966
 967 2018-03-07  Alan Modra  <amodra@gmail.com>
 968
 969         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
 970         bfd_arch_rs6000.
 971         * disassemble.h (print_insn_rs6000): Delete.
 972         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
 973         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
 974         (print_insn_rs6000): Delete.
 975
 976 2018-03-03  Alan Modra  <amodra@gmail.com>
 977
 978         * sysdep.h (opcodes_error_handler): Define.
 979         (_bfd_error_handler): Declare.
 980         * Makefile.am: Remove stray #.
 981         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
 982         EDIT" comment.
 983         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
 984         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
 985         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
 986         opcodes_error_handler to print errors.  Standardize error messages.
 987         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
 988         and include opintl.h.
 989         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
 990         * i386-gen.c: Standardize error messages.
 991         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
 992         * Makefile.in: Regenerate.
 993         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
 994         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
 995         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
 996         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
 997         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
 998         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
 999         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1000         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1001         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1002         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1003         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1004         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1005         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1006
1007 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1008
1009         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1010         vpsub[bwdq] instructions.
1011         * i386-tbl.h: Regenerated.
1012
1013 2018-03-01  Alan Modra  <amodra@gmail.com>
1014
1015         * configure.ac (ALL_LINGUAS): Sort.
1016         * configure: Regenerate.
1017
1018 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1019
1020         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1021         macro by assignements.
1022
1023 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
1024
1025         PR gas/22871
1026         * i386-gen.c (opcode_modifiers): Add Optimize.
1027         * i386-opc.h (Optimize): New enum.
1028         (i386_opcode_modifier): Add optimize.
1029         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1030         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1031         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1032         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1033         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1034         vpxord and vpxorq.
1035         * i386-tbl.h: Regenerated.
1036
1037 2018-02-26  Alan Modra  <amodra@gmail.com>
1038
1039         * crx-dis.c (getregliststring): Allocate a large enough buffer
1040         to silence false positive gcc8 warning.
1041
1042 2018-02-22  Shea Levy <shea@shealevy.com>
1043
1044         * disassemble.c (ARCH_riscv): Define if ARCH_all.
1045
1046 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
1047
1048         * i386-opc.tbl: Add {rex},
1049         * i386-tbl.h: Regenerated.
1050
1051 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
1052
1053         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1054         (mips16_opcodes): Replace `M' with `m' for "restore".
1055
1056 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1057
1058         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1059
1060 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
1061
1062         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1063         variable to `function_index'.
1064
1065 2018-02-13  Nick Clifton  <nickc@redhat.com>
1066
1067         PR 22823
1068         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1069         about truncation of printing.
1070
1071 2018-02-12  Henry Wong <henry@stuffedcow.net>
1072
1073         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1074
1075 2018-02-05  Nick Clifton  <nickc@redhat.com>
1076
1077         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1078
1079 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1080
1081         * i386-dis.c (enum): Add pconfig.
1082         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1083         (cpu_flags): Add CpuPCONFIG.
1084         * i386-opc.h (enum): Add CpuPCONFIG.
1085         (i386_cpu_flags): Add cpupconfig.
1086         * i386-opc.tbl: Add PCONFIG instruction.
1087         * i386-init.h: Regenerate.
1088         * i386-tbl.h: Likewise.
1089
1090 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1091
1092         * i386-dis.c (enum): Add PREFIX_0F09.
1093         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1094         (cpu_flags): Add CpuWBNOINVD.
1095         * i386-opc.h (enum): Add CpuWBNOINVD.
1096         (i386_cpu_flags): Add cpuwbnoinvd.
1097         * i386-opc.tbl: Add WBNOINVD instruction.
1098         * i386-init.h: Regenerate.
1099         * i386-tbl.h: Likewise.
1100
1101 2018-01-17  Jim Wilson  <jimw@sifive.com>
1102
1103         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1104
1105 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1106
1107         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1108         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1109         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1110         (cpu_flags): Add CpuIBT, CpuSHSTK.
1111         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1112         (i386_cpu_flags): Add cpuibt, cpushstk.
1113         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1114         * i386-init.h: Regenerate.
1115         * i386-tbl.h: Likewise.
1116
1117 2018-01-16  Nick Clifton  <nickc@redhat.com>
1118
1119         * po/pt_BR.po: Updated Brazilian Portugese translation.
1120         * po/de.po: Updated German translation.
1121
1122 2018-01-15  Jim Wilson  <jimw@sifive.com>
1123
1124         * riscv-opc.c (match_c_nop): New.
1125         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1126
1127 2018-01-15  Nick Clifton  <nickc@redhat.com>
1128
1129         * po/uk.po: Updated Ukranian translation.
1130
1131 2018-01-13  Nick Clifton  <nickc@redhat.com>
1132
1133         * po/opcodes.pot: Regenerated.
1134
1135 2018-01-13  Nick Clifton  <nickc@redhat.com>
1136
1137         * configure: Regenerate.
1138
1139 2018-01-13  Nick Clifton  <nickc@redhat.com>
1140
1141         2.30 branch created.
1142
1143 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1144
1145         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1146         * i386-tbl.h: Regenerate.
1147
1148 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1149
1150         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1151         * i386-tbl.h: Re-generate.
1152
1153 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1154
1155         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1156         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1157         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1158         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1159         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1160         Disp8MemShift of AVX512VL forms.
1161         * i386-tbl.h: Re-generate.
1162
1163 2018-01-09  Jim Wilson  <jimw@sifive.com>
1164
1165         * riscv-dis.c (maybe_print_address): If base_reg is zero,
1166         then the hi_addr value is zero.
1167
1168 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1169
1170         * arm-dis.c (arm_opcodes): Add csdb.
1171         (thumb32_opcodes): Add csdb.
1172
1173 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1174
1175         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1176         * aarch64-asm-2.c: Regenerate.
1177         * aarch64-dis-2.c: Regenerate.
1178         * aarch64-opc-2.c: Regenerate.
1179
1180 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
1181
1182         PR gas/22681
1183         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1184         Remove AVX512 vmovd with 64-bit operands.
1185         * i386-tbl.h: Regenerated.
1186
1187 2018-01-05  Jim Wilson  <jimw@sifive.com>
1188
1189         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1190         jalr.
1191
1192 2018-01-03  Alan Modra  <amodra@gmail.com>
1193
1194         Update year range in copyright notice of all files.
1195
1196 2018-01-02  Jan Beulich  <jbeulich@suse.com>
1197
1198         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1199         and OPERAND_TYPE_REGZMM entries.
1200
1201 For older changes see ChangeLog-2017
1202 \f
1203 Copyright (C) 2018 Free Software Foundation, Inc.
1204
1205 Copying and distribution of this file, with or without modification,
1206 are permitted in any medium without royalty provided the copyright
1207 notice and this notice are preserved.
1208
1209 Local Variables:
1210 mode: change-log
1211 left-margin: 8
1212 fill-column: 74
1213 version-control: never
1214 End: