opcodes/ChangeLog

   1 2015-08-21  Alexander Fomin  <alexander.fomin@intel.com>
   2
   3         PR binutils/18257
   4         * i386-dis.c: Use MOD_TABLE for most of mask instructions.
   5         (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
   6         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
   7         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
   8         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
   9         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
  10         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
  11         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
  12         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
  13         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
  14         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
  15         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
  16         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
  17         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
  18         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
  19         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
  20         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
  21         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
  22         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
  23         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
  24         MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
  25         MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
  26         MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
  27         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
  28         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
  29         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
  30         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
  31         MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
  32         MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
  33         MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
  34         MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
  35         (vex_w_table): Replace terminals with MOD_TABLE entries for
  36         most of mask instructions.
  37
  38 2015-08-17  Alan Modra  <amodra@gmail.com>
  39
  40         * cgen.sh: Trim trailing space from cgen output.
  41         * ia64-gen.c (print_dependency_table): Don't generate trailing space.
  42         (print_dis_table): Likewise.
  43         * opc2c.c (dump_lines): Likewise.
  44         (orig_filename): Warning fix.
  45         * ia64-asmtab.c: Regenerate.
  46
  47 2015-08-13  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  48
  49         * arm-dis.c (print_insn_arm): Disassembling for all targets V6
  50         and higher with ARM instruction set will now mark the 26-bit
  51         versions of teq,tst,cmn and cmp as UNPREDICTABLE.
  52         (arm_opcodes): Fix for unpredictable nop being recognized as a
  53         teq.
  54
  55 2015-08-12  Simon Dardis  <simon.dardis@imgtec.com>
  56
  57         * micromips-opc.c (micromips_opcodes): Re-order table so that move
  58         based on 'or' is first.
  59         * mips-opc.c (mips_builtin_opcodes): Ditto.
  60
  61 2015-08-11  Nick Clifton  <nickc@redhat.com>
  62
  63         PR 18800
  64         * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
  65         instruction.
  66
  67 2015-08-10  Robert Suchanek  <robert.suchanek@imgtec.com>
  68
  69         * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
  70
  71 2015-08-07  Amit Pawar <Amit.Pawar@amd.com>
  72
  73         * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
  74         * i386-init.h: Regenerated.
  75
  76 2015-07-30  H.J. Lu  <hongjiu.lu@intel.com>
  77
  78         PR binutils/13571
  79         * i386-dis.c (MOD_0FC3): New.
  80         (PREFIX_0FC3): Renamed to ...
  81         (PREFIX_MOD_0_0FC3): This.
  82         (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
  83         (prefix_table): Replace Ma with Ev on movntiS.
  84         (mod_table): Add MOD_0FC3.
  85
  86 2015-07-27  H.J. Lu  <hongjiu.lu@intel.com>
  87
  88         * configure: Regenerated.
  89
  90 2015-07-23  Alan Modra  <amodra@gmail.com>
  91
  92         PR 18708
  93         * i386-dis.c (get64): Avoid signed integer overflow.
  94
  95 2015-07-22  Alexander Fomin  <alexander.fomin@intel.com>
  96
  97         PR binutils/18631
  98         * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
  99         "EXEvexHalfBcstXmmq" for the second operand.
 100         (EVEX_W_0F79_P_2): Likewise.
 101         (EVEX_W_0F7A_P_2): Likewise.
 102         (EVEX_W_0F7B_P_2): Likewise.
 103
 104 2015-07-16  Alessandro Marzocchi  <alessandro.marzocchi@gmail.com>
 105
 106         * arm-dis.c (print_insn_coprocessor): Added support for quarter
 107         float bitfield format.
 108         (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
 109         quarter float bitfield format.
 110
 111 2015-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 112
 113         * configure: Regenerated.
 114
 115 2015-07-03  Alan Modra  <amodra@gmail.com>
 116
 117         * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
 118         * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries.  Add
 119         PPC_OPCODE_7450 to 7450 entry.  Add PPC_OPCODE_750 to 750cl entry.
 120
 121 2015-07-01  Sandra Loosemore  <sandra@codesourcery.com>
 122             Cesar Philippidis  <cesar@codesourcery.com>
 123
 124         * nios2-dis.c (nios2_extract_opcode): New.
 125         (nios2_disassembler_state): New.
 126         (nios2_find_opcode_hash): Use mach parameter to select correct
 127         disassembler state.
 128         (nios2_print_insn_arg): Extend to support new R2 argument letters
 129         and formats.
 130         (print_insn_nios2): Check for 16-bit instruction at end of memory.
 131         * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
 132         (NIOS2_NUM_OPCODES): Rename to...
 133         (NIOS2_NUM_R1_OPCODES): This.
 134         (nios2_r2_opcodes): New.
 135         (NIOS2_NUM_R2_OPCODES): New.
 136         (nios2_num_r2_opcodes): New.
 137         (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
 138         (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
 139         (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
 140         (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
 141         (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
 142
 143 2015-06-30  Amit Pawar  <Amit.Pawar@amd.com>
 144
 145         * i386-dis.c (OP_Mwaitx): New.
 146         (rm_table): Add monitorx/mwaitx.
 147         * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
 148         and CPU_ZNVER1_FLAGS.  Add CPU_MWAITX_FLAGS.
 149         (operand_type_init): Add CpuMWAITX.
 150         * i386-opc.h (CpuMWAITX): New.
 151         (i386_cpu_flags): Add cpumwaitx.
 152         * i386-opc.tbl: Add monitorx and mwaitx.
 153         * i386-init.h: Regenerated.
 154         * i386-tbl.h: Likewise.
 155
 156 2015-06-22  Peter Bergner  <bergner@vnet.ibm.com>
 157
 158         * ppc-opc.c (insert_ls): Test for invalid LS operands.
 159         (insert_esync): New function.
 160         (LS, WC): Use insert_ls.
 161         (ESYNC): Use insert_esync.
 162
 163 2015-06-22  Nick Clifton  <nickc@redhat.com>
 164
 165         * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
 166         requested region lies beyond it.
 167         * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
 168         looking for 32-bit insns.
 169         * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
 170         data.
 171         * sh-dis.c (print_insn_sh): Likewise.
 172         * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
 173         blocks of instructions.
 174         * vax-dis.c (print_insn_vax): Check that the requested address
 175         does not clash with the stop_vma.
 176
 177 2015-06-19  Peter Bergner  <bergner@vnet.ibm.com>
 178
 179         * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
 180         * ppc-opc.c (FXM4): Add non-zero optional value.
 181         (TBR): Likewise.
 182         (SXL): Likewise.
 183         (insert_fxm): Handle new default operand value.
 184         (extract_fxm): Likewise.
 185         (insert_tbr): Likewise.
 186         (extract_tbr): Likewise.
 187
 188 2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
 189
 190         * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
 191
 192 2015-06-16  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 193
 194         * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
 195
 196 2015-06-12  Peter Bergner  <bergner@vnet.ibm.com>
 197
 198         * ppc-opc.c: Add comment accidentally removed by old commit.
 199         (MTMSRD_L): Delete.
 200
 201 2015-06-04  Peter Bergner  <bergner@vnet.ibm.com>
 202
 203         * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
 204
 205 2015-06-04  Nick Clifton  <nickc@redhat.com>
 206
 207         PR 18474
 208         * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
 209
 210 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 211
 212         * arm-dis.c (arm_opcodes): Add "setpan".
 213         (thumb_opcodes): Add "setpan".
 214
 215 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 216
 217         * arm-dis.c (select_arm_features): Rework to avoid used of redefined
 218         macros.
 219
 220 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 221
 222         * aarch64-tbl.h (aarch64_feature_rdma): New.
 223         (RDMA): New.
 224         (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
 225         * aarch64-asm-2.c: Regenerate.
 226         * aarch64-dis-2.c: Regenerate.
 227         * aarch64-opc-2.c: Regenerate.
 228
 229 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 230
 231         * aarch64-tbl.h (aarch64_feature_lor): New.
 232         (LOR): New.
 233         (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
 234         "stllrb", "stllrh".
 235         * aarch64-asm-2.c: Regenerate.
 236         * aarch64-dis-2.c: Regenerate.
 237         * aarch64-opc-2.c: Regenerate.
 238
 239 2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
 240
 241         * aarch64-opc.c (F_ARCHEXT): New.
 242         (aarch64_sys_regs): Add "pan".
 243         (aarch64_sys_reg_supported_p): New.
 244         (aarch64_pstatefields): Add "pan".
 245         (aarch64_pstatefield_supported_p): New.
 246
 247 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 248
 249         * i386-tbl.h: Regenerate.
 250
 251 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 252
 253         * i386-dis.c (print_insn): Swap rounding mode specifier and
 254         general purpose register in Intel mode.
 255
 256 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 257
 258         * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
 259         * i386-tbl.h: Regenerate.
 260
 261 2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>
 262
 263         * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
 264         * i386-init.h: Regenerated.
 265
 266 2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>
 267
 268         PR binutis/18386
 269         * i386-dis.c: Add comments for '@'.
 270         (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
 271         (enum x86_64_isa): New.
 272         (isa64): Likewise.
 273         (print_i386_disassembler_options): Add amd64 and intel64.
 274         (print_insn): Handle amd64 and intel64.
 275         (putop): Handle '@'.
 276         (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
 277         * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
 278         * i386-opc.h (AMD64): New.
 279         (CpuIntel64): Likewise.
 280         (i386_cpu_flags): Add cpuamd64 and cpuintel64.
 281         * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
 282         Mark direct call/jmp without Disp16|Disp32 as Intel64.
 283         * i386-init.h: Regenerated.
 284         * i386-tbl.h: Likewise.
 285
 286 2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>
 287
 288         * ppc-opc.c (IH) New define.
 289         (powerpc_opcodes) <wait>: Do not enable for POWER7.
 290         <tlbie>: Add RS operand for POWER7.
 291         <slbia>: Add IH operand for POWER6.
 292
 293 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 294
 295         * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
 296         direct branch.
 297         (jmp): Likewise.
 298         * i386-tbl.h: Regenerated.
 299
 300 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 301
 302         * configure.ac: Support bfd_iamcu_arch.
 303         * disassemble.c (disassembler): Support bfd_iamcu_arch.
 304         * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
 305         CPU_IAMCU_COMPAT_FLAGS.
 306         (cpu_flags): Add CpuIAMCU.
 307         * i386-opc.h (CpuIAMCU): New.
 308         (i386_cpu_flags): Add cpuiamcu.
 309         * configure: Regenerated.
 310         * i386-init.h: Likewise.
 311         * i386-tbl.h: Likewise.
 312
 313 2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>
 314
 315         PR binutis/18386
 316         * i386-dis.c (X86_64_E8): New.
 317         (X86_64_E9): Likewise.
 318         Update comments on 'T', 'U', 'V'.  Add comments for '^'.
 319         (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
 320         (x86_64_table): Add X86_64_E8 and X86_64_E9.
 321         (mod_table): Replace {T|} with ^ on Jcall/Jmp.
 322         (putop): Handle '^'.
 323         (OP_J): Ignore the operand size prefix in 64-bit.  Don't check
 324         REX_W.
 325
 326 2015-04-30  DJ Delorie  <dj@redhat.com>
 327
 328         * disassemble.c (disassembler): Choose suitable disassembler based
 329         on E_ABI.
 330         * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
 331         it to decode mul/div insns.
 332         * rl78-decode.c: Regenerate.
 333         * rl78-dis.c (print_insn_rl78): Rename to...
 334         (print_insn_rl78_common): ...this, take ISA parameter.
 335         (print_insn_rl78): New.
 336         (print_insn_rl78_g10): New.
 337         (print_insn_rl78_g13): New.
 338         (print_insn_rl78_g14): New.
 339         (rl78_get_disassembler): New.
 340
 341 2015-04-29  Nick Clifton  <nickc@redhat.com>
 342
 343         * po/fr.po: Updated French translation.
 344
 345 2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>
 346
 347         * ppc-opc.c (DCBT_EO): New define.
 348         (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
 349         <lharx>: Likewise.
 350         <stbcx.>: Likewise.
 351         <sthcx.>: Likewise.
 352         <waitrsv>: Do not enable for POWER7 and later.
 353         <waitimpl>: Likewise.
 354         <dcbt>: Default to the two operand form of the instruction for all
 355         "old" cpus.  For "new" cpus, use the operand ordering that matches
 356         whether the cpu is server or embedded.
 357         <dcbtst>: Likewise.
 358
 359 2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 360
 361         * s390-opc.c: New instruction type VV0UU2.
 362         * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
 363         and WFC.
 364
 365 2015-04-23  Jan Beulich  <jbeulich@suse.com>
 366
 367         * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
 368         * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
 369         vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
 370         (vfpclasspd, vfpclassps): Add %XZ.
 371
 372 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 373
 374         * i386-dis.c (PREFIX_UD_SHIFT): Removed.
 375         (PREFIX_UD_REPZ): Likewise.
 376         (PREFIX_UD_REPNZ): Likewise.
 377         (PREFIX_UD_DATA): Likewise.
 378         (PREFIX_UD_ADDR): Likewise.
 379         (PREFIX_UD_LOCK): Likewise.
 380
 381 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 382
 383         * i386-dis.c (prefix_requirement): Removed.
 384         (print_insn): Don't set prefix_requirement.  Check
 385         dp->prefix_requirement instead of prefix_requirement.
 386
 387 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 388
 389         PR binutils/17898
 390         * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
 391         (PREFIX_MOD_0_0FC7_REG_6): This.
 392         (PREFIX_MOD_3_0FC7_REG_6): New.
 393         (PREFIX_MOD_3_0FC7_REG_7): Likewise.
 394         (prefix_table): Replace PREFIX_0FC7_REG_6 with
 395         PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
 396         PREFIX_MOD_3_0FC7_REG_7.
 397         (mod_table): Replace PREFIX_0FC7_REG_6 with
 398         PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
 399         PREFIX_MOD_3_0FC7_REG_7.
 400
 401 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 402
 403         * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
 404         (PREFIX_MANDATORY_REPNZ): Likewise.
 405         (PREFIX_MANDATORY_DATA): Likewise.
 406         (PREFIX_MANDATORY_ADDR): Likewise.
 407         (PREFIX_MANDATORY_LOCK): Likewise.
 408         (PREFIX_MANDATORY): Likewise.
 409         (PREFIX_UD_SHIFT): Set to 8
 410         (PREFIX_UD_REPZ): Updated.
 411         (PREFIX_UD_REPNZ): Likewise.
 412         (PREFIX_UD_DATA): Likewise.
 413         (PREFIX_UD_ADDR): Likewise.
 414         (PREFIX_UD_LOCK): Likewise.
 415         (PREFIX_IGNORED_SHIFT): New.
 416         (PREFIX_IGNORED_REPZ): Likewise.
 417         (PREFIX_IGNORED_REPNZ): Likewise.
 418         (PREFIX_IGNORED_DATA): Likewise.
 419         (PREFIX_IGNORED_ADDR): Likewise.
 420         (PREFIX_IGNORED_LOCK): Likewise.
 421         (PREFIX_OPCODE): Likewise.
 422         (PREFIX_IGNORED): Likewise.
 423         (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
 424         (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 425         (three_byte_table): Likewise.
 426         (mod_table): Likewise.
 427         (mandatory_prefix): Renamed to ...
 428         (prefix_requirement): This.
 429         (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 430         Update PREFIX_90 entry.
 431         (get_valid_dis386): Check prefix_requirement to see if a prefix
 432         should be ignored.
 433         (print_insn): Replace mandatory_prefix with prefix_requirement.
 434
 435 2015-04-15  Renlin Li  <renlin.li@arm.com>
 436
 437         * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
 438         use it for ssat and ssat16.
 439         (print_insn_thumb32): Add handle case for 'D' control code.
 440
 441 2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
 442             H.J. Lu  <hongjiu.lu@intel.com>
 443
 444         * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
 445         * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
 446         PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
 447         PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
 448         PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
 449         (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
 450         Fill prefix_requirement field.
 451         (struct dis386): Add prefix_requirement field.
 452         (dis386): Fill prefix_requirement field.
 453         (dis386_twobyte): Ditto.
 454         (twobyte_has_mandatory_prefix_: Remove.
 455         (reg_table): Fill prefix_requirement field.
 456         (prefix_table): Ditto.
 457         (x86_64_table): Ditto.
 458         (three_byte_table): Ditto.
 459         (xop_table): Ditto.
 460         (vex_table): Ditto.
 461         (vex_len_table): Ditto.
 462         (vex_w_table): Ditto.
 463         (mod_table): Ditto.
 464         (bad_opcode): Ditto.
 465         (print_insn): Use prefix_requirement.
 466         (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
 467         FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
 468         (float_reg): Ditto.
 469
 470 2015-03-30  Mike Frysinger  <vapier@gentoo.org>
 471
 472         * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
 473
 474 2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 475
 476         * Makefile.in: Regenerated.
 477
 478 2015-03-25  Anton Blanchard  <anton@samba.org>
 479
 480         * ppc-dis.c (disassemble_init_powerpc): Only initialise
 481         powerpc_opcd_indices and vle_opcd_indices once.
 482
 483 2015-03-25  Anton Blanchard  <anton@samba.org>
 484
 485         * ppc-opc.c (powerpc_opcodes): Add slbfee.
 486
 487 2015-03-24  Terry Guo  <terry.guo@arm.com>
 488
 489         * arm-dis.c (opcode32): Updated to use new arm feature struct.
 490         (opcode16): Likewise.
 491         (coprocessor_opcodes): Replace bit with feature struct.
 492         (neon_opcodes): Likewise.
 493         (arm_opcodes): Likewise.
 494         (thumb_opcodes): Likewise.
 495         (thumb32_opcodes): Likewise.
 496         (print_insn_coprocessor): Likewise.
 497         (print_insn_arm): Likewise.
 498         (select_arm_features): Follow new feature struct.
 499
 500 2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
 501
 502         * i386-dis.c (rm_table): Add clzero.
 503         * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
 504         Add CPU_CLZERO_FLAGS.
 505         (cpu_flags): Add CpuCLZERO.
 506         * i386-opc.h: Add CpuCLZERO.
 507         * i386-opc.tbl: Add clzero.
 508         * i386-init.h: Re-generated.
 509         * i386-tbl.h: Re-generated.
 510
 511 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 512
 513         * mips-opc.c (decode_mips_operand): Fix constraint issues
 514         with u and y operands.
 515
 516 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 517
 518         * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
 519
 520 2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 521
 522         * s390-opc.c: Add new IBM z13 instructions.
 523         * s390-opc.txt: Likewise.
 524
 525 2015-03-10  Renlin Li  <renlin.li@arm.com>
 526
 527         * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
 528         stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
 529         related alias.
 530         * aarch64-asm-2.c: Regenerate.
 531         * aarch64-dis-2.c: Likewise.
 532         * aarch64-opc-2.c: Likewise.
 533
 534 2015-03-03  Jiong Wang  <jiong.wang@arm.com>
 535
 536         * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
 537
 538 2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>
 539
 540         * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
 541         arch_sh_up.
 542         (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
 543         arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
 544
 545 2015-02-23  Vinay  <Vinay.G@kpit.com>
 546
 547         * rl78-decode.opc (MOV): Added space between two operands for
 548         'mov' instruction in index addressing mode.
 549         * rl78-decode.c: Regenerate.
 550
 551 2015-02-19  Pedro Alves  <palves@redhat.com>
 552
 553         * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
 554
 555 2015-02-10  Pedro Alves  <palves@redhat.com>
 556             Tom Tromey  <tromey@redhat.com>
 557
 558         * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
 559         microblaze_and, microblaze_xor.
 560         * microblaze-opc.h (opcodes): Adjust.
 561
 562 2015-01-28  James Bowman  <james.bowman@ftdichip.com>
 563
 564         * Makefile.am: Add FT32 files.
 565         * configure.ac: Handle FT32.
 566         * disassemble.c (disassembler): Call print_insn_ft32.
 567         * ft32-dis.c: New file.
 568         * ft32-opc.c: New file.
 569         * Makefile.in: Regenerate.
 570         * configure: Regenerate.
 571         * po/POTFILES.in: Regenerate.
 572
 573 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
 574
 575         * nds32-asm.c (keyword_sr): Add new system registers.
 576
 577 2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 578
 579         * s390-dis.c (s390_extract_operand): Support vector register
 580         operands.
 581         (s390_print_insn_with_opcode): Support new operands types and add
 582         new handling of optional operands.
 583         * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
 584         and include opcode/s390.h instead.
 585         (struct op_struct): New field `flags'.
 586         (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
 587         (dumpTable): Dump flags.
 588         (main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
 589         string.
 590         * s390-opc.c: Add new operands types, instruction formats, and
 591         instruction masks.
 592         (s390_opformats): Add new formats for .insn.
 593         * s390-opc.txt: Add new instructions.
 594
 595 2015-01-01  Alan Modra  <amodra@gmail.com>
 596
 597         Update year range in copyright notice of all files.
 598
 599 For older changes see ChangeLog-2014
 600 \f
 601 Copyright (C) 2015 Free Software Foundation, Inc.
 602
 603 Copying and distribution of this file, with or without modification,
 604 are permitted in any medium without royalty provided the copyright
 605 notice and this notice are preserved.
 606
 607 Local Variables:
 608 mode: change-log
 609 left-margin: 8
 610 fill-column: 74
 611 version-control: never
 612 End: