opcodes/ChangeLog

   1 2020-02-11  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
   4         * i386-opc.h (ShortForm): Delete.
   5         (struct i386_opcode_modifier): Remove shortform field.
   6         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
   7         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
   8         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
   9         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
  10         Drop ShortForm.
  11         * i386-tbl.h: Re-generate.
  12
  13 2020-02-11  Jan Beulich  <jbeulich@suse.com>
  14
  15         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
  16         fucompi): Drop ShortForm from operand-less templates.
  17         * i386-tbl.h: Re-generate.
  18
  19 2020-02-11  Alan Modra  <amodra@gmail.com>
  20
  21         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
  22         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
  23         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
  24         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
  25         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
  26
  27 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
  28
  29         * arm-dis.c (print_insn_cde): Define 'V' parse character.
  30         (cde_opcodes): Add VCX* instructions.
  31
  32 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
  33             Matthew Malcomson  <matthew.malcomson@arm.com>
  34
  35         * arm-dis.c (struct cdeopcode32): New.
  36         (CDE_OPCODE): New macro.
  37         (cde_opcodes): New disassembly table.
  38         (regnames): New option to table.
  39         (cde_coprocs): New global variable.
  40         (print_insn_cde): New
  41         (print_insn_thumb32): Use print_insn_cde.
  42         (parse_arm_disassembler_options): Parse coprocN args.
  43
  44 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
  45
  46         PR gas/25516
  47         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
  48         with ISA64.
  49         * i386-opc.h (AMD64): Removed.
  50         (Intel64): Likewose.
  51         (AMD64): New.
  52         (INTEL64): Likewise.
  53         (INTEL64ONLY): Likewise.
  54         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
  55         * i386-opc.tbl (Amd64): New.
  56         (Intel64): Likewise.
  57         (Intel64Only): Likewise.
  58         Replace AMD64 with Amd64.  Update sysenter/sysenter with
  59         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
  60         * i386-tbl.h: Regenerated.
  61
  62 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
  63
  64         PR 25469
  65         * z80-dis.c: Add support for GBZ80 opcodes.
  66
  67 2020-02-04  Alan Modra  <amodra@gmail.com>
  68
  69         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
  70
  71 2020-02-03  Alan Modra  <amodra@gmail.com>
  72
  73         * m32c-ibld.c: Regenerate.
  74
  75 2020-02-01  Alan Modra  <amodra@gmail.com>
  76
  77         * frv-ibld.c: Regenerate.
  78
  79 2020-01-31  Jan Beulich  <jbeulich@suse.com>
  80
  81         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
  82         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
  83         (OP_E_memory): Replace xmm_mdq_mode case label by
  84         vex_scalar_w_dq_mode one.
  85         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
  86
  87 2020-01-31  Jan Beulich  <jbeulich@suse.com>
  88
  89         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
  90         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
  91         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
  92         (intel_operand_size): Drop vex_w_dq_mode case label.
  93
  94 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
  95
  96         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
  97         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
  98
  99 2020-01-30  Alan Modra  <amodra@gmail.com>
 100
 101         * m32c-ibld.c: Regenerate.
 102
 103 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 104
 105         * bpf-opc.c: Regenerate.
 106
 107 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 108
 109         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 110         (dis386): Use them to replace C2/C3 table entries.
 111         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 112         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 113         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 114         * i386-tbl.h: Re-generate.
 115
 116 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 117
 118         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 119         forms.
 120         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 121         DefaultSize.
 122         * i386-tbl.h: Re-generate.
 123
 124 2020-01-30  Alan Modra  <amodra@gmail.com>
 125
 126         * tic4x-dis.c (tic4x_dp): Make unsigned.
 127
 128 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 129             Jan Beulich  <jbeulich@suse.com>
 130
 131         PR binutils/25445
 132         * i386-dis.c (MOVSXD_Fixup): New function.
 133         (movsxd_mode): New enum.
 134         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 135         (intel_operand_size): Handle movsxd_mode.
 136         (OP_E_register): Likewise.
 137         (OP_G): Likewise.
 138         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 139         register on movsxd.  Add movsxd with 16-bit destination register
 140         for AMD64 and Intel64 ISAs.
 141         * i386-tbl.h: Regenerated.
 142
 143 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 144
 145         PR 25403
 146         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 147         * aarch64-asm-2.c: Regenerate
 148         * aarch64-dis-2.c: Likewise.
 149         * aarch64-opc-2.c: Likewise.
 150
 151 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 152
 153         * i386-opc.tbl (sysret): Drop DefaultSize.
 154         * i386-tbl.h: Re-generate.
 155
 156 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 157
 158         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 159         Dword.
 160         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 161         * i386-tbl.h: Re-generate.
 162
 163 2020-01-20  Nick Clifton  <nickc@redhat.com>
 164
 165         * po/de.po: Updated German translation.
 166         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 167         * po/uk.po: Updated Ukranian translation.
 168
 169 2020-01-20  Alan Modra  <amodra@gmail.com>
 170
 171         * hppa-dis.c (fput_const): Remove useless cast.
 172
 173 2020-01-20  Alan Modra  <amodra@gmail.com>
 174
 175         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 176
 177 2020-01-18  Nick Clifton  <nickc@redhat.com>
 178
 179         * configure: Regenerate.
 180         * po/opcodes.pot: Regenerate.
 181
 182 2020-01-18  Nick Clifton  <nickc@redhat.com>
 183
 184         Binutils 2.34 branch created.
 185
 186 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 187
 188         * opintl.h: Fix spelling error (seperate).
 189
 190 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 191
 192         * i386-opc.tbl: Add {vex} pseudo prefix.
 193         * i386-tbl.h: Regenerated.
 194
 195 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 196
 197         PR 25376
 198         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 199         (neon_opcodes): Likewise.
 200         (select_arm_features): Make sure we enable MVE bits when selecting
 201         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 202         any architecture.
 203
 204 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 205
 206         * i386-opc.tbl: Drop stale comment from XOP section.
 207
 208 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 209
 210         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 211         (extractps): Add VexWIG to SSE2AVX forms.
 212         * i386-tbl.h: Re-generate.
 213
 214 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 215
 216         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 217         Size64 from and use VexW1 on SSE2AVX forms.
 218         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 219         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 220         * i386-tbl.h: Re-generate.
 221
 222 2020-01-15  Alan Modra  <amodra@gmail.com>
 223
 224         * tic4x-dis.c (tic4x_version): Make unsigned long.
 225         (optab, optab_special, registernames): New file scope vars.
 226         (tic4x_print_register): Set up registernames rather than
 227         malloc'd registertable.
 228         (tic4x_disassemble): Delete optable and optable_special.  Use
 229         optab and optab_special instead.  Throw away old optab,
 230         optab_special and registernames when info->mach changes.
 231
 232 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 233
 234         PR 25377
 235         * z80-dis.c (suffix): Use .db instruction to generate double
 236         prefix.
 237
 238 2020-01-14  Alan Modra  <amodra@gmail.com>
 239
 240         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 241         values to unsigned before shifting.
 242
 243 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 244
 245         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 246         flow instructions.
 247         (print_insn_thumb16, print_insn_thumb32): Likewise.
 248         (print_insn): Initialize the insn info.
 249         * i386-dis.c (print_insn): Initialize the insn info fields, and
 250         detect jumps.
 251
 252 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 253
 254         * arc-opc.c (C_NE): Make it required.
 255
 256 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 257
 258         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 259         reserved register name.
 260
 261 2020-01-13  Alan Modra  <amodra@gmail.com>
 262
 263         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 264         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 265
 266 2020-01-13  Alan Modra  <amodra@gmail.com>
 267
 268         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 269         result of wasm_read_leb128 in a uint64_t and check that bits
 270         are not lost when copying to other locals.  Use uint32_t for
 271         most locals.  Use PRId64 when printing int64_t.
 272
 273 2020-01-13  Alan Modra  <amodra@gmail.com>
 274
 275         * score-dis.c: Formatting.
 276         * score7-dis.c: Formatting.
 277
 278 2020-01-13  Alan Modra  <amodra@gmail.com>
 279
 280         * score-dis.c (print_insn_score48): Use unsigned variables for
 281         unsigned values.  Don't left shift negative values.
 282         (print_insn_score32): Likewise.
 283         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 284
 285 2020-01-13  Alan Modra  <amodra@gmail.com>
 286
 287         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 288
 289 2020-01-13  Alan Modra  <amodra@gmail.com>
 290
 291         * fr30-ibld.c: Regenerate.
 292
 293 2020-01-13  Alan Modra  <amodra@gmail.com>
 294
 295         * xgate-dis.c (print_insn): Don't left shift signed value.
 296         (ripBits): Formatting, use 1u.
 297
 298 2020-01-10  Alan Modra  <amodra@gmail.com>
 299
 300         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 301         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 302
 303 2020-01-10  Alan Modra  <amodra@gmail.com>
 304
 305         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 306         and XRREG value earlier to avoid a shift with negative exponent.
 307         * m10200-dis.c (disassemble): Similarly.
 308
 309 2020-01-09  Nick Clifton  <nickc@redhat.com>
 310
 311         PR 25224
 312         * z80-dis.c (ld_ii_ii): Use correct cast.
 313
 314 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 315
 316         PR 25224
 317         * z80-dis.c (ld_ii_ii): Use character constant when checking
 318         opcode byte value.
 319
 320 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 321
 322         * i386-dis.c (SEP_Fixup): New.
 323         (SEP): Define.
 324         (dis386_twobyte): Use it for sysenter/sysexit.
 325         (enum x86_64_isa): Change amd64 enumerator to value 1.
 326         (OP_J): Compare isa64 against intel64 instead of amd64.
 327         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 328         forms.
 329         * i386-tbl.h: Re-generate.
 330
 331 2020-01-08  Alan Modra  <amodra@gmail.com>
 332
 333         * z8k-dis.c: Include libiberty.h
 334         (instr_data_s): Make max_fetched unsigned.
 335         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 336         Don't exceed byte_info bounds.
 337         (output_instr): Make num_bytes unsigned.
 338         (unpack_instr): Likewise for nibl_count and loop.
 339         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 340         idx unsigned.
 341         * z8k-opc.h: Regenerate.
 342
 343 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 344
 345         * arc-tbl.h (llock): Use 'LLOCK' as class.
 346         (llockd): Likewise.
 347         (scond): Use 'SCOND' as class.
 348         (scondd): Likewise.
 349         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 350         (scondd): Likewise.
 351
 352 2020-01-06  Alan Modra  <amodra@gmail.com>
 353
 354         * m32c-ibld.c: Regenerate.
 355
 356 2020-01-06  Alan Modra  <amodra@gmail.com>
 357
 358         PR 25344
 359         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 360         Peek at next byte to prevent recursion on repeated prefix bytes.
 361         Ensure uninitialised "mybuf" is not accessed.
 362         (print_insn_z80): Don't zero n_fetch and n_used here,..
 363         (print_insn_z80_buf): ..do it here instead.
 364
 365 2020-01-04  Alan Modra  <amodra@gmail.com>
 366
 367         * m32r-ibld.c: Regenerate.
 368
 369 2020-01-04  Alan Modra  <amodra@gmail.com>
 370
 371         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 372
 373 2020-01-04  Alan Modra  <amodra@gmail.com>
 374
 375         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 376
 377 2020-01-04  Alan Modra  <amodra@gmail.com>
 378
 379         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 380
 381 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 382
 383         * aarch64-tbl.h (aarch64_opcode_table): Use
 384         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 385
 386 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 387
 388         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 389         forms of SUDOT and USDOT.
 390
 391 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 392
 393         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 394         uzip{1,2}.
 395         * opcodes/aarch64-dis-2.c: Re-generate.
 396
 397 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 398
 399         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 400         FMMLA encoding.
 401         * opcodes/aarch64-dis-2.c: Re-generate.
 402
 403 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 404
 405         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 406
 407 2020-01-01  Alan Modra  <amodra@gmail.com>
 408
 409         Update year range in copyright notice of all files.
 410
 411 For older changes see ChangeLog-2019
 412 \f
 413 Copyright (C) 2020 Free Software Foundation, Inc.
 414
 415 Copying and distribution of this file, with or without modification,
 416 are permitted in any medium without royalty provided the copyright
 417 notice and this notice are preserved.
 418
 419 Local Variables:
 420 mode: change-log
 421 left-margin: 8
 422 fill-column: 74
 423 version-control: never
 424 End: