opcodes/ChangeLog

   1 2019-09-23  Alan Modra  <amodra@gmail.com>
   2
   3         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
   4         "elf/mips.h" earlier.
   5
   6 2018-09-20  Jan Beulich  <jbeulich@suse.com>
   7
   8         PR gas/25012
   9         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
  10         with SReg operand.
  11         * i386-tbl.h: Re-generate.
  12
  13 2019-09-18  Alan Modra  <amodra@gmail.com>
  14
  15         * arc-ext.c: Update throughout for bfd section macro changes.
  16
  17 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
  18
  19         * Makefile.in: Re-generate.
  20         * configure: Re-generate.
  21
  22 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
  23
  24         * riscv-opc.c (riscv_opcodes): Change subset field
  25         to insn_class field for all instructions.
  26         (riscv_insn_types): Likewise.
  27
  28 2019-09-16  Phil Blundell  <pb@pbcl.net>
  29
  30         * configure: Regenerated.
  31
  32 2019-09-10  Miod Vallat  <miod@online.fr>
  33
  34         PR 24982
  35         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
  36
  37 2019-09-09  Phil Blundell  <pb@pbcl.net>
  38
  39         binutils 2.33 branch created.
  40
  41 2019-09-03  Nick Clifton  <nickc@redhat.com>
  42
  43         PR 24961
  44         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
  45         greater than zero before indexing via (bufcnt -1).
  46
  47 2019-09-03  Nick Clifton  <nickc@redhat.com>
  48
  49         PR 24958
  50         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
  51         (MAX_SPEC_REG_NAME_LEN): Define.
  52         (struct mmix_dis_info): Use defined constants for array lengths.
  53         (get_reg_name): New function.
  54         (get_sprec_reg_name): New function.
  55         (print_insn_mmix): Use new functions.
  56
  57 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
  58
  59         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
  60         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
  61         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
  62
  63 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
  64
  65         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
  66         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
  67         (aarch64_sys_reg_supported_p): Update checks for the above.
  68
  69 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
  70
  71         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
  72         cases MVE_SQRSHRL and MVE_UQRSHLL.
  73         (print_insn_mve): Add case for specifier 'k' to check
  74         specific bit of the instruction.
  75
  76 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
  77
  78         PR 24854
  79         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
  80         encountering an unknown machine type.
  81         (print_insn_arc): Handle arc_insn_length returning 0.  In error
  82         cases return -1 rather than calling abort.
  83
  84 2019-08-07  Jan Beulich  <jbeulich@suse.com>
  85
  86         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
  87         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
  88         IgnoreSize.
  89         * i386-tbl.h: Re-generate.
  90
  91 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
  92
  93         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
  94         instructions.
  95
  96 2019-07-30  Mel Chen <mel.chen@sifive.com>
  97
  98         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
  99         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 100
 101         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 102         fscsr.
 103
 104 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 105
 106         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 107         and MPY class instructions.
 108         (parse_option): Add nps400 option.
 109         (print_arc_disassembler_options): Add nps400 info.
 110
 111 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 112
 113         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 114         (bspop): Likewise.
 115         (modapp): Likewise.
 116         * arc-opc.c (RAD_CHK): Add.
 117         * arc-tbl.h: Regenerate.
 118
 119 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 120
 121         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 122         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 123
 124 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 125
 126         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 127         instructions as UNPREDICTABLE.
 128
 129 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 130
 131         * bpf-desc.c: Regenerated.
 132
 133 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 134
 135         * i386-gen.c (static_assert): Define.
 136         (main): Use it.
 137         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 138         (Opcode_Modifier_Num): ... this.
 139         (Mem): Delete.
 140
 141 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 142
 143         * i386-gen.c (operand_types): Move RegMem ...
 144         (opcode_modifiers): ... here.
 145         * i386-opc.h (RegMem): Move to opcode modifer enum.
 146         (union i386_operand_type): Move regmem field ...
 147         (struct i386_opcode_modifier): ... here.
 148         * i386-opc.tbl (RegMem): Define.
 149         (mov, movq): Move RegMem on segment, control, debug, and test
 150         register flavors.
 151         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 152         to non-SSE2AVX flavor.
 153         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 154         Move RegMem on register only flavors. Drop IgnoreSize from
 155         legacy encoding flavors.
 156         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 157         flavors.
 158         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 159         register only flavors.
 160         (vmovd): Move RegMem and drop IgnoreSize on register only
 161         flavor. Change opcode and operand order to store form.
 162         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 163
 164 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 165
 166         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 167         entries.
 168         * i386-opc.h (SReg2, SReg3): Replace by ...
 169         (SReg): ... this.
 170         (union i386_operand_type): Replace sreg fields.
 171         * i386-opc.tbl (mov, ): Use SReg.
 172         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 173         register flavors.
 174         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 175         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 176
 177 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 178
 179         * bpf-desc.c: Regenerate.
 180         * bpf-opc.c: Likewise.
 181         * bpf-opc.h: Likewise.
 182
 183 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 184
 185         * bpf-desc.c: Regenerate.
 186         * bpf-opc.c: Likewise.
 187
 188 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 189
 190         * arm-dis.c (print_insn_coprocessor): Rename index to
 191         index_operand.
 192
 193 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 194
 195         * riscv-opc.c (riscv_insn_types): Add r4 type.
 196
 197         * riscv-opc.c (riscv_insn_types): Add b and j type.
 198
 199         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 200         format for sb type and correct s type.
 201
 202 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 203
 204         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 205         SVE FMOV alias of FCPY.
 206
 207 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 208
 209         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 210         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 211
 212 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 213
 214         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 215         registers in an instruction prefixed by MOVPRFX.
 216
 217 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 218
 219         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 220         sve_size_13 icode to account for variant behaviour of
 221         pmull{t,b}.
 222         * aarch64-dis-2.c: Regenerate.
 223         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 224         sve_size_13 icode to account for variant behaviour of
 225         pmull{t,b}.
 226         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 227         (OP_SVE_VVV_Q_D): Add new qualifier.
 228         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 229         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 230         AES and those not.
 231
 232 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 233
 234         * opcodes/i386-gen.c (operand_type_init): Remove
 235         OPERAND_TYPE_VEC_IMM4 entry.
 236         (operand_types): Remove Vec_Imm4.
 237         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 238         (union i386_operand_type): Remove vec_imm4.
 239         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 240         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 241
 242 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 243
 244         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 245         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 246         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 247         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 248         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 249         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 250         * i386-tbl.h: Re-generate.
 251
 252 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 253
 254         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 255         register operands.
 256         * i386-tbl.h: Re-generate.
 257
 258 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 259
 260         * i386-opc.tbl (C): New.
 261         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 262         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 263         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 264         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 265         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 266         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 267         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 268         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 269         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 270         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 271         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 272         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 273         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 274         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 275         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 276         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 277         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 278         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 279         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 280         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 281         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 282         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 283         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 284         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 285         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 286         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 287         flavors.
 288         * i386-tbl.h: Re-generate.
 289
 290 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 291
 292         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 293         register operands.
 294         * i386-tbl.h: Re-generate.
 295
 296 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 297
 298         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 299         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 300         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 301         * i386-tbl.h: Re-generate.
 302
 303 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 304
 305         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 306         Disp8MemShift from register only templates.
 307         * i386-tbl.h: Re-generate.
 308
 309 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 310
 311         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 312         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 313         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 314         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 315         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 316         EVEX_W_0F11_P_3_M_1): Delete.
 317         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 318         EVEX_W_0F11_P_3): New.
 319         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 320         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 321         MOD_EVEX_0F11_PREFIX_3 table entries.
 322         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 323         PREFIX_EVEX_0F11 table entries.
 324         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 325         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 326         EVEX_W_0F11_P_3_M_{0,1} table entries.
 327
 328 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 329
 330         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 331         Delete.
 332
 333 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 334
 335         PR binutils/24719
 336         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 337         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 338         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 339         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 340         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 341         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 342         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 343         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 344         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 345         PREFIX_EVEX_0F38C6_REG_6 entries.
 346         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 347         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 348         EVEX_W_0F38C7_R_6_P_2 entries.
 349         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 350         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 351         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 352         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 353         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 354         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 355         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 356
 357 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 358
 359         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 360         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 361         VEX_LEN_0F2D_P_3): Delete.
 362         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 363         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 364         (prefix_table): ... here.
 365
 366 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 367
 368         * i386-dis.c (Iq): Delete.
 369         (Id): New.
 370         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 371         TBM insns.
 372         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 373         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 374         (OP_E_memory): Also honor needindex when deciding whether an
 375         address size prefix needs printing.
 376         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 377
 378 2019-06-26  Jim Wilson  <jimw@sifive.com>
 379
 380         PR binutils/24739
 381         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 382         Set info->display_endian to info->endian_code.
 383
 384 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 385
 386         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 387         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 388         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 389         OPERAND_TYPE_ACC64 entries.
 390         * i386-init.h: Re-generate.
 391
 392 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 393
 394         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 395         Delete.
 396         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 397         of dqa_mode.
 398         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 399         entries here.
 400         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 401         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 402
 403 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 404
 405         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 406         variables.
 407
 408 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 409
 410         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 411         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 412         movnti.
 413         * i386-opc.tbl (movnti): Add IgnoreSize.
 414         * i386-tbl.h: Re-generate.
 415
 416 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 417
 418         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 419         * i386-tbl.h: Re-generate.
 420
 421 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 422
 423         * i386-dis-evex.h: Break into ...
 424         * i386-dis-evex-len.h: New file.
 425         * i386-dis-evex-mod.h: Likewise.
 426         * i386-dis-evex-prefix.h: Likewise.
 427         * i386-dis-evex-reg.h: Likewise.
 428         * i386-dis-evex-w.h: Likewise.
 429         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 430         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 431         i386-dis-evex-mod.h.
 432
 433 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 434
 435         PR binutils/24700
 436         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 437         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 438         EVEX_W_0F385B_P_2.
 439         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 440         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 441         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 442         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 443         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 444         EVEX_LEN_0F385B_P_2_W_1.
 445         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 446         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 447         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 448         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 449         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 450         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 451         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 452         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 453         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 454         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 455
 456 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 457
 458         PR binutils/24691
 459         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 460         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 461         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 462         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 463         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 464         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 465         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 466         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 467         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 468         EVEX_LEN_0F3A43_P_2_W_1.
 469         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 470         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 471         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 472         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 473         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 474         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 475         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 476         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 477         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 478         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 479         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 480         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 481
 482 2019-06-14  Nick Clifton  <nickc@redhat.com>
 483
 484         * po/fr.po; Updated French translation.
 485
 486 2019-06-13  Stafford Horne  <shorne@gmail.com>
 487
 488         * or1k-asm.c: Regenerated.
 489         * or1k-desc.c: Regenerated.
 490         * or1k-desc.h: Regenerated.
 491         * or1k-dis.c: Regenerated.
 492         * or1k-ibld.c: Regenerated.
 493         * or1k-opc.c: Regenerated.
 494         * or1k-opc.h: Regenerated.
 495         * or1k-opinst.c: Regenerated.
 496
 497 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 498
 499         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 500
 501 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 502
 503         PR binutils/24633
 504         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 505         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 506         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 507         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 508         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 509         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 510         EVEX_LEN_0F3A1B_P_2_W_1.
 511         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 512         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 513         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 514         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 515         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 516         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 517         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 518         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 519
 520 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 521
 522         PR binutils/24626
 523         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 524         EVEX.vvvv when disassembling VEX and EVEX instructions.
 525         (OP_VEX): Set vex.register_specifier to 0 after readding
 526         vex.register_specifier.
 527         (OP_Vex_2src_1): Likewise.
 528         (OP_Vex_2src_2): Likewise.
 529         (OP_LWP_E): Likewise.
 530         (OP_EX_Vex): Don't check vex.register_specifier.
 531         (OP_XMM_Vex): Likewise.
 532
 533 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 534             Lili Cui  <lili.cui@intel.com>
 535
 536         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 537         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 538         instructions.
 539         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 540         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 541         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 542         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 543         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 544         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 545         * i386-init.h: Regenerated.
 546         * i386-tbl.h: Likewise.
 547
 548 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 549             Lili Cui  <lili.cui@intel.com>
 550
 551         * doc/c-i386.texi: Document enqcmd.
 552         * testsuite/gas/i386/enqcmd-intel.d: New file.
 553         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 554         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 555         * testsuite/gas/i386/enqcmd.d: Likewise.
 556         * testsuite/gas/i386/enqcmd.s: Likewise.
 557         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 558         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 559         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 560         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 561         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 562         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 563         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 564         and x86-64-enqcmd.
 565
 566 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 567
 568         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 569
 570 2019-06-03  Alan Modra  <amodra@gmail.com>
 571
 572         * ppc-dis.c (prefix_opcd_indices): Correct size.
 573
 574 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 575
 576         PR gas/24625
 577         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 578         Disp8ShiftVL.
 579         * i386-tbl.h: Regenerated.
 580
 581 2019-05-24  Alan Modra  <amodra@gmail.com>
 582
 583         * po/POTFILES.in: Regenerate.
 584
 585 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 586             Alan Modra  <amodra@gmail.com>
 587
 588         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 589         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 590         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 591         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 592         XTOP>): Define and add entries.
 593         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 594         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 595         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 596         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 597
 598 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 599             Alan Modra  <amodra@gmail.com>
 600
 601         * ppc-dis.c (ppc_opts): Add "future" entry.
 602         (PREFIX_OPCD_SEGS): Define.
 603         (prefix_opcd_indices): New array.
 604         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 605         (lookup_prefix): New function.
 606         (print_insn_powerpc): Handle 64-bit prefix instructions.
 607         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 608         (PMRR, POWERXX): Define.
 609         (prefix_opcodes): New instruction table.
 610         (prefix_num_opcodes): New constant.
 611
 612 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 613
 614         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 615         * configure: Regenerated.
 616         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 617         and cpu/bpf.opc.
 618         (HFILES): Add bpf-desc.h and bpf-opc.h.
 619         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 620         bpf-ibld.c and bpf-opc.c.
 621         (BPF_DEPS): Define.
 622         * Makefile.in: Regenerated.
 623         * disassemble.c (ARCH_bpf): Define.
 624         (disassembler): Add case for bfd_arch_bpf.
 625         (disassemble_init_for_target): Likewise.
 626         (enum epbf_isa_attr): Define.
 627         * disassemble.h: extern print_insn_bpf.
 628         * bpf-asm.c: Generated.
 629         * bpf-opc.h: Likewise.
 630         * bpf-opc.c: Likewise.
 631         * bpf-ibld.c: Likewise.
 632         * bpf-dis.c: Likewise.
 633         * bpf-desc.h: Likewise.
 634         * bpf-desc.c: Likewise.
 635
 636 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 637
 638         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 639         and VMSR with the new operands.
 640
 641 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 642
 643         * arm-dis.c (enum mve_instructions): New enum
 644         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 645         and cneg.
 646         (mve_opcodes): New instructions as above.
 647         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 648         csneg and csel.
 649         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 650
 651 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 652
 653         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 654         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 655         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 656         uqshl, urshrl and urshr.
 657         (is_mve_okay_in_it): Add new instructions to TRUE list.
 658         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 659         (print_insn_mve): Updated to accept new %j,
 660         %<bitfield>m and %<bitfield>n patterns.
 661
 662 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 663
 664         * mips-opc.c (mips_builtin_opcodes): Change source register
 665         constraint for DAUI.
 666
 667 2019-05-20  Nick Clifton  <nickc@redhat.com>
 668
 669         * po/fr.po: Updated French translation.
 670
 671 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 672             Michael Collison <michael.collison@arm.com>
 673
 674         * arm-dis.c (thumb32_opcodes): Add new instructions.
 675         (enum mve_instructions): Likewise.
 676         (enum mve_undefined): Add new reasons.
 677         (is_mve_encoding_conflict): Handle new instructions.
 678         (is_mve_undefined): Likewise.
 679         (is_mve_unpredictable): Likewise.
 680         (print_mve_undefined): Likewise.
 681         (print_mve_size): Likewise.
 682
 683 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 684             Michael Collison <michael.collison@arm.com>
 685
 686         * arm-dis.c (thumb32_opcodes): Add new instructions.
 687         (enum mve_instructions): Likewise.
 688         (is_mve_encoding_conflict): Handle new instructions.
 689         (is_mve_undefined): Likewise.
 690         (is_mve_unpredictable): Likewise.
 691         (print_mve_size): Likewise.
 692
 693 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 694             Michael Collison <michael.collison@arm.com>
 695
 696         * arm-dis.c (thumb32_opcodes): Add new instructions.
 697         (enum mve_instructions): Likewise.
 698         (is_mve_encoding_conflict): Likewise.
 699         (is_mve_unpredictable): Likewise.
 700         (print_mve_size): Likewise.
 701
 702 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 703             Michael Collison <michael.collison@arm.com>
 704
 705         * arm-dis.c (thumb32_opcodes): Add new instructions.
 706         (enum mve_instructions): Likewise.
 707         (is_mve_encoding_conflict): Handle new instructions.
 708         (is_mve_undefined): Likewise.
 709         (is_mve_unpredictable): Likewise.
 710         (print_mve_size): Likewise.
 711
 712 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 713             Michael Collison <michael.collison@arm.com>
 714
 715         * arm-dis.c (thumb32_opcodes): Add new instructions.
 716         (enum mve_instructions): Likewise.
 717         (is_mve_encoding_conflict): Handle new instructions.
 718         (is_mve_undefined): Likewise.
 719         (is_mve_unpredictable): Likewise.
 720         (print_mve_size): Likewise.
 721         (print_insn_mve): Likewise.
 722
 723 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 724             Michael Collison <michael.collison@arm.com>
 725
 726         * arm-dis.c (thumb32_opcodes): Add new instructions.
 727         (print_insn_thumb32): Handle new instructions.
 728
 729 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 730             Michael Collison <michael.collison@arm.com>
 731
 732         * arm-dis.c (enum mve_instructions): Add new instructions.
 733         (enum mve_undefined): Add new reasons.
 734         (is_mve_encoding_conflict): Handle new instructions.
 735         (is_mve_undefined): Likewise.
 736         (is_mve_unpredictable): Likewise.
 737         (print_mve_undefined): Likewise.
 738         (print_mve_size): Likewise.
 739         (print_mve_shift_n): Likewise.
 740         (print_insn_mve): Likewise.
 741
 742 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 743             Michael Collison <michael.collison@arm.com>
 744
 745         * arm-dis.c (enum mve_instructions): Add new instructions.
 746         (is_mve_encoding_conflict): Handle new instructions.
 747         (is_mve_unpredictable): Likewise.
 748         (print_mve_rotate): Likewise.
 749         (print_mve_size): Likewise.
 750         (print_insn_mve): Likewise.
 751
 752 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 753             Michael Collison <michael.collison@arm.com>
 754
 755         * arm-dis.c (enum mve_instructions): Add new instructions.
 756         (is_mve_encoding_conflict): Handle new instructions.
 757         (is_mve_unpredictable): Likewise.
 758         (print_mve_size): Likewise.
 759         (print_insn_mve): Likewise.
 760
 761 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 762             Michael Collison <michael.collison@arm.com>
 763
 764         * arm-dis.c (enum mve_instructions): Add new instructions.
 765         (enum mve_undefined): Add new reasons.
 766         (is_mve_encoding_conflict): Handle new instructions.
 767         (is_mve_undefined): Likewise.
 768         (is_mve_unpredictable): Likewise.
 769         (print_mve_undefined): Likewise.
 770         (print_mve_size): Likewise.
 771         (print_insn_mve): Likewise.
 772
 773 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 774             Michael Collison <michael.collison@arm.com>
 775
 776         * arm-dis.c (enum mve_instructions): Add new instructions.
 777         (is_mve_encoding_conflict): Handle new instructions.
 778         (is_mve_undefined): Likewise.
 779         (is_mve_unpredictable): Likewise.
 780         (print_mve_size): Likewise.
 781         (print_insn_mve): Likewise.
 782
 783 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 784             Michael Collison <michael.collison@arm.com>
 785
 786         * arm-dis.c (enum mve_instructions): Add new instructions.
 787         (enum mve_unpredictable): Add new reasons.
 788         (enum mve_undefined): Likewise.
 789         (is_mve_okay_in_it): Handle new isntructions.
 790         (is_mve_encoding_conflict): Likewise.
 791         (is_mve_undefined): Likewise.
 792         (is_mve_unpredictable): Likewise.
 793         (print_mve_vmov_index): Likewise.
 794         (print_simd_imm8): Likewise.
 795         (print_mve_undefined): Likewise.
 796         (print_mve_unpredictable): Likewise.
 797         (print_mve_size): Likewise.
 798         (print_insn_mve): Likewise.
 799
 800 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 801             Michael Collison <michael.collison@arm.com>
 802
 803         * arm-dis.c (enum mve_instructions): Add new instructions.
 804         (enum mve_unpredictable): Add new reasons.
 805         (enum mve_undefined): Likewise.
 806         (is_mve_encoding_conflict): Handle new instructions.
 807         (is_mve_undefined): Likewise.
 808         (is_mve_unpredictable): Likewise.
 809         (print_mve_undefined): Likewise.
 810         (print_mve_unpredictable): Likewise.
 811         (print_mve_rounding_mode): Likewise.
 812         (print_mve_vcvt_size): Likewise.
 813         (print_mve_size): Likewise.
 814         (print_insn_mve): Likewise.
 815
 816 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 817             Michael Collison <michael.collison@arm.com>
 818
 819         * arm-dis.c (enum mve_instructions): Add new instructions.
 820         (enum mve_unpredictable): Add new reasons.
 821         (enum mve_undefined): Likewise.
 822         (is_mve_undefined): Handle new instructions.
 823         (is_mve_unpredictable): Likewise.
 824         (print_mve_undefined): Likewise.
 825         (print_mve_unpredictable): Likewise.
 826         (print_mve_size): Likewise.
 827         (print_insn_mve): Likewise.
 828
 829 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 830             Michael Collison <michael.collison@arm.com>
 831
 832         * arm-dis.c (enum mve_instructions): Add new instructions.
 833         (enum mve_undefined): Add new reasons.
 834         (insns): Add new instructions.
 835         (is_mve_encoding_conflict):
 836         (print_mve_vld_str_addr): New print function.
 837         (is_mve_undefined): Handle new instructions.
 838         (is_mve_unpredictable): Likewise.
 839         (print_mve_undefined): Likewise.
 840         (print_mve_size): Likewise.
 841         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 842         (print_insn_mve):  Handle new operands.
 843
 844 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 845             Michael Collison <michael.collison@arm.com>
 846
 847         * arm-dis.c (enum mve_instructions): Add new instructions.
 848         (enum mve_unpredictable): Add new reasons.
 849         (is_mve_encoding_conflict): Handle new instructions.
 850         (is_mve_unpredictable): Likewise.
 851         (mve_opcodes): Add new instructions.
 852         (print_mve_unpredictable): Handle new reasons.
 853         (print_mve_register_blocks): New print function.
 854         (print_mve_size): Handle new instructions.
 855         (print_insn_mve): Likewise.
 856
 857 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 858             Michael Collison <michael.collison@arm.com>
 859
 860         * arm-dis.c (enum mve_instructions): Add new instructions.
 861         (enum mve_unpredictable): Add new reasons.
 862         (enum mve_undefined): Likewise.
 863         (is_mve_encoding_conflict): Handle new instructions.
 864         (is_mve_undefined): Likewise.
 865         (is_mve_unpredictable): Likewise.
 866         (coprocessor_opcodes): Move NEON VDUP from here...
 867         (neon_opcodes): ... to here.
 868         (mve_opcodes): Add new instructions.
 869         (print_mve_undefined):  Handle new reasons.
 870         (print_mve_unpredictable): Likewise.
 871         (print_mve_size): Handle new instructions.
 872         (print_insn_neon): Handle vdup.
 873         (print_insn_mve): Handle new operands.
 874
 875 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 876             Michael Collison <michael.collison@arm.com>
 877
 878         * arm-dis.c (enum mve_instructions): Add new instructions.
 879         (enum mve_unpredictable): Add new values.
 880         (mve_opcodes): Add new instructions.
 881         (vec_condnames): New array with vector conditions.
 882         (mve_predicatenames): New array with predicate suffixes.
 883         (mve_vec_sizename): New array with vector sizes.
 884         (enum vpt_pred_state): New enum with vector predication states.
 885         (struct vpt_block): New struct type for vpt blocks.
 886         (vpt_block_state): Global struct to keep track of state.
 887         (mve_extract_pred_mask): New helper function.
 888         (num_instructions_vpt_block): Likewise.
 889         (mark_outside_vpt_block): Likewise.
 890         (mark_inside_vpt_block): Likewise.
 891         (invert_next_predicate_state): Likewise.
 892         (update_next_predicate_state): Likewise.
 893         (update_vpt_block_state): Likewise.
 894         (is_vpt_instruction): Likewise.
 895         (is_mve_encoding_conflict): Add entries for new instructions.
 896         (is_mve_unpredictable): Likewise.
 897         (print_mve_unpredictable): Handle new cases.
 898         (print_instruction_predicate): Likewise.
 899         (print_mve_size): New function.
 900         (print_vec_condition): New function.
 901         (print_insn_mve): Handle vpt blocks and new print operands.
 902
 903 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 904
 905         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 906         8, 14 and 15 for Armv8.1-M Mainline.
 907
 908 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 909             Michael Collison <michael.collison@arm.com>
 910
 911         * arm-dis.c (enum mve_instructions): New enum.
 912         (enum mve_unpredictable): Likewise.
 913         (enum mve_undefined): Likewise.
 914         (struct mopcode32): New struct.
 915         (is_mve_okay_in_it): New function.
 916         (is_mve_architecture): Likewise.
 917         (arm_decode_field): Likewise.
 918         (arm_decode_field_multiple): Likewise.
 919         (is_mve_encoding_conflict): Likewise.
 920         (is_mve_undefined): Likewise.
 921         (is_mve_unpredictable): Likewise.
 922         (print_mve_undefined): Likewise.
 923         (print_mve_unpredictable): Likewise.
 924         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 925         (print_insn_mve): New function.
 926         (print_insn_thumb32): Handle MVE architecture.
 927         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 928
 929 2019-05-10  Nick Clifton  <nickc@redhat.com>
 930
 931         PR 24538
 932         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 933         end of the table prematurely.
 934
 935 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 936
 937         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 938         macros for R6.
 939
 940 2019-05-11  Alan Modra  <amodra@gmail.com>
 941
 942         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 943         when -Mraw is in effect.
 944
 945 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 946
 947         * aarch64-dis-2.c: Regenerate.
 948         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 949         (OP_SVE_BBB): New variant set.
 950         (OP_SVE_DDDD): New variant set.
 951         (OP_SVE_HHH): New variant set.
 952         (OP_SVE_HHHU): New variant set.
 953         (OP_SVE_SSS): New variant set.
 954         (OP_SVE_SSSU): New variant set.
 955         (OP_SVE_SHH): New variant set.
 956         (OP_SVE_SBBU): New variant set.
 957         (OP_SVE_DSS): New variant set.
 958         (OP_SVE_DHHU): New variant set.
 959         (OP_SVE_VMV_HSD_BHS): New variant set.
 960         (OP_SVE_VVU_HSD_BHS): New variant set.
 961         (OP_SVE_VVVU_SD_BH): New variant set.
 962         (OP_SVE_VVVU_BHSD): New variant set.
 963         (OP_SVE_VVV_QHD_DBS): New variant set.
 964         (OP_SVE_VVV_HSD_BHS): New variant set.
 965         (OP_SVE_VVV_HSD_BHS2): New variant set.
 966         (OP_SVE_VVV_BHS_HSD): New variant set.
 967         (OP_SVE_VV_BHS_HSD): New variant set.
 968         (OP_SVE_VVV_SD): New variant set.
 969         (OP_SVE_VVU_BHS_HSD): New variant set.
 970         (OP_SVE_VZVV_SD): New variant set.
 971         (OP_SVE_VZVV_BH): New variant set.
 972         (OP_SVE_VZV_SD): New variant set.
 973         (aarch64_opcode_table): Add sve2 instructions.
 974
 975 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 976
 977         * aarch64-asm-2.c: Regenerated.
 978         * aarch64-dis-2.c: Regenerated.
 979         * aarch64-opc-2.c: Regenerated.
 980         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 981         for SVE_SHLIMM_UNPRED_22.
 982         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 983         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 984         operand.
 985
 986 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 987
 988         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 989         sve_size_tsz_bhs iclass encode.
 990         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 991         sve_size_tsz_bhs iclass decode.
 992
 993 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 994
 995         * aarch64-asm-2.c: Regenerated.
 996         * aarch64-dis-2.c: Regenerated.
 997         * aarch64-opc-2.c: Regenerated.
 998         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 999         for SVE_Zm4_11_INDEX.
1000         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1001         (fields): Handle SVE_i2h field.
1002         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1003         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1004
1005 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1006
1007         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1008         sve_shift_tsz_bhsd iclass encode.
1009         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1010         sve_shift_tsz_bhsd iclass decode.
1011
1012 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1013
1014         * aarch64-asm-2.c: Regenerated.
1015         * aarch64-dis-2.c: Regenerated.
1016         * aarch64-opc-2.c: Regenerated.
1017         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1018         (aarch64_encode_variant_using_iclass): Handle
1019         sve_shift_tsz_hsd iclass encode.
1020         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1021         sve_shift_tsz_hsd iclass decode.
1022         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1023         for SVE_SHRIMM_UNPRED_22.
1024         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1025         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1026         operand.
1027
1028 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1029
1030         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1031         sve_size_013 iclass encode.
1032         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1033         sve_size_013 iclass decode.
1034
1035 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1036
1037         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1038         sve_size_bh iclass encode.
1039         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1040         sve_size_bh iclass decode.
1041
1042 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1043
1044         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1045         sve_size_sd2 iclass encode.
1046         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1047         sve_size_sd2 iclass decode.
1048         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1049         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1050
1051 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1052
1053         * aarch64-asm-2.c: Regenerated.
1054         * aarch64-dis-2.c: Regenerated.
1055         * aarch64-opc-2.c: Regenerated.
1056         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1057         for SVE_ADDR_ZX.
1058         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1059         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1060
1061 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1062
1063         * aarch64-asm-2.c: Regenerated.
1064         * aarch64-dis-2.c: Regenerated.
1065         * aarch64-opc-2.c: Regenerated.
1066         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1067         for SVE_Zm3_11_INDEX.
1068         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1069         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1070         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1071         fields.
1072         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1073
1074 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1075
1076         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1077         sve_size_hsd2 iclass encode.
1078         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1079         sve_size_hsd2 iclass decode.
1080         * aarch64-opc.c (fields): Handle SVE_size field.
1081         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1082
1083 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1084
1085         * aarch64-asm-2.c: Regenerated.
1086         * aarch64-dis-2.c: Regenerated.
1087         * aarch64-opc-2.c: Regenerated.
1088         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1089         for SVE_IMM_ROT3.
1090         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1091         (fields): Handle SVE_rot3 field.
1092         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1093         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1094
1095 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1096
1097         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1098         instructions.
1099
1100 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1101
1102         * aarch64-tbl.h
1103         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1104         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1105         aarch64_feature_sve2bitperm): New feature sets.
1106         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1107         for feature set addresses.
1108         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1109         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1110
1111 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1112             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1113
1114         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1115         argument and set ASE_EVA_R6 appropriately.
1116         (set_default_mips_dis_options): Pass ISA to above.
1117         (parse_mips_dis_option): Likewise.
1118         * mips-opc.c (EVAR6): New macro.
1119         (mips_builtin_opcodes): Add llwpe, scwpe.
1120
1121 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1122
1123         * aarch64-asm-2.c: Regenerated.
1124         * aarch64-dis-2.c: Regenerated.
1125         * aarch64-opc-2.c: Regenerated.
1126         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1127         AARCH64_OPND_TME_UIMM16.
1128         (aarch64_print_operand): Likewise.
1129         * aarch64-tbl.h (QL_IMM_NIL): New.
1130         (TME): New.
1131         (_TME_INSN): New.
1132         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1133
1134 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1135
1136         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1137
1138 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1139             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1140
1141         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1142
1143 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1144
1145         * s12z-opc.h: Add extern "C" bracketing to help
1146         users who wish to use this interface in c++ code.
1147
1148 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1149
1150         * s12z-opc.c (bm_decode): Handle bit map operations with the
1151         "reserved0" mode.
1152
1153 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1154
1155         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1156         specifier.  Add entries for VLDR and VSTR of system registers.
1157         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1158         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1159         of %J and %K format specifier.
1160
1161 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1162
1163         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1164         Add new entries for VSCCLRM instruction.
1165         (print_insn_coprocessor): Handle new %C format control code.
1166
1167 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1168
1169         * arm-dis.c (enum isa): New enum.
1170         (struct sopcode32): New structure.
1171         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1172         set isa field of all current entries to ANY.
1173         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1174         Only match an entry if its isa field allows the current mode.
1175
1176 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1177
1178         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1179         CLRM.
1180         (print_insn_thumb32): Add logic to print %n CLRM register list.
1181
1182 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1183
1184         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1185         and %Q patterns.
1186
1187 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1188
1189         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1190         (print_insn_thumb32): Edit the switch case for %Z.
1191
1192 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1193
1194         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1195
1196 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1197
1198         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1199
1200 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1201
1202         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1203
1204 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1205
1206         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1207         Arm register with r13 and r15 unpredictable.
1208         (thumb32_opcodes): New instructions for bfx and bflx.
1209
1210 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1211
1212         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1213
1214 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1215
1216         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1217
1218 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1219
1220         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1221
1222 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1223
1224         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1225
1226 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1227
1228         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1229         "optr". ("operator" is a reserved word in c++).
1230
1231 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1232
1233         * aarch64-opc.c (aarch64_print_operand): Add case for
1234         AARCH64_OPND_Rt_SP.
1235         (verify_constraints): Likewise.
1236         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1237         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1238         to accept Rt|SP as first operand.
1239         (AARCH64_OPERANDS): Add new Rt_SP.
1240         * aarch64-asm-2.c: Regenerated.
1241         * aarch64-dis-2.c: Regenerated.
1242         * aarch64-opc-2.c: Regenerated.
1243
1244 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1245
1246         * aarch64-asm-2.c: Regenerated.
1247         * aarch64-dis-2.c: Likewise.
1248         * aarch64-opc-2.c: Likewise.
1249         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1250
1251 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1252
1253         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1254
1255 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1256
1257         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1258         * i386-init.h: Regenerated.
1259
1260 2019-04-07  Alan Modra  <amodra@gmail.com>
1261
1262         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1263         op_separator to control printing of spaces, comma and parens
1264         rather than need_comma, need_paren and spaces vars.
1265
1266 2019-04-07  Alan Modra  <amodra@gmail.com>
1267
1268         PR 24421
1269         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1270         (print_insn_neon, print_insn_arm): Likewise.
1271
1272 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1273
1274         * i386-dis-evex.h (evex_table): Updated to support BF16
1275         instructions.
1276         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1277         and EVEX_W_0F3872_P_3.
1278         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1279         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1280         * i386-opc.h (enum): Add CpuAVX512_BF16.
1281         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1282         * i386-opc.tbl: Add AVX512 BF16 instructions.
1283         * i386-init.h: Regenerated.
1284         * i386-tbl.h: Likewise.
1285
1286 2019-04-05  Alan Modra  <amodra@gmail.com>
1287
1288         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1289         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1290         to favour printing of "-" branch hint when using the "y" bit.
1291         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1292
1293 2019-04-05  Alan Modra  <amodra@gmail.com>
1294
1295         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1296         opcode until first operand is output.
1297
1298 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1299
1300         PR gas/24349
1301         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1302         (valid_bo_post_v2): Add support for 'at' branch hints.
1303         (insert_bo): Only error on branch on ctr.
1304         (get_bo_hint_mask): New function.
1305         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1306         for inserting 'at' branch hints.
1307         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1308         for extracting 'at' branch hints.
1309         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1310         (BOE): Delete operand.
1311         (BOM, BOP): New operands.
1312         (RM): Update value.
1313         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1314         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1315         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1316         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1317         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1318         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1319         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1320         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1321         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1322         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1323         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1324         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1325         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1326         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1327         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1328         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1329         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1330         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1331         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1332         bttarl+>: New extended mnemonics.
1333
1334 2019-03-28  Alan Modra  <amodra@gmail.com>
1335
1336         PR 24390
1337         * ppc-opc.c (BTF): Define.
1338         (powerpc_opcodes): Use for mtfsb*.
1339         * ppc-dis.c (print_insn_powerpc): Print fields with both
1340         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1341
1342 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1343
1344         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1345         (mapping_symbol_for_insn): Implement new algorithm.
1346         (print_insn): Remove duplicate code.
1347
1348 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1349
1350         * aarch64-dis.c (print_insn_aarch64):
1351         Implement override.
1352
1353 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1354
1355         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1356         order.
1357
1358 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1359
1360         * aarch64-dis.c (last_stop_offset): New.
1361         (print_insn_aarch64): Use stop_offset.
1362
1363 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1364
1365         PR gas/24359
1366         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1367         CPU_ANY_AVX2_FLAGS.
1368         * i386-init.h: Regenerated.
1369
1370 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1371
1372         PR gas/24348
1373         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1374         vmovdqu16, vmovdqu32 and vmovdqu64.
1375         * i386-tbl.h: Regenerated.
1376
1377 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1378
1379         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1380         from vstrszb, vstrszh, and vstrszf.
1381
1382 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1383
1384         * s390-opc.txt: Add instruction descriptions.
1385
1386 2019-02-08  Jim Wilson  <jimw@sifive.com>
1387
1388         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1389         <bne>: Likewise.
1390
1391 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1392
1393         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1394
1395 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1396
1397         PR binutils/23212
1398         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1399         * aarch64-opc.c (verify_elem_sd): New.
1400         (fields): Add FLD_sz entr.
1401         * aarch64-tbl.h (_SIMD_INSN): New.
1402         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1403         fmulx scalar and vector by element isns.
1404
1405 2019-02-07  Nick Clifton  <nickc@redhat.com>
1406
1407         * po/sv.po: Updated Swedish translation.
1408
1409 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1410
1411         * s390-mkopc.c (main): Accept arch13 as cpu string.
1412         * s390-opc.c: Add new instruction formats and instruction opcode
1413         masks.
1414         * s390-opc.txt: Add new arch13 instructions.
1415
1416 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1417
1418         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1419         (aarch64_opcode): Change encoding for stg, stzg
1420         st2g and st2zg.
1421         * aarch64-asm-2.c: Regenerated.
1422         * aarch64-dis-2.c: Regenerated.
1423         * aarch64-opc-2.c: Regenerated.
1424
1425 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1426
1427         * aarch64-asm-2.c: Regenerated.
1428         * aarch64-dis-2.c: Likewise.
1429         * aarch64-opc-2.c: Likewise.
1430         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1431
1432 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1433             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1434
1435         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1436         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1437         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1438         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1439         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1440         case for ldstgv_indexed.
1441         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1442         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1443         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1444         * aarch64-asm-2.c: Regenerated.
1445         * aarch64-dis-2.c: Regenerated.
1446         * aarch64-opc-2.c: Regenerated.
1447
1448 2019-01-23  Nick Clifton  <nickc@redhat.com>
1449
1450         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1451
1452 2019-01-21  Nick Clifton  <nickc@redhat.com>
1453
1454         * po/de.po: Updated German translation.
1455         * po/uk.po: Updated Ukranian translation.
1456
1457 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1458         * mips-dis.c (mips_arch_choices): Fix typo in
1459         gs464, gs464e and gs264e descriptors.
1460
1461 2019-01-19  Nick Clifton  <nickc@redhat.com>
1462
1463         * configure: Regenerate.
1464         * po/opcodes.pot: Regenerate.
1465
1466 2018-06-24  Nick Clifton  <nickc@redhat.com>
1467
1468         2.32 branch created.
1469
1470 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1471
1472         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1473         if it is null.
1474         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1475         zero.
1476
1477 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1478
1479         * configure: Regenerate.
1480
1481 2019-01-07  Alan Modra  <amodra@gmail.com>
1482
1483         * configure: Regenerate.
1484         * po/POTFILES.in: Regenerate.
1485
1486 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1487
1488         * s12z-opc.c: New file.
1489         * s12z-opc.h: New file.
1490         * s12z-dis.c: Removed all code not directly related to display
1491         of instructions.  Used the interface provided by the new files
1492         instead.
1493         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1494         * Makefile.in: Regenerate.
1495         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1496         * configure: Regenerate.
1497
1498 2019-01-01  Alan Modra  <amodra@gmail.com>
1499
1500         Update year range in copyright notice of all files.
1501
1502 For older changes see ChangeLog-2018
1503 \f
1504 Copyright (C) 2019 Free Software Foundation, Inc.
1505
1506 Copying and distribution of this file, with or without modification,
1507 are permitted in any medium without royalty provided the copyright
1508 notice and this notice are preserved.
1509
1510 Local Variables:
1511 mode: change-log
1512 left-margin: 8
1513 fill-column: 74
1514 version-control: never
1515 End: