opcodes/ChangeLog

   1 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         PR binutils/24700
   4         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
   5         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
   6         EVEX_W_0F385B_P_2.
   7         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
   8         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
   9         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
  10         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
  11         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
  12         EVEX_LEN_0F385B_P_2_W_1.
  13         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
  14         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
  15         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
  16         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
  17         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
  18         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
  19         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
  20         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
  21         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
  22         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
  23
  24 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
  25
  26         PR binutils/24691
  27         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
  28         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
  29         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
  30         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
  31         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
  32         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
  33         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
  34         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
  35         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
  36         EVEX_LEN_0F3A43_P_2_W_1.
  37         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
  38         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
  39         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
  40         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
  41         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
  42         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
  43         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
  44         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
  45         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
  46         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
  47         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
  48         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
  49
  50 2019-06-14  Nick Clifton  <nickc@redhat.com>
  51
  52         * po/fr.po; Updated French translation.
  53
  54 2019-06-13  Stafford Horne  <shorne@gmail.com>
  55
  56         * or1k-asm.c: Regenerated.
  57         * or1k-desc.c: Regenerated.
  58         * or1k-desc.h: Regenerated.
  59         * or1k-dis.c: Regenerated.
  60         * or1k-ibld.c: Regenerated.
  61         * or1k-opc.c: Regenerated.
  62         * or1k-opc.h: Regenerated.
  63         * or1k-opinst.c: Regenerated.
  64
  65 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
  66
  67         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
  68
  69 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
  70
  71         PR binutils/24633
  72         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
  73         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
  74         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
  75         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
  76         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
  77         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
  78         EVEX_LEN_0F3A1B_P_2_W_1.
  79         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
  80         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
  81         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
  82         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
  83         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
  84         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
  85         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
  86         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
  87
  88 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
  89
  90         PR binutils/24626
  91         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
  92         EVEX.vvvv when disassembling VEX and EVEX instructions.
  93         (OP_VEX): Set vex.register_specifier to 0 after readding
  94         vex.register_specifier.
  95         (OP_Vex_2src_1): Likewise.
  96         (OP_Vex_2src_2): Likewise.
  97         (OP_LWP_E): Likewise.
  98         (OP_EX_Vex): Don't check vex.register_specifier.
  99         (OP_XMM_Vex): Likewise.
 100
 101 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 102             Lili Cui  <lili.cui@intel.com>
 103
 104         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 105         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 106         instructions.
 107         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 108         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 109         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 110         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 111         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 112         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 113         * i386-init.h: Regenerated.
 114         * i386-tbl.h: Likewise.
 115
 116 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 117             Lili Cui  <lili.cui@intel.com>
 118
 119         * doc/c-i386.texi: Document enqcmd.
 120         * testsuite/gas/i386/enqcmd-intel.d: New file.
 121         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 122         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 123         * testsuite/gas/i386/enqcmd.d: Likewise.
 124         * testsuite/gas/i386/enqcmd.s: Likewise.
 125         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 126         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 127         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 128         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 129         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 130         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 131         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 132         and x86-64-enqcmd.
 133
 134 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 135
 136         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 137
 138 2019-06-03  Alan Modra  <amodra@gmail.com>
 139
 140         * ppc-dis.c (prefix_opcd_indices): Correct size.
 141
 142 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 143
 144         PR gas/24625
 145         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 146         Disp8ShiftVL.
 147         * i386-tbl.h: Regenerated.
 148
 149 2019-05-24  Alan Modra  <amodra@gmail.com>
 150
 151         * po/POTFILES.in: Regenerate.
 152
 153 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 154             Alan Modra  <amodra@gmail.com>
 155
 156         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 157         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 158         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 159         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 160         XTOP>): Define and add entries.
 161         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 162         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 163         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 164         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 165
 166 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 167             Alan Modra  <amodra@gmail.com>
 168
 169         * ppc-dis.c (ppc_opts): Add "future" entry.
 170         (PREFIX_OPCD_SEGS): Define.
 171         (prefix_opcd_indices): New array.
 172         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 173         (lookup_prefix): New function.
 174         (print_insn_powerpc): Handle 64-bit prefix instructions.
 175         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 176         (PMRR, POWERXX): Define.
 177         (prefix_opcodes): New instruction table.
 178         (prefix_num_opcodes): New constant.
 179
 180 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 181
 182         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 183         * configure: Regenerated.
 184         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 185         and cpu/bpf.opc.
 186         (HFILES): Add bpf-desc.h and bpf-opc.h.
 187         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 188         bpf-ibld.c and bpf-opc.c.
 189         (BPF_DEPS): Define.
 190         * Makefile.in: Regenerated.
 191         * disassemble.c (ARCH_bpf): Define.
 192         (disassembler): Add case for bfd_arch_bpf.
 193         (disassemble_init_for_target): Likewise.
 194         (enum epbf_isa_attr): Define.
 195         * disassemble.h: extern print_insn_bpf.
 196         * bpf-asm.c: Generated.
 197         * bpf-opc.h: Likewise.
 198         * bpf-opc.c: Likewise.
 199         * bpf-ibld.c: Likewise.
 200         * bpf-dis.c: Likewise.
 201         * bpf-desc.h: Likewise.
 202         * bpf-desc.c: Likewise.
 203
 204 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 205
 206         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 207         and VMSR with the new operands.
 208
 209 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 210
 211         * arm-dis.c (enum mve_instructions): New enum
 212         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 213         and cneg.
 214         (mve_opcodes): New instructions as above.
 215         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 216         csneg and csel.
 217         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 218
 219 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 220
 221         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 222         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 223         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 224         uqshl, urshrl and urshr.
 225         (is_mve_okay_in_it): Add new instructions to TRUE list.
 226         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 227         (print_insn_mve): Updated to accept new %j,
 228         %<bitfield>m and %<bitfield>n patterns.
 229
 230 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 231
 232         * mips-opc.c (mips_builtin_opcodes): Change source register
 233         constraint for DAUI.
 234
 235 2019-05-20  Nick Clifton  <nickc@redhat.com>
 236
 237         * po/fr.po: Updated French translation.
 238
 239 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 240             Michael Collison <michael.collison@arm.com>
 241
 242         * arm-dis.c (thumb32_opcodes): Add new instructions.
 243         (enum mve_instructions): Likewise.
 244         (enum mve_undefined): Add new reasons.
 245         (is_mve_encoding_conflict): Handle new instructions.
 246         (is_mve_undefined): Likewise.
 247         (is_mve_unpredictable): Likewise.
 248         (print_mve_undefined): Likewise.
 249         (print_mve_size): Likewise.
 250
 251 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 252             Michael Collison <michael.collison@arm.com>
 253
 254         * arm-dis.c (thumb32_opcodes): Add new instructions.
 255         (enum mve_instructions): Likewise.
 256         (is_mve_encoding_conflict): Handle new instructions.
 257         (is_mve_undefined): Likewise.
 258         (is_mve_unpredictable): Likewise.
 259         (print_mve_size): Likewise.
 260
 261 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 262             Michael Collison <michael.collison@arm.com>
 263
 264         * arm-dis.c (thumb32_opcodes): Add new instructions.
 265         (enum mve_instructions): Likewise.
 266         (is_mve_encoding_conflict): Likewise.
 267         (is_mve_unpredictable): Likewise.
 268         (print_mve_size): Likewise.
 269
 270 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 271             Michael Collison <michael.collison@arm.com>
 272
 273         * arm-dis.c (thumb32_opcodes): Add new instructions.
 274         (enum mve_instructions): Likewise.
 275         (is_mve_encoding_conflict): Handle new instructions.
 276         (is_mve_undefined): Likewise.
 277         (is_mve_unpredictable): Likewise.
 278         (print_mve_size): Likewise.
 279
 280 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 281             Michael Collison <michael.collison@arm.com>
 282
 283         * arm-dis.c (thumb32_opcodes): Add new instructions.
 284         (enum mve_instructions): Likewise.
 285         (is_mve_encoding_conflict): Handle new instructions.
 286         (is_mve_undefined): Likewise.
 287         (is_mve_unpredictable): Likewise.
 288         (print_mve_size): Likewise.
 289         (print_insn_mve): Likewise.
 290
 291 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 292             Michael Collison <michael.collison@arm.com>
 293
 294         * arm-dis.c (thumb32_opcodes): Add new instructions.
 295         (print_insn_thumb32): Handle new instructions.
 296
 297 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 298             Michael Collison <michael.collison@arm.com>
 299
 300         * arm-dis.c (enum mve_instructions): Add new instructions.
 301         (enum mve_undefined): Add new reasons.
 302         (is_mve_encoding_conflict): Handle new instructions.
 303         (is_mve_undefined): Likewise.
 304         (is_mve_unpredictable): Likewise.
 305         (print_mve_undefined): Likewise.
 306         (print_mve_size): Likewise.
 307         (print_mve_shift_n): Likewise.
 308         (print_insn_mve): Likewise.
 309
 310 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 311             Michael Collison <michael.collison@arm.com>
 312
 313         * arm-dis.c (enum mve_instructions): Add new instructions.
 314         (is_mve_encoding_conflict): Handle new instructions.
 315         (is_mve_unpredictable): Likewise.
 316         (print_mve_rotate): Likewise.
 317         (print_mve_size): Likewise.
 318         (print_insn_mve): Likewise.
 319
 320 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 321             Michael Collison <michael.collison@arm.com>
 322
 323         * arm-dis.c (enum mve_instructions): Add new instructions.
 324         (is_mve_encoding_conflict): Handle new instructions.
 325         (is_mve_unpredictable): Likewise.
 326         (print_mve_size): Likewise.
 327         (print_insn_mve): Likewise.
 328
 329 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 330             Michael Collison <michael.collison@arm.com>
 331
 332         * arm-dis.c (enum mve_instructions): Add new instructions.
 333         (enum mve_undefined): Add new reasons.
 334         (is_mve_encoding_conflict): Handle new instructions.
 335         (is_mve_undefined): Likewise.
 336         (is_mve_unpredictable): Likewise.
 337         (print_mve_undefined): Likewise.
 338         (print_mve_size): Likewise.
 339         (print_insn_mve): Likewise.
 340
 341 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 342             Michael Collison <michael.collison@arm.com>
 343
 344         * arm-dis.c (enum mve_instructions): Add new instructions.
 345         (is_mve_encoding_conflict): Handle new instructions.
 346         (is_mve_undefined): Likewise.
 347         (is_mve_unpredictable): Likewise.
 348         (print_mve_size): Likewise.
 349         (print_insn_mve): Likewise.
 350
 351 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 352             Michael Collison <michael.collison@arm.com>
 353
 354         * arm-dis.c (enum mve_instructions): Add new instructions.
 355         (enum mve_unpredictable): Add new reasons.
 356         (enum mve_undefined): Likewise.
 357         (is_mve_okay_in_it): Handle new isntructions.
 358         (is_mve_encoding_conflict): Likewise.
 359         (is_mve_undefined): Likewise.
 360         (is_mve_unpredictable): Likewise.
 361         (print_mve_vmov_index): Likewise.
 362         (print_simd_imm8): Likewise.
 363         (print_mve_undefined): Likewise.
 364         (print_mve_unpredictable): Likewise.
 365         (print_mve_size): Likewise.
 366         (print_insn_mve): Likewise.
 367
 368 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 369             Michael Collison <michael.collison@arm.com>
 370
 371         * arm-dis.c (enum mve_instructions): Add new instructions.
 372         (enum mve_unpredictable): Add new reasons.
 373         (enum mve_undefined): Likewise.
 374         (is_mve_encoding_conflict): Handle new instructions.
 375         (is_mve_undefined): Likewise.
 376         (is_mve_unpredictable): Likewise.
 377         (print_mve_undefined): Likewise.
 378         (print_mve_unpredictable): Likewise.
 379         (print_mve_rounding_mode): Likewise.
 380         (print_mve_vcvt_size): Likewise.
 381         (print_mve_size): Likewise.
 382         (print_insn_mve): Likewise.
 383
 384 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 385             Michael Collison <michael.collison@arm.com>
 386
 387         * arm-dis.c (enum mve_instructions): Add new instructions.
 388         (enum mve_unpredictable): Add new reasons.
 389         (enum mve_undefined): Likewise.
 390         (is_mve_undefined): Handle new instructions.
 391         (is_mve_unpredictable): Likewise.
 392         (print_mve_undefined): Likewise.
 393         (print_mve_unpredictable): Likewise.
 394         (print_mve_size): Likewise.
 395         (print_insn_mve): Likewise.
 396
 397 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 398             Michael Collison <michael.collison@arm.com>
 399
 400         * arm-dis.c (enum mve_instructions): Add new instructions.
 401         (enum mve_undefined): Add new reasons.
 402         (insns): Add new instructions.
 403         (is_mve_encoding_conflict):
 404         (print_mve_vld_str_addr): New print function.
 405         (is_mve_undefined): Handle new instructions.
 406         (is_mve_unpredictable): Likewise.
 407         (print_mve_undefined): Likewise.
 408         (print_mve_size): Likewise.
 409         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 410         (print_insn_mve):  Handle new operands.
 411
 412 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 413             Michael Collison <michael.collison@arm.com>
 414
 415         * arm-dis.c (enum mve_instructions): Add new instructions.
 416         (enum mve_unpredictable): Add new reasons.
 417         (is_mve_encoding_conflict): Handle new instructions.
 418         (is_mve_unpredictable): Likewise.
 419         (mve_opcodes): Add new instructions.
 420         (print_mve_unpredictable): Handle new reasons.
 421         (print_mve_register_blocks): New print function.
 422         (print_mve_size): Handle new instructions.
 423         (print_insn_mve): Likewise.
 424
 425 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 426             Michael Collison <michael.collison@arm.com>
 427
 428         * arm-dis.c (enum mve_instructions): Add new instructions.
 429         (enum mve_unpredictable): Add new reasons.
 430         (enum mve_undefined): Likewise.
 431         (is_mve_encoding_conflict): Handle new instructions.
 432         (is_mve_undefined): Likewise.
 433         (is_mve_unpredictable): Likewise.
 434         (coprocessor_opcodes): Move NEON VDUP from here...
 435         (neon_opcodes): ... to here.
 436         (mve_opcodes): Add new instructions.
 437         (print_mve_undefined):  Handle new reasons.
 438         (print_mve_unpredictable): Likewise.
 439         (print_mve_size): Handle new instructions.
 440         (print_insn_neon): Handle vdup.
 441         (print_insn_mve): Handle new operands.
 442
 443 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 444             Michael Collison <michael.collison@arm.com>
 445
 446         * arm-dis.c (enum mve_instructions): Add new instructions.
 447         (enum mve_unpredictable): Add new values.
 448         (mve_opcodes): Add new instructions.
 449         (vec_condnames): New array with vector conditions.
 450         (mve_predicatenames): New array with predicate suffixes.
 451         (mve_vec_sizename): New array with vector sizes.
 452         (enum vpt_pred_state): New enum with vector predication states.
 453         (struct vpt_block): New struct type for vpt blocks.
 454         (vpt_block_state): Global struct to keep track of state.
 455         (mve_extract_pred_mask): New helper function.
 456         (num_instructions_vpt_block): Likewise.
 457         (mark_outside_vpt_block): Likewise.
 458         (mark_inside_vpt_block): Likewise.
 459         (invert_next_predicate_state): Likewise.
 460         (update_next_predicate_state): Likewise.
 461         (update_vpt_block_state): Likewise.
 462         (is_vpt_instruction): Likewise.
 463         (is_mve_encoding_conflict): Add entries for new instructions.
 464         (is_mve_unpredictable): Likewise.
 465         (print_mve_unpredictable): Handle new cases.
 466         (print_instruction_predicate): Likewise.
 467         (print_mve_size): New function.
 468         (print_vec_condition): New function.
 469         (print_insn_mve): Handle vpt blocks and new print operands.
 470
 471 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 472
 473         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 474         8, 14 and 15 for Armv8.1-M Mainline.
 475
 476 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 477             Michael Collison <michael.collison@arm.com>
 478
 479         * arm-dis.c (enum mve_instructions): New enum.
 480         (enum mve_unpredictable): Likewise.
 481         (enum mve_undefined): Likewise.
 482         (struct mopcode32): New struct.
 483         (is_mve_okay_in_it): New function.
 484         (is_mve_architecture): Likewise.
 485         (arm_decode_field): Likewise.
 486         (arm_decode_field_multiple): Likewise.
 487         (is_mve_encoding_conflict): Likewise.
 488         (is_mve_undefined): Likewise.
 489         (is_mve_unpredictable): Likewise.
 490         (print_mve_undefined): Likewise.
 491         (print_mve_unpredictable): Likewise.
 492         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 493         (print_insn_mve): New function.
 494         (print_insn_thumb32): Handle MVE architecture.
 495         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 496
 497 2019-05-10  Nick Clifton  <nickc@redhat.com>
 498
 499         PR 24538
 500         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 501         end of the table prematurely.
 502
 503 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 504
 505         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 506         macros for R6.
 507
 508 2019-05-11  Alan Modra  <amodra@gmail.com>
 509
 510         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 511         when -Mraw is in effect.
 512
 513 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 514
 515         * aarch64-dis-2.c: Regenerate.
 516         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 517         (OP_SVE_BBB): New variant set.
 518         (OP_SVE_DDDD): New variant set.
 519         (OP_SVE_HHH): New variant set.
 520         (OP_SVE_HHHU): New variant set.
 521         (OP_SVE_SSS): New variant set.
 522         (OP_SVE_SSSU): New variant set.
 523         (OP_SVE_SHH): New variant set.
 524         (OP_SVE_SBBU): New variant set.
 525         (OP_SVE_DSS): New variant set.
 526         (OP_SVE_DHHU): New variant set.
 527         (OP_SVE_VMV_HSD_BHS): New variant set.
 528         (OP_SVE_VVU_HSD_BHS): New variant set.
 529         (OP_SVE_VVVU_SD_BH): New variant set.
 530         (OP_SVE_VVVU_BHSD): New variant set.
 531         (OP_SVE_VVV_QHD_DBS): New variant set.
 532         (OP_SVE_VVV_HSD_BHS): New variant set.
 533         (OP_SVE_VVV_HSD_BHS2): New variant set.
 534         (OP_SVE_VVV_BHS_HSD): New variant set.
 535         (OP_SVE_VV_BHS_HSD): New variant set.
 536         (OP_SVE_VVV_SD): New variant set.
 537         (OP_SVE_VVU_BHS_HSD): New variant set.
 538         (OP_SVE_VZVV_SD): New variant set.
 539         (OP_SVE_VZVV_BH): New variant set.
 540         (OP_SVE_VZV_SD): New variant set.
 541         (aarch64_opcode_table): Add sve2 instructions.
 542
 543 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 544
 545         * aarch64-asm-2.c: Regenerated.
 546         * aarch64-dis-2.c: Regenerated.
 547         * aarch64-opc-2.c: Regenerated.
 548         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 549         for SVE_SHLIMM_UNPRED_22.
 550         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 551         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 552         operand.
 553
 554 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 555
 556         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 557         sve_size_tsz_bhs iclass encode.
 558         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 559         sve_size_tsz_bhs iclass decode.
 560
 561 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 562
 563         * aarch64-asm-2.c: Regenerated.
 564         * aarch64-dis-2.c: Regenerated.
 565         * aarch64-opc-2.c: Regenerated.
 566         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 567         for SVE_Zm4_11_INDEX.
 568         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 569         (fields): Handle SVE_i2h field.
 570         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 571         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 572
 573 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 574
 575         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 576         sve_shift_tsz_bhsd iclass encode.
 577         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 578         sve_shift_tsz_bhsd iclass decode.
 579
 580 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 581
 582         * aarch64-asm-2.c: Regenerated.
 583         * aarch64-dis-2.c: Regenerated.
 584         * aarch64-opc-2.c: Regenerated.
 585         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 586         (aarch64_encode_variant_using_iclass): Handle
 587         sve_shift_tsz_hsd iclass encode.
 588         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 589         sve_shift_tsz_hsd iclass decode.
 590         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 591         for SVE_SHRIMM_UNPRED_22.
 592         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 593         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 594         operand.
 595
 596 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 597
 598         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 599         sve_size_013 iclass encode.
 600         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 601         sve_size_013 iclass decode.
 602
 603 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 604
 605         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 606         sve_size_bh iclass encode.
 607         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 608         sve_size_bh iclass decode.
 609
 610 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 611
 612         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 613         sve_size_sd2 iclass encode.
 614         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 615         sve_size_sd2 iclass decode.
 616         * aarch64-opc.c (fields): Handle SVE_sz2 field.
 617         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
 618
 619 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 620
 621         * aarch64-asm-2.c: Regenerated.
 622         * aarch64-dis-2.c: Regenerated.
 623         * aarch64-opc-2.c: Regenerated.
 624         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 625         for SVE_ADDR_ZX.
 626         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
 627         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
 628
 629 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 630
 631         * aarch64-asm-2.c: Regenerated.
 632         * aarch64-dis-2.c: Regenerated.
 633         * aarch64-opc-2.c: Regenerated.
 634         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 635         for SVE_Zm3_11_INDEX.
 636         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
 637         (fields): Handle SVE_i3l and SVE_i3h2 fields.
 638         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
 639         fields.
 640         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
 641
 642 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 643
 644         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 645         sve_size_hsd2 iclass encode.
 646         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 647         sve_size_hsd2 iclass decode.
 648         * aarch64-opc.c (fields): Handle SVE_size field.
 649         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
 650
 651 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 652
 653         * aarch64-asm-2.c: Regenerated.
 654         * aarch64-dis-2.c: Regenerated.
 655         * aarch64-opc-2.c: Regenerated.
 656         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 657         for SVE_IMM_ROT3.
 658         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
 659         (fields): Handle SVE_rot3 field.
 660         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
 661         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
 662
 663 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 664
 665         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
 666         instructions.
 667
 668 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 669
 670         * aarch64-tbl.h
 671         (aarch64_feature_sve2, aarch64_feature_sve2aes,
 672         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
 673         aarch64_feature_sve2bitperm): New feature sets.
 674         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
 675         for feature set addresses.
 676         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
 677         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
 678
 679 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
 680             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 681
 682         * mips-dis.c (mips_calculate_combination_ases): Add ISA
 683         argument and set ASE_EVA_R6 appropriately.
 684         (set_default_mips_dis_options): Pass ISA to above.
 685         (parse_mips_dis_option): Likewise.
 686         * mips-opc.c (EVAR6): New macro.
 687         (mips_builtin_opcodes): Add llwpe, scwpe.
 688
 689 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
 690
 691         * aarch64-asm-2.c: Regenerated.
 692         * aarch64-dis-2.c: Regenerated.
 693         * aarch64-opc-2.c: Regenerated.
 694         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
 695         AARCH64_OPND_TME_UIMM16.
 696         (aarch64_print_operand): Likewise.
 697         * aarch64-tbl.h (QL_IMM_NIL): New.
 698         (TME): New.
 699         (_TME_INSN): New.
 700         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
 701
 702 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
 703
 704         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
 705
 706 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
 707             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 708
 709         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
 710
 711 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 712
 713         * s12z-opc.h: Add extern "C" bracketing to help
 714         users who wish to use this interface in c++ code.
 715
 716 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 717
 718         * s12z-opc.c (bm_decode): Handle bit map operations with the
 719         "reserved0" mode.
 720
 721 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 722
 723         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
 724         specifier.  Add entries for VLDR and VSTR of system registers.
 725         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
 726         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
 727         of %J and %K format specifier.
 728
 729 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 730
 731         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
 732         Add new entries for VSCCLRM instruction.
 733         (print_insn_coprocessor): Handle new %C format control code.
 734
 735 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 736
 737         * arm-dis.c (enum isa): New enum.
 738         (struct sopcode32): New structure.
 739         (coprocessor_opcodes): change type of entries to struct sopcode32 and
 740         set isa field of all current entries to ANY.
 741         (print_insn_coprocessor): Change type of insn to struct sopcode32.
 742         Only match an entry if its isa field allows the current mode.
 743
 744 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 745
 746         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
 747         CLRM.
 748         (print_insn_thumb32): Add logic to print %n CLRM register list.
 749
 750 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 751
 752         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
 753         and %Q patterns.
 754
 755 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 756
 757         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
 758         (print_insn_thumb32): Edit the switch case for %Z.
 759
 760 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 761
 762         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
 763
 764 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 765
 766         * arm-dis.c (thumb32_opcodes): New instruction bfl.
 767
 768 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 769
 770         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
 771
 772 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 773
 774         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
 775         Arm register with r13 and r15 unpredictable.
 776         (thumb32_opcodes): New instructions for bfx and bflx.
 777
 778 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 779
 780         * arm-dis.c (thumb32_opcodes): New instructions for bf.
 781
 782 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 783
 784         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
 785
 786 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 787
 788         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
 789
 790 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 791
 792         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
 793
 794 2019-04-12  John Darrington <john@darrington.wattle.id.au>
 795
 796         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
 797         "optr". ("operator" is a reserved word in c++).
 798
 799 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 800
 801         * aarch64-opc.c (aarch64_print_operand): Add case for
 802         AARCH64_OPND_Rt_SP.
 803         (verify_constraints): Likewise.
 804         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
 805         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
 806         to accept Rt|SP as first operand.
 807         (AARCH64_OPERANDS): Add new Rt_SP.
 808         * aarch64-asm-2.c: Regenerated.
 809         * aarch64-dis-2.c: Regenerated.
 810         * aarch64-opc-2.c: Regenerated.
 811
 812 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 813
 814         * aarch64-asm-2.c: Regenerated.
 815         * aarch64-dis-2.c: Likewise.
 816         * aarch64-opc-2.c: Likewise.
 817         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
 818
 819 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
 820
 821         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
 822
 823 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
 824
 825         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
 826         * i386-init.h: Regenerated.
 827
 828 2019-04-07  Alan Modra  <amodra@gmail.com>
 829
 830         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
 831         op_separator to control printing of spaces, comma and parens
 832         rather than need_comma, need_paren and spaces vars.
 833
 834 2019-04-07  Alan Modra  <amodra@gmail.com>
 835
 836         PR 24421
 837         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
 838         (print_insn_neon, print_insn_arm): Likewise.
 839
 840 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
 841
 842         * i386-dis-evex.h (evex_table): Updated to support BF16
 843         instructions.
 844         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
 845         and EVEX_W_0F3872_P_3.
 846         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
 847         (cpu_flags): Add bitfield for CpuAVX512_BF16.
 848         * i386-opc.h (enum): Add CpuAVX512_BF16.
 849         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
 850         * i386-opc.tbl: Add AVX512 BF16 instructions.
 851         * i386-init.h: Regenerated.
 852         * i386-tbl.h: Likewise.
 853
 854 2019-04-05  Alan Modra  <amodra@gmail.com>
 855
 856         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
 857         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
 858         to favour printing of "-" branch hint when using the "y" bit.
 859         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
 860
 861 2019-04-05  Alan Modra  <amodra@gmail.com>
 862
 863         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
 864         opcode until first operand is output.
 865
 866 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
 867
 868         PR gas/24349
 869         * ppc-opc.c (valid_bo_pre_v2): Add comments.
 870         (valid_bo_post_v2): Add support for 'at' branch hints.
 871         (insert_bo): Only error on branch on ctr.
 872         (get_bo_hint_mask): New function.
 873         (insert_boe): Add new 'branch_taken' formal argument.  Add support
 874         for inserting 'at' branch hints.
 875         (extract_boe): Add new 'branch_taken' formal argument.  Add support
 876         for extracting 'at' branch hints.
 877         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
 878         (BOE): Delete operand.
 879         (BOM, BOP): New operands.
 880         (RM): Update value.
 881         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
 882         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
 883         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
 884         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
 885         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
 886         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
 887         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
 888         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
 889         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
 890         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
 891         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
 892         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
 893         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
 894         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
 895         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
 896         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
 897         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
 898         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
 899         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
 900         bttarl+>: New extended mnemonics.
 901
 902 2019-03-28  Alan Modra  <amodra@gmail.com>
 903
 904         PR 24390
 905         * ppc-opc.c (BTF): Define.
 906         (powerpc_opcodes): Use for mtfsb*.
 907         * ppc-dis.c (print_insn_powerpc): Print fields with both
 908         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
 909
 910 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 911
 912         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
 913         (mapping_symbol_for_insn): Implement new algorithm.
 914         (print_insn): Remove duplicate code.
 915
 916 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 917
 918         * aarch64-dis.c (print_insn_aarch64):
 919         Implement override.
 920
 921 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 922
 923         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
 924         order.
 925
 926 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 927
 928         * aarch64-dis.c (last_stop_offset): New.
 929         (print_insn_aarch64): Use stop_offset.
 930
 931 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
 932
 933         PR gas/24359
 934         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
 935         CPU_ANY_AVX2_FLAGS.
 936         * i386-init.h: Regenerated.
 937
 938 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
 939
 940         PR gas/24348
 941         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
 942         vmovdqu16, vmovdqu32 and vmovdqu64.
 943         * i386-tbl.h: Regenerated.
 944
 945 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 946
 947         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
 948         from vstrszb, vstrszh, and vstrszf.
 949
 950 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 951
 952         * s390-opc.txt: Add instruction descriptions.
 953
 954 2019-02-08  Jim Wilson  <jimw@sifive.com>
 955
 956         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
 957         <bne>: Likewise.
 958
 959 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 960
 961         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
 962
 963 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 964
 965         PR binutils/23212
 966         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
 967         * aarch64-opc.c (verify_elem_sd): New.
 968         (fields): Add FLD_sz entr.
 969         * aarch64-tbl.h (_SIMD_INSN): New.
 970         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
 971         fmulx scalar and vector by element isns.
 972
 973 2019-02-07  Nick Clifton  <nickc@redhat.com>
 974
 975         * po/sv.po: Updated Swedish translation.
 976
 977 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
 978
 979         * s390-mkopc.c (main): Accept arch13 as cpu string.
 980         * s390-opc.c: Add new instruction formats and instruction opcode
 981         masks.
 982         * s390-opc.txt: Add new arch13 instructions.
 983
 984 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 985
 986         * aarch64-tbl.h (QL_LDST_AT): Update macro.
 987         (aarch64_opcode): Change encoding for stg, stzg
 988         st2g and st2zg.
 989         * aarch64-asm-2.c: Regenerated.
 990         * aarch64-dis-2.c: Regenerated.
 991         * aarch64-opc-2.c: Regenerated.
 992
 993 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 994
 995         * aarch64-asm-2.c: Regenerated.
 996         * aarch64-dis-2.c: Likewise.
 997         * aarch64-opc-2.c: Likewise.
 998         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
 999
1000 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1001             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1002
1003         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1004         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1005         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1006         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1007         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1008         case for ldstgv_indexed.
1009         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1010         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1011         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1012         * aarch64-asm-2.c: Regenerated.
1013         * aarch64-dis-2.c: Regenerated.
1014         * aarch64-opc-2.c: Regenerated.
1015
1016 2019-01-23  Nick Clifton  <nickc@redhat.com>
1017
1018         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1019
1020 2019-01-21  Nick Clifton  <nickc@redhat.com>
1021
1022         * po/de.po: Updated German translation.
1023         * po/uk.po: Updated Ukranian translation.
1024
1025 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1026         * mips-dis.c (mips_arch_choices): Fix typo in
1027         gs464, gs464e and gs264e descriptors.
1028
1029 2019-01-19  Nick Clifton  <nickc@redhat.com>
1030
1031         * configure: Regenerate.
1032         * po/opcodes.pot: Regenerate.
1033
1034 2018-06-24  Nick Clifton  <nickc@redhat.com>
1035
1036         2.32 branch created.
1037
1038 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1039
1040         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1041         if it is null.
1042         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1043         zero.
1044
1045 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1046
1047         * configure: Regenerate.
1048
1049 2019-01-07  Alan Modra  <amodra@gmail.com>
1050
1051         * configure: Regenerate.
1052         * po/POTFILES.in: Regenerate.
1053
1054 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1055
1056         * s12z-opc.c: New file.
1057         * s12z-opc.h: New file.
1058         * s12z-dis.c: Removed all code not directly related to display
1059         of instructions.  Used the interface provided by the new files
1060         instead.
1061         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1062         * Makefile.in: Regenerate.
1063         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1064         * configure: Regenerate.
1065
1066 2019-01-01  Alan Modra  <amodra@gmail.com>
1067
1068         Update year range in copyright notice of all files.
1069
1070 For older changes see ChangeLog-2018
1071 \f
1072 Copyright (C) 2019 Free Software Foundation, Inc.
1073
1074 Copying and distribution of this file, with or without modification,
1075 are permitted in any medium without royalty provided the copyright
1076 notice and this notice are preserved.
1077
1078 Local Variables:
1079 mode: change-log
1080 left-margin: 8
1081 fill-column: 74
1082 version-control: never
1083 End: