1 2019-12-11 Alan Modra <amodra@gmail.com>
3 * d30v-dis.c (print_insn): Make opind unsigned. Don't access
4 past end of operands array.
6 2019-12-11 Alan Modra <amodra@gmail.com>
8 * csky-dis.c (csky_chars_to_number): Rewrite. Avoid signed
9 overflow when collecting bytes of a number.
11 2019-12-11 Alan Modra <amodra@gmail.com>
13 * cris-dis.c (print_with_operands): Avoid signed integer
14 overflow when collecting bytes of a 32-bit integer.
16 2019-12-11 Alan Modra <amodra@gmail.com>
18 * cr16-dis.c (EXTRACT, SBM): Rewrite.
19 (cr16_match_opcode): Delete duplicate bcond test.
21 2019-12-11 Alan Modra <amodra@gmail.com>
23 * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
25 (MASKBITS, SIGNEXTEND): Rewrite.
26 (fmtconst): Don't use ? expression now that SIGNEXTEND uses
27 unsigned arithmetic, instead assign result of SIGNEXTEND back
29 (fmtconst_val): Use 1u in shift expression.
31 2019-12-11 Alan Modra <amodra@gmail.com>
33 * arc-dis.c (find_format_from_table): Use ull constant when
36 2019-12-11 Alan Modra <amodra@gmail.com>
39 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
40 false when field is zero for sve_size_tsz_bhs.
42 2019-12-11 Alan Modra <amodra@gmail.com>
44 * epiphany-ibld.c: Regenerate.
46 2019-12-10 Alan Modra <amodra@gmail.com>
49 * disassemble.c (disassemble_free_target): New function.
51 2019-12-10 Alan Modra <amodra@gmail.com>
53 * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
54 * disassemble.c (disassemble_init_for_target): Likewise.
55 * bpf-dis.c: Regenerate.
56 * epiphany-dis.c: Regenerate.
57 * fr30-dis.c: Regenerate.
58 * frv-dis.c: Regenerate.
59 * ip2k-dis.c: Regenerate.
60 * iq2000-dis.c: Regenerate.
61 * lm32-dis.c: Regenerate.
62 * m32c-dis.c: Regenerate.
63 * m32r-dis.c: Regenerate.
64 * mep-dis.c: Regenerate.
65 * mt-dis.c: Regenerate.
66 * or1k-dis.c: Regenerate.
67 * xc16x-dis.c: Regenerate.
68 * xstormy16-dis.c: Regenerate.
70 2019-12-10 Alan Modra <amodra@gmail.com>
72 * ppc-dis.c (private): Delete variable.
73 (get_powerpc_dialect): Don't segfault on NULL info->private_data.
74 (powerpc_init_dialect): Don't use global private.
76 2019-12-10 Alan Modra <amodra@gmail.com>
78 * s12z-opc.c: Formatting.
80 2019-12-08 Alan Modra <amodra@gmail.com>
82 * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
85 2019-12-05 Jan Beulich <jbeulich@suse.com>
87 * aarch64-tbl.h (aarch64_feature_crypto,
88 aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
89 CRYPTO_V8_2_INSN): Delete.
91 2019-12-05 Alan Modra <amodra@gmail.com>
94 * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
95 (struct string_buf): New.
96 (strbuf): New function.
97 (get_field): Use strbuf rather than strdup of local temp.
98 (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
99 (get_field_rfsl, get_field_imm15): Likewise.
100 (get_field_rd, get_field_r1, get_field_r2): Update macros.
101 (get_field_special): Likewise. Don't strcpy spr. Formatting.
102 (print_insn_microblaze): Formatting. Init and pass string_buf to
105 2019-12-04 Jan Beulich <jbeulich@suse.com>
107 * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
108 * i386-tbl.h: Re-generate.
110 2019-12-04 Jan Beulich <jbeulich@suse.com>
112 * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
114 2019-12-04 Jan Beulich <jbeulich@suse.com>
116 * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
118 (xbegin): Drop DefaultSize.
119 * i386-tbl.h: Re-generate.
121 2019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
123 * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
124 Change the coproc CRC conditions to use the extension
125 feature set, second word, base on ARM_EXT2_CRC.
127 2019-11-14 Jan Beulich <jbeulich@suse.com>
129 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
130 * i386-tbl.h: Re-generate.
132 2019-11-14 Jan Beulich <jbeulich@suse.com>
134 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
135 JumpInterSegment, and JumpAbsolute entries.
136 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
137 JUMP_ABSOLUTE): Define.
138 (struct i386_opcode_modifier): Extend jump field to 3 bits.
139 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
141 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
142 JumpInterSegment): Define.
143 * i386-tbl.h: Re-generate.
145 2019-11-14 Jan Beulich <jbeulich@suse.com>
147 * i386-gen.c (operand_type_init): Remove
148 OPERAND_TYPE_JUMPABSOLUTE entry.
149 (opcode_modifiers): Add JumpAbsolute entry.
150 (operand_types): Remove JumpAbsolute entry.
151 * i386-opc.h (JumpAbsolute): Move between enums.
152 (struct i386_opcode_modifier): Add jumpabsolute field.
153 (union i386_operand_type): Remove jumpabsolute field.
154 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
155 * i386-init.h, i386-tbl.h: Re-generate.
157 2019-11-14 Jan Beulich <jbeulich@suse.com>
159 * i386-gen.c (opcode_modifiers): Add AnySize entry.
160 (operand_types): Remove AnySize entry.
161 * i386-opc.h (AnySize): Move between enums.
162 (struct i386_opcode_modifier): Add anysize field.
163 (OTUnused): Un-comment.
164 (union i386_operand_type): Remove anysize field.
165 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
166 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
167 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
169 * i386-tbl.h: Re-generate.
171 2019-11-12 Nelson Chu <nelson.chu@sifive.com>
173 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
174 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
175 use the floating point register (FPR).
177 2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
179 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
181 (is_mve_encoding_conflict): Update cmode conflict checks for
184 2019-11-12 Jan Beulich <jbeulich@suse.com>
186 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
188 (operand_types): Remove EsSeg entry.
189 (main): Replace stale use of OTMax.
190 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
191 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
193 (OTUnused): Comment out.
194 (union i386_operand_type): Remove esseg field.
195 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
196 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
197 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
198 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
199 * i386-init.h, i386-tbl.h: Re-generate.
201 2019-11-12 Jan Beulich <jbeulich@suse.com>
203 * i386-gen.c (operand_instances): Add RegB entry.
204 * i386-opc.h (enum operand_instance): Add RegB.
205 * i386-opc.tbl (RegC, RegD, RegB): Define.
206 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
207 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
208 monitorx, mwaitx): Drop ImmExt and convert encodings
210 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
211 (edx, rdx): Add Instance=RegD.
212 (ebx, rbx): Add Instance=RegB.
213 * i386-tbl.h: Re-generate.
215 2019-11-12 Jan Beulich <jbeulich@suse.com>
217 * i386-gen.c (operand_type_init): Adjust
218 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
219 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
220 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
221 (operand_instances): New.
222 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
223 (output_operand_type): New parameter "instance". Process it.
224 (process_i386_operand_type): New local variable "instance".
225 (main): Adjust static assertions.
226 * i386-opc.h (INSTANCE_WIDTH): Define.
227 (enum operand_instance): New.
228 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
229 (union i386_operand_type): Replace acc, inoutportreg, and
230 shiftcount by instance.
231 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
232 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
234 * i386-init.h, i386-tbl.h: Re-generate.
236 2019-11-11 Jan Beulich <jbeulich@suse.com>
238 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
239 smaxp/sminp entries' "tied_operand" field to 2.
241 2019-11-11 Jan Beulich <jbeulich@suse.com>
243 * aarch64-opc.c (operand_general_constraint_met_p): Replace
244 "index" local variable by that of the already existing "num".
246 2019-11-08 H.J. Lu <hongjiu.lu@intel.com>
249 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
250 * i386-tbl.h: Regenerated.
252 2019-11-08 Jan Beulich <jbeulich@suse.com>
254 * i386-gen.c (operand_type_init): Add Class= to
255 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
256 OPERAND_TYPE_REGBND entry.
257 (operand_classes): Add RegMask and RegBND entries.
258 (operand_types): Drop RegMask and RegBND entry.
259 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
260 (RegMask, RegBND): Delete.
261 (union i386_operand_type): Remove regmask and regbnd fields.
262 * i386-opc.tbl (RegMask, RegBND): Define.
263 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
265 * i386-init.h, i386-tbl.h: Re-generate.
267 2019-11-08 Jan Beulich <jbeulich@suse.com>
269 * i386-gen.c (operand_type_init): Add Class= to
270 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
271 OPERAND_TYPE_REGZMM entries.
272 (operand_classes): Add RegMMX and RegSIMD entries.
273 (operand_types): Drop RegMMX and RegSIMD entries.
274 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
275 (RegMMX, RegSIMD): Delete.
276 (union i386_operand_type): Remove regmmx and regsimd fields.
277 * i386-opc.tbl (RegMMX): Define.
278 (RegXMM, RegYMM, RegZMM): Add Class=.
279 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
281 * i386-init.h, i386-tbl.h: Re-generate.
283 2019-11-08 Jan Beulich <jbeulich@suse.com>
285 * i386-gen.c (operand_type_init): Add Class= to
286 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
288 (operand_classes): Add RegCR, RegDR, and RegTR entries.
289 (operand_types): Drop Control, Debug, and Test entries.
290 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
291 (Control, Debug, Test): Delete.
292 (union i386_operand_type): Remove control, debug, and test
294 * i386-opc.tbl (Control, Debug, Test): Define.
295 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
296 Class=RegDR, and Test by Class=RegTR.
297 * i386-init.h, i386-tbl.h: Re-generate.
299 2019-11-08 Jan Beulich <jbeulich@suse.com>
301 * i386-gen.c (operand_type_init): Add Class= to
302 OPERAND_TYPE_SREG entry.
303 (operand_classes): Add SReg entry.
304 (operand_types): Drop SReg entry.
305 * i386-opc.h (enum operand_class): Add SReg.
307 (union i386_operand_type): Remove sreg field.
308 * i386-opc.tbl (SReg): Define.
309 * i386-reg.tbl: Replace SReg by Class=SReg.
310 * i386-init.h, i386-tbl.h: Re-generate.
312 2019-11-08 Jan Beulich <jbeulich@suse.com>
314 * i386-gen.c (operand_type_init): Add Class=. New
315 OPERAND_TYPE_ANYIMM entry.
316 (operand_classes): New.
317 (operand_types): Drop Reg entry.
318 (output_operand_type): New parameter "class". Process it.
319 (process_i386_operand_type): New local variable "class".
320 (main): Adjust static assertions.
321 * i386-opc.h (CLASS_WIDTH): Define.
322 (enum operand_class): New.
323 (Reg): Replace by Class. Adjust comment.
324 (union i386_operand_type): Replace reg by class.
325 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
327 * i386-reg.tbl: Replace Reg by Class=Reg.
328 * i386-init.h: Re-generate.
330 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
332 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
333 (aarch64_opcode_table): Add data gathering hint mnemonic.
334 * opcodes/aarch64-dis-2.c: Account for new instruction.
336 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
338 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
341 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
343 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
344 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
345 aarch64_feature_f64mm): New feature sets.
346 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
347 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
349 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
351 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
352 (OP_SVE_QQQ): New qualifier.
353 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
354 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
355 the movprfx constraint.
356 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
357 (aarch64_opcode_table): Define new instructions smmla,
358 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
360 * aarch64-opc.c (operand_general_constraint_met_p): Handle
361 AARCH64_OPND_SVE_ADDR_RI_S4x32.
362 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
363 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
364 Account for new instructions.
365 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
367 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
369 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
370 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
372 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
374 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
375 (neon_opcodes): Add bfloat SIMD instructions.
376 (print_insn_coprocessor): Add new control character %b to print
377 condition code without checking cp_num.
378 (print_insn_neon): Account for BFloat16 instructions that have no
379 special top-byte handling.
381 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
382 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
384 * arm-dis.c (print_insn_coprocessor,
385 print_insn_generic_coprocessor): Create wrapper functions around
386 the implementation of the print_insn_coprocessor control codes.
387 (print_insn_coprocessor_1): Original print_insn_coprocessor
388 function that now takes which array to look at as an argument.
389 (print_insn_arm): Use both print_insn_coprocessor and
390 print_insn_generic_coprocessor.
391 (print_insn_thumb32): As above.
393 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
394 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
396 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
397 in reglane special case.
398 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
399 aarch64_find_next_opcode): Account for new instructions.
400 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
401 in reglane special case.
402 * aarch64-opc.c (struct operand_qualifier_data): Add data for
403 new AARCH64_OPND_QLF_S_2H qualifier.
404 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
405 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
406 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
408 (BFLOAT_SVE, BFLOAT): New feature set macros.
409 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
411 (aarch64_opcode_table): Define new instructions bfdot,
412 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
415 2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
416 2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
418 * aarch64-tbl.h (ARMV8_6): New macro.
420 2019-11-07 Jan Beulich <jbeulich@suse.com>
422 * i386-dis.c (prefix_table): Add mcommit.
423 (rm_table): Add rdpru.
424 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
425 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
426 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
427 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
428 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
429 * i386-opc.tbl (mcommit, rdpru): New.
430 * i386-init.h, i386-tbl.h: Re-generate.
432 2019-11-07 Jan Beulich <jbeulich@suse.com>
434 * i386-dis.c (OP_Mwait): Drop local variable "names", use
436 (OP_Monitor): Drop local variable "op1_names", re-purpose
437 "names" for it instead, and replace former "names" uses by
440 2019-11-07 Jan Beulich <jbeulich@suse.com>
443 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
445 * opcodes/i386-tbl.h: Re-generate.
447 2019-11-05 Jan Beulich <jbeulich@suse.com>
449 * i386-dis.c (OP_Mwaitx): Delete.
450 (prefix_table): Use OP_Mwait for mwaitx entry.
451 (OP_Mwait): Also handle mwaitx.
453 2019-11-05 Jan Beulich <jbeulich@suse.com>
455 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
456 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
457 (prefix_table): Add respective entries.
458 (rm_table): Link to those entries.
460 2019-11-05 Jan Beulich <jbeulich@suse.com>
462 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
463 (REG_0F1C_P_0_MOD_0): ... this.
464 (REG_0F1E_MOD_3): Rename to ...
465 (REG_0F1E_P_1_MOD_3): ... this.
466 (RM_0F01_REG_5): Rename to ...
467 (RM_0F01_REG_5_MOD_3): ... this.
468 (RM_0F01_REG_7): Rename to ...
469 (RM_0F01_REG_7_MOD_3): ... this.
470 (RM_0F1E_MOD_3_REG_7): Rename to ...
471 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
472 (RM_0FAE_REG_6): Rename to ...
473 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
474 (RM_0FAE_REG_7): Rename to ...
475 (RM_0FAE_REG_7_MOD_3): ... this.
476 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
477 (PREFIX_0F01_REG_5_MOD_0): ... this.
478 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
479 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
480 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
481 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
482 (PREFIX_0FAE_REG_0): Rename to ...
483 (PREFIX_0FAE_REG_0_MOD_3): ... this.
484 (PREFIX_0FAE_REG_1): Rename to ...
485 (PREFIX_0FAE_REG_1_MOD_3): ... this.
486 (PREFIX_0FAE_REG_2): Rename to ...
487 (PREFIX_0FAE_REG_2_MOD_3): ... this.
488 (PREFIX_0FAE_REG_3): Rename to ...
489 (PREFIX_0FAE_REG_3_MOD_3): ... this.
490 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
491 (PREFIX_0FAE_REG_4_MOD_0): ... this.
492 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
493 (PREFIX_0FAE_REG_4_MOD_3): ... this.
494 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
495 (PREFIX_0FAE_REG_5_MOD_0): ... this.
496 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
497 (PREFIX_0FAE_REG_5_MOD_3): ... this.
498 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
499 (PREFIX_0FAE_REG_6_MOD_0): ... this.
500 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
501 (PREFIX_0FAE_REG_6_MOD_3): ... this.
502 (PREFIX_0FAE_REG_7): Rename to ...
503 (PREFIX_0FAE_REG_7_MOD_0): ... this.
504 (PREFIX_MOD_0_0FC3): Rename to ...
505 (PREFIX_0FC3_MOD_0): ... this.
506 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
507 (PREFIX_0FC7_REG_6_MOD_0): ... this.
508 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
509 (PREFIX_0FC7_REG_6_MOD_3): ... this.
510 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
511 (PREFIX_0FC7_REG_7_MOD_3): ... this.
512 (reg_table, prefix_table, mod_table, rm_table): Adjust
515 2019-11-04 Nick Clifton <nickc@redhat.com>
517 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
518 of a v850 system register. Move the v850_sreg_names array into
520 (get_v850_reg_name): Likewise for ordinary register names.
521 (get_v850_vreg_name): Likewise for vector register names.
522 (get_v850_cc_name): Likewise for condition codes.
523 * get_v850_float_cc_name): Likewise for floating point condition
525 (get_v850_cacheop_name): Likewise for cache-ops.
526 (get_v850_prefop_name): Likewise for pref-ops.
527 (disassemble): Use the new accessor functions.
529 2019-10-30 Delia Burduv <delia.burduv@arm.com>
531 * aarch64-opc.c (print_immediate_offset_address): Don't print the
532 immediate for the writeback form of ldraa/ldrab if it is 0.
533 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
534 * aarch64-opc-2.c: Regenerated.
536 2019-10-30 Jan Beulich <jbeulich@suse.com>
538 * i386-gen.c (operand_type_shorthands): Delete.
539 (operand_type_init): Expand previous shorthands.
540 (set_bitfield_from_shorthand): Rename back to ...
541 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
542 of operand_type_init[].
543 (set_bitfield): Adjust call to the above function.
544 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
545 RegXMM, RegYMM, RegZMM): Define.
546 * i386-reg.tbl: Expand prior shorthands.
548 2019-10-30 Jan Beulich <jbeulich@suse.com>
550 * i386-gen.c (output_i386_opcode): Change order of fields
552 * i386-opc.h (struct insn_template): Move operands field.
553 Convert extension_opcode field to unsigned short.
554 * i386-tbl.h: Re-generate.
556 2019-10-30 Jan Beulich <jbeulich@suse.com>
558 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
560 * i386-opc.h (W): Extend comment.
561 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
562 general purpose variants not allowing for byte operands.
563 * i386-tbl.h: Re-generate.
565 2019-10-29 Nick Clifton <nickc@redhat.com>
567 * tic30-dis.c (print_branch): Correct size of operand array.
569 2019-10-29 Nick Clifton <nickc@redhat.com>
571 * d30v-dis.c (print_insn): Check that operand index is valid
572 before attempting to access the operands array.
574 2019-10-29 Nick Clifton <nickc@redhat.com>
576 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
577 locating the bit to be tested.
579 2019-10-29 Nick Clifton <nickc@redhat.com>
581 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
583 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
584 (print_insn_s12z): Check for illegal size values.
586 2019-10-28 Nick Clifton <nickc@redhat.com>
588 * csky-dis.c (csky_chars_to_number): Check for a negative
589 count. Use an unsigned integer to construct the return value.
591 2019-10-28 Nick Clifton <nickc@redhat.com>
593 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
594 operand buffer. Set value to 15 not 13.
595 (get_register_operand): Use OPERAND_BUFFER_LEN.
596 (get_indirect_operand): Likewise.
597 (print_two_operand): Likewise.
598 (print_three_operand): Likewise.
599 (print_oar_insn): Likewise.
601 2019-10-28 Nick Clifton <nickc@redhat.com>
603 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
604 (bit_extract_simple): Likewise.
605 (bit_copy): Likewise.
606 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
607 index_offset array are not accessed.
609 2019-10-28 Nick Clifton <nickc@redhat.com>
611 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
614 2019-10-25 Nick Clifton <nickc@redhat.com>
616 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
617 access to opcodes.op array element.
619 2019-10-23 Nick Clifton <nickc@redhat.com>
621 * rx-dis.c (get_register_name): Fix spelling typo in error
623 (get_condition_name, get_flag_name, get_double_register_name)
624 (get_double_register_high_name, get_double_register_low_name)
625 (get_double_control_register_name, get_double_condition_name)
626 (get_opsize_name, get_size_name): Likewise.
628 2019-10-22 Nick Clifton <nickc@redhat.com>
630 * rx-dis.c (get_size_name): New function. Provides safe
631 access to name array.
632 (get_opsize_name): Likewise.
633 (print_insn_rx): Use the accessor functions.
635 2019-10-16 Nick Clifton <nickc@redhat.com>
637 * rx-dis.c (get_register_name): New function. Provides safe
638 access to name array.
639 (get_condition_name, get_flag_name, get_double_register_name)
640 (get_double_register_high_name, get_double_register_low_name)
641 (get_double_control_register_name, get_double_condition_name):
643 (print_insn_rx): Use the accessor functions.
645 2019-10-09 Nick Clifton <nickc@redhat.com>
648 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
651 2019-10-07 Jan Beulich <jbeulich@suse.com>
653 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
654 (cmpsd): Likewise. Move EsSeg to other operand.
655 * opcodes/i386-tbl.h: Re-generate.
657 2019-09-23 Alan Modra <amodra@gmail.com>
659 * m68k-dis.c: Include cpu-m68k.h
661 2019-09-23 Alan Modra <amodra@gmail.com>
663 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
664 "elf/mips.h" earlier.
666 2018-09-20 Jan Beulich <jbeulich@suse.com>
669 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
671 * i386-tbl.h: Re-generate.
673 2019-09-18 Alan Modra <amodra@gmail.com>
675 * arc-ext.c: Update throughout for bfd section macro changes.
677 2019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
679 * Makefile.in: Re-generate.
680 * configure: Re-generate.
682 2019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
684 * riscv-opc.c (riscv_opcodes): Change subset field
685 to insn_class field for all instructions.
686 (riscv_insn_types): Likewise.
688 2019-09-16 Phil Blundell <pb@pbcl.net>
690 * configure: Regenerated.
692 2019-09-10 Miod Vallat <miod@online.fr>
695 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
697 2019-09-09 Phil Blundell <pb@pbcl.net>
699 binutils 2.33 branch created.
701 2019-09-03 Nick Clifton <nickc@redhat.com>
704 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
705 greater than zero before indexing via (bufcnt -1).
707 2019-09-03 Nick Clifton <nickc@redhat.com>
710 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
711 (MAX_SPEC_REG_NAME_LEN): Define.
712 (struct mmix_dis_info): Use defined constants for array lengths.
713 (get_reg_name): New function.
714 (get_sprec_reg_name): New function.
715 (print_insn_mmix): Use new functions.
717 2019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
719 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
720 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
721 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
723 2019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
725 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
726 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
727 (aarch64_sys_reg_supported_p): Update checks for the above.
729 2019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
731 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
732 cases MVE_SQRSHRL and MVE_UQRSHLL.
733 (print_insn_mve): Add case for specifier 'k' to check
734 specific bit of the instruction.
736 2019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
739 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
740 encountering an unknown machine type.
741 (print_insn_arc): Handle arc_insn_length returning 0. In error
742 cases return -1 rather than calling abort.
744 2019-08-07 Jan Beulich <jbeulich@suse.com>
746 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
747 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
749 * i386-tbl.h: Re-generate.
751 2019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
753 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
756 2019-07-30 Mel Chen <mel.chen@sifive.com>
758 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
759 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
761 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
764 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
766 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
767 and MPY class instructions.
768 (parse_option): Add nps400 option.
769 (print_arc_disassembler_options): Add nps400 info.
771 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
773 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
776 * arc-opc.c (RAD_CHK): Add.
777 * arc-tbl.h: Regenerate.
779 2019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
781 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
782 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
784 2019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
786 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
787 instructions as UNPREDICTABLE.
789 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
791 * bpf-desc.c: Regenerated.
793 2019-07-17 Jan Beulich <jbeulich@suse.com>
795 * i386-gen.c (static_assert): Define.
797 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
798 (Opcode_Modifier_Num): ... this.
801 2019-07-16 Jan Beulich <jbeulich@suse.com>
803 * i386-gen.c (operand_types): Move RegMem ...
804 (opcode_modifiers): ... here.
805 * i386-opc.h (RegMem): Move to opcode modifer enum.
806 (union i386_operand_type): Move regmem field ...
807 (struct i386_opcode_modifier): ... here.
808 * i386-opc.tbl (RegMem): Define.
809 (mov, movq): Move RegMem on segment, control, debug, and test
811 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
812 to non-SSE2AVX flavor.
813 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
814 Move RegMem on register only flavors. Drop IgnoreSize from
815 legacy encoding flavors.
816 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
818 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
819 register only flavors.
820 (vmovd): Move RegMem and drop IgnoreSize on register only
821 flavor. Change opcode and operand order to store form.
822 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
824 2019-07-16 Jan Beulich <jbeulich@suse.com>
826 * i386-gen.c (operand_type_init, operand_types): Replace SReg
828 * i386-opc.h (SReg2, SReg3): Replace by ...
830 (union i386_operand_type): Replace sreg fields.
831 * i386-opc.tbl (mov, ): Use SReg.
832 (push, pop): Likewies. Drop i386 and x86-64 specific segment
834 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
835 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
837 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
839 * bpf-desc.c: Regenerate.
840 * bpf-opc.c: Likewise.
841 * bpf-opc.h: Likewise.
843 2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
845 * bpf-desc.c: Regenerate.
846 * bpf-opc.c: Likewise.
848 2019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
850 * arm-dis.c (print_insn_coprocessor): Rename index to
853 2019-07-05 Kito Cheng <kito.cheng@sifive.com>
855 * riscv-opc.c (riscv_insn_types): Add r4 type.
857 * riscv-opc.c (riscv_insn_types): Add b and j type.
859 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
860 format for sb type and correct s type.
862 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
864 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
865 SVE FMOV alias of FCPY.
867 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
869 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
870 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
872 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
874 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
875 registers in an instruction prefixed by MOVPRFX.
877 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
879 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
880 sve_size_13 icode to account for variant behaviour of
882 * aarch64-dis-2.c: Regenerate.
883 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
884 sve_size_13 icode to account for variant behaviour of
886 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
887 (OP_SVE_VVV_Q_D): Add new qualifier.
888 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
889 (struct aarch64_opcode): Split pmull{t,b} into those requiring
892 2019-07-01 Jan Beulich <jbeulich@suse.com>
894 * opcodes/i386-gen.c (operand_type_init): Remove
895 OPERAND_TYPE_VEC_IMM4 entry.
896 (operand_types): Remove Vec_Imm4.
897 * opcodes/i386-opc.h (Vec_Imm4): Delete.
898 (union i386_operand_type): Remove vec_imm4.
899 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
900 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
902 2019-07-01 Jan Beulich <jbeulich@suse.com>
904 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
905 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
906 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
907 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
908 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
909 monitorx, mwaitx): Drop ImmExt from operand-less forms.
910 * i386-tbl.h: Re-generate.
912 2019-07-01 Jan Beulich <jbeulich@suse.com>
914 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
916 * i386-tbl.h: Re-generate.
918 2019-07-01 Jan Beulich <jbeulich@suse.com>
920 * i386-opc.tbl (C): New.
921 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
922 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
923 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
924 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
925 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
926 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
927 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
928 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
929 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
930 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
931 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
932 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
933 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
934 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
935 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
936 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
937 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
938 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
939 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
940 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
941 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
942 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
943 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
944 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
945 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
946 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
948 * i386-tbl.h: Re-generate.
950 2019-07-01 Jan Beulich <jbeulich@suse.com>
952 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
954 * i386-tbl.h: Re-generate.
956 2019-07-01 Jan Beulich <jbeulich@suse.com>
958 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
959 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
960 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
961 * i386-tbl.h: Re-generate.
963 2019-07-01 Jan Beulich <jbeulich@suse.com>
965 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
966 Disp8MemShift from register only templates.
967 * i386-tbl.h: Re-generate.
969 2019-07-01 Jan Beulich <jbeulich@suse.com>
971 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
972 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
973 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
974 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
975 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
976 EVEX_W_0F11_P_3_M_1): Delete.
977 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
978 EVEX_W_0F11_P_3): New.
979 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
980 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
981 MOD_EVEX_0F11_PREFIX_3 table entries.
982 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
983 PREFIX_EVEX_0F11 table entries.
984 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
985 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
986 EVEX_W_0F11_P_3_M_{0,1} table entries.
988 2019-07-01 Jan Beulich <jbeulich@suse.com>
990 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
993 2019-06-27 H.J. Lu <hongjiu.lu@intel.com>
996 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
997 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
998 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
999 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1000 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1001 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1002 EVEX_LEN_0F38C7_R_6_P_2_W_1.
1003 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1004 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1005 PREFIX_EVEX_0F38C6_REG_6 entries.
1006 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1007 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1008 EVEX_W_0F38C7_R_6_P_2 entries.
1009 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1010 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1011 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1012 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1013 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1014 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1015 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1017 2019-06-27 Jan Beulich <jbeulich@suse.com>
1019 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1020 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1021 VEX_LEN_0F2D_P_3): Delete.
1022 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1023 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1024 (prefix_table): ... here.
1026 2019-06-27 Jan Beulich <jbeulich@suse.com>
1028 * i386-dis.c (Iq): Delete.
1030 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1032 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1033 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1034 (OP_E_memory): Also honor needindex when deciding whether an
1035 address size prefix needs printing.
1036 (OP_I): Remove handling of q_mode. Add handling of d_mode.
1038 2019-06-26 Jim Wilson <jimw@sifive.com>
1041 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1042 Set info->display_endian to info->endian_code.
1044 2019-06-25 Jan Beulich <jbeulich@suse.com>
1046 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1047 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1048 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1049 OPERAND_TYPE_ACC64 entries.
1050 * i386-init.h: Re-generate.
1052 2019-06-25 Jan Beulich <jbeulich@suse.com>
1054 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1056 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1058 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1060 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1061 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1063 2019-06-25 Jan Beulich <jbeulich@suse.com>
1065 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1068 2019-06-25 Jan Beulich <jbeulich@suse.com>
1070 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1071 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1073 * i386-opc.tbl (movnti): Add IgnoreSize.
1074 * i386-tbl.h: Re-generate.
1076 2019-06-25 Jan Beulich <jbeulich@suse.com>
1078 * i386-opc.tbl (and): Mark Imm8S form for optimization.
1079 * i386-tbl.h: Re-generate.
1081 2019-06-21 H.J. Lu <hongjiu.lu@intel.com>
1083 * i386-dis-evex.h: Break into ...
1084 * i386-dis-evex-len.h: New file.
1085 * i386-dis-evex-mod.h: Likewise.
1086 * i386-dis-evex-prefix.h: Likewise.
1087 * i386-dis-evex-reg.h: Likewise.
1088 * i386-dis-evex-w.h: Likewise.
1089 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1090 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1091 i386-dis-evex-mod.h.
1093 2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
1096 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1097 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1099 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1100 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1101 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1102 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1103 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1104 EVEX_LEN_0F385B_P_2_W_1.
1105 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1106 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1107 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1108 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1109 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1110 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1111 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1112 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1113 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1114 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1116 2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
1119 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1120 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1121 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1122 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1123 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1124 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1125 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1126 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1127 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1128 EVEX_LEN_0F3A43_P_2_W_1.
1129 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1130 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1131 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1132 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1133 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1134 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1135 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1136 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1137 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1138 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1139 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1140 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1142 2019-06-14 Nick Clifton <nickc@redhat.com>
1144 * po/fr.po; Updated French translation.
1146 2019-06-13 Stafford Horne <shorne@gmail.com>
1148 * or1k-asm.c: Regenerated.
1149 * or1k-desc.c: Regenerated.
1150 * or1k-desc.h: Regenerated.
1151 * or1k-dis.c: Regenerated.
1152 * or1k-ibld.c: Regenerated.
1153 * or1k-opc.c: Regenerated.
1154 * or1k-opc.h: Regenerated.
1155 * or1k-opinst.c: Regenerated.
1157 2019-06-12 Peter Bergner <bergner@linux.ibm.com>
1159 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1161 2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1164 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1165 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1166 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1167 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1168 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1169 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1170 EVEX_LEN_0F3A1B_P_2_W_1.
1171 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1172 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1173 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1174 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1175 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1176 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1177 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1178 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1180 2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1183 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1184 EVEX.vvvv when disassembling VEX and EVEX instructions.
1185 (OP_VEX): Set vex.register_specifier to 0 after readding
1186 vex.register_specifier.
1187 (OP_Vex_2src_1): Likewise.
1188 (OP_Vex_2src_2): Likewise.
1189 (OP_LWP_E): Likewise.
1190 (OP_EX_Vex): Don't check vex.register_specifier.
1191 (OP_XMM_Vex): Likewise.
1193 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1194 Lili Cui <lili.cui@intel.com>
1196 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1197 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1199 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1200 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1201 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1202 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1203 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1204 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1205 * i386-init.h: Regenerated.
1206 * i386-tbl.h: Likewise.
1208 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1209 Lili Cui <lili.cui@intel.com>
1211 * doc/c-i386.texi: Document enqcmd.
1212 * testsuite/gas/i386/enqcmd-intel.d: New file.
1213 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1214 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1215 * testsuite/gas/i386/enqcmd.d: Likewise.
1216 * testsuite/gas/i386/enqcmd.s: Likewise.
1217 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1218 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1219 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1220 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1221 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1222 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1223 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1226 2019-06-04 Alan Hayward <alan.hayward@arm.com>
1228 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1230 2019-06-03 Alan Modra <amodra@gmail.com>
1232 * ppc-dis.c (prefix_opcd_indices): Correct size.
1234 2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1237 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1239 * i386-tbl.h: Regenerated.
1241 2019-05-24 Alan Modra <amodra@gmail.com>
1243 * po/POTFILES.in: Regenerate.
1245 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
1246 Alan Modra <amodra@gmail.com>
1248 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1249 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1250 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1251 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1252 XTOP>): Define and add entries.
1253 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1254 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1255 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1256 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1258 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
1259 Alan Modra <amodra@gmail.com>
1261 * ppc-dis.c (ppc_opts): Add "future" entry.
1262 (PREFIX_OPCD_SEGS): Define.
1263 (prefix_opcd_indices): New array.
1264 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1265 (lookup_prefix): New function.
1266 (print_insn_powerpc): Handle 64-bit prefix instructions.
1267 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1268 (PMRR, POWERXX): Define.
1269 (prefix_opcodes): New instruction table.
1270 (prefix_num_opcodes): New constant.
1272 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1274 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1275 * configure: Regenerated.
1276 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1278 (HFILES): Add bpf-desc.h and bpf-opc.h.
1279 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1280 bpf-ibld.c and bpf-opc.c.
1282 * Makefile.in: Regenerated.
1283 * disassemble.c (ARCH_bpf): Define.
1284 (disassembler): Add case for bfd_arch_bpf.
1285 (disassemble_init_for_target): Likewise.
1286 (enum epbf_isa_attr): Define.
1287 * disassemble.h: extern print_insn_bpf.
1288 * bpf-asm.c: Generated.
1289 * bpf-opc.h: Likewise.
1290 * bpf-opc.c: Likewise.
1291 * bpf-ibld.c: Likewise.
1292 * bpf-dis.c: Likewise.
1293 * bpf-desc.h: Likewise.
1294 * bpf-desc.c: Likewise.
1296 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1298 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1299 and VMSR with the new operands.
1301 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1303 * arm-dis.c (enum mve_instructions): New enum
1304 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1306 (mve_opcodes): New instructions as above.
1307 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1309 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1311 2019-05-21 Sudakshina Das <sudi.das@arm.com>
1313 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1314 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1315 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1316 uqshl, urshrl and urshr.
1317 (is_mve_okay_in_it): Add new instructions to TRUE list.
1318 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1319 (print_insn_mve): Updated to accept new %j,
1320 %<bitfield>m and %<bitfield>n patterns.
1322 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1324 * mips-opc.c (mips_builtin_opcodes): Change source register
1325 constraint for DAUI.
1327 2019-05-20 Nick Clifton <nickc@redhat.com>
1329 * po/fr.po: Updated French translation.
1331 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1332 Michael Collison <michael.collison@arm.com>
1334 * arm-dis.c (thumb32_opcodes): Add new instructions.
1335 (enum mve_instructions): Likewise.
1336 (enum mve_undefined): Add new reasons.
1337 (is_mve_encoding_conflict): Handle new instructions.
1338 (is_mve_undefined): Likewise.
1339 (is_mve_unpredictable): Likewise.
1340 (print_mve_undefined): Likewise.
1341 (print_mve_size): Likewise.
1343 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1344 Michael Collison <michael.collison@arm.com>
1346 * arm-dis.c (thumb32_opcodes): Add new instructions.
1347 (enum mve_instructions): Likewise.
1348 (is_mve_encoding_conflict): Handle new instructions.
1349 (is_mve_undefined): Likewise.
1350 (is_mve_unpredictable): Likewise.
1351 (print_mve_size): Likewise.
1353 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1354 Michael Collison <michael.collison@arm.com>
1356 * arm-dis.c (thumb32_opcodes): Add new instructions.
1357 (enum mve_instructions): Likewise.
1358 (is_mve_encoding_conflict): Likewise.
1359 (is_mve_unpredictable): Likewise.
1360 (print_mve_size): Likewise.
1362 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1363 Michael Collison <michael.collison@arm.com>
1365 * arm-dis.c (thumb32_opcodes): Add new instructions.
1366 (enum mve_instructions): Likewise.
1367 (is_mve_encoding_conflict): Handle new instructions.
1368 (is_mve_undefined): Likewise.
1369 (is_mve_unpredictable): Likewise.
1370 (print_mve_size): Likewise.
1372 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1373 Michael Collison <michael.collison@arm.com>
1375 * arm-dis.c (thumb32_opcodes): Add new instructions.
1376 (enum mve_instructions): Likewise.
1377 (is_mve_encoding_conflict): Handle new instructions.
1378 (is_mve_undefined): Likewise.
1379 (is_mve_unpredictable): Likewise.
1380 (print_mve_size): Likewise.
1381 (print_insn_mve): Likewise.
1383 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1384 Michael Collison <michael.collison@arm.com>
1386 * arm-dis.c (thumb32_opcodes): Add new instructions.
1387 (print_insn_thumb32): Handle new instructions.
1389 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1390 Michael Collison <michael.collison@arm.com>
1392 * arm-dis.c (enum mve_instructions): Add new instructions.
1393 (enum mve_undefined): Add new reasons.
1394 (is_mve_encoding_conflict): Handle new instructions.
1395 (is_mve_undefined): Likewise.
1396 (is_mve_unpredictable): Likewise.
1397 (print_mve_undefined): Likewise.
1398 (print_mve_size): Likewise.
1399 (print_mve_shift_n): Likewise.
1400 (print_insn_mve): Likewise.
1402 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1403 Michael Collison <michael.collison@arm.com>
1405 * arm-dis.c (enum mve_instructions): Add new instructions.
1406 (is_mve_encoding_conflict): Handle new instructions.
1407 (is_mve_unpredictable): Likewise.
1408 (print_mve_rotate): Likewise.
1409 (print_mve_size): Likewise.
1410 (print_insn_mve): Likewise.
1412 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1413 Michael Collison <michael.collison@arm.com>
1415 * arm-dis.c (enum mve_instructions): Add new instructions.
1416 (is_mve_encoding_conflict): Handle new instructions.
1417 (is_mve_unpredictable): Likewise.
1418 (print_mve_size): Likewise.
1419 (print_insn_mve): Likewise.
1421 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1422 Michael Collison <michael.collison@arm.com>
1424 * arm-dis.c (enum mve_instructions): Add new instructions.
1425 (enum mve_undefined): Add new reasons.
1426 (is_mve_encoding_conflict): Handle new instructions.
1427 (is_mve_undefined): Likewise.
1428 (is_mve_unpredictable): Likewise.
1429 (print_mve_undefined): Likewise.
1430 (print_mve_size): Likewise.
1431 (print_insn_mve): Likewise.
1433 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1434 Michael Collison <michael.collison@arm.com>
1436 * arm-dis.c (enum mve_instructions): Add new instructions.
1437 (is_mve_encoding_conflict): Handle new instructions.
1438 (is_mve_undefined): Likewise.
1439 (is_mve_unpredictable): Likewise.
1440 (print_mve_size): Likewise.
1441 (print_insn_mve): Likewise.
1443 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1444 Michael Collison <michael.collison@arm.com>
1446 * arm-dis.c (enum mve_instructions): Add new instructions.
1447 (enum mve_unpredictable): Add new reasons.
1448 (enum mve_undefined): Likewise.
1449 (is_mve_okay_in_it): Handle new isntructions.
1450 (is_mve_encoding_conflict): Likewise.
1451 (is_mve_undefined): Likewise.
1452 (is_mve_unpredictable): Likewise.
1453 (print_mve_vmov_index): Likewise.
1454 (print_simd_imm8): Likewise.
1455 (print_mve_undefined): Likewise.
1456 (print_mve_unpredictable): Likewise.
1457 (print_mve_size): Likewise.
1458 (print_insn_mve): Likewise.
1460 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1461 Michael Collison <michael.collison@arm.com>
1463 * arm-dis.c (enum mve_instructions): Add new instructions.
1464 (enum mve_unpredictable): Add new reasons.
1465 (enum mve_undefined): Likewise.
1466 (is_mve_encoding_conflict): Handle new instructions.
1467 (is_mve_undefined): Likewise.
1468 (is_mve_unpredictable): Likewise.
1469 (print_mve_undefined): Likewise.
1470 (print_mve_unpredictable): Likewise.
1471 (print_mve_rounding_mode): Likewise.
1472 (print_mve_vcvt_size): Likewise.
1473 (print_mve_size): Likewise.
1474 (print_insn_mve): Likewise.
1476 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1477 Michael Collison <michael.collison@arm.com>
1479 * arm-dis.c (enum mve_instructions): Add new instructions.
1480 (enum mve_unpredictable): Add new reasons.
1481 (enum mve_undefined): Likewise.
1482 (is_mve_undefined): Handle new instructions.
1483 (is_mve_unpredictable): Likewise.
1484 (print_mve_undefined): Likewise.
1485 (print_mve_unpredictable): Likewise.
1486 (print_mve_size): Likewise.
1487 (print_insn_mve): Likewise.
1489 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1490 Michael Collison <michael.collison@arm.com>
1492 * arm-dis.c (enum mve_instructions): Add new instructions.
1493 (enum mve_undefined): Add new reasons.
1494 (insns): Add new instructions.
1495 (is_mve_encoding_conflict):
1496 (print_mve_vld_str_addr): New print function.
1497 (is_mve_undefined): Handle new instructions.
1498 (is_mve_unpredictable): Likewise.
1499 (print_mve_undefined): Likewise.
1500 (print_mve_size): Likewise.
1501 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1502 (print_insn_mve): Handle new operands.
1504 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1505 Michael Collison <michael.collison@arm.com>
1507 * arm-dis.c (enum mve_instructions): Add new instructions.
1508 (enum mve_unpredictable): Add new reasons.
1509 (is_mve_encoding_conflict): Handle new instructions.
1510 (is_mve_unpredictable): Likewise.
1511 (mve_opcodes): Add new instructions.
1512 (print_mve_unpredictable): Handle new reasons.
1513 (print_mve_register_blocks): New print function.
1514 (print_mve_size): Handle new instructions.
1515 (print_insn_mve): Likewise.
1517 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1518 Michael Collison <michael.collison@arm.com>
1520 * arm-dis.c (enum mve_instructions): Add new instructions.
1521 (enum mve_unpredictable): Add new reasons.
1522 (enum mve_undefined): Likewise.
1523 (is_mve_encoding_conflict): Handle new instructions.
1524 (is_mve_undefined): Likewise.
1525 (is_mve_unpredictable): Likewise.
1526 (coprocessor_opcodes): Move NEON VDUP from here...
1527 (neon_opcodes): ... to here.
1528 (mve_opcodes): Add new instructions.
1529 (print_mve_undefined): Handle new reasons.
1530 (print_mve_unpredictable): Likewise.
1531 (print_mve_size): Handle new instructions.
1532 (print_insn_neon): Handle vdup.
1533 (print_insn_mve): Handle new operands.
1535 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1536 Michael Collison <michael.collison@arm.com>
1538 * arm-dis.c (enum mve_instructions): Add new instructions.
1539 (enum mve_unpredictable): Add new values.
1540 (mve_opcodes): Add new instructions.
1541 (vec_condnames): New array with vector conditions.
1542 (mve_predicatenames): New array with predicate suffixes.
1543 (mve_vec_sizename): New array with vector sizes.
1544 (enum vpt_pred_state): New enum with vector predication states.
1545 (struct vpt_block): New struct type for vpt blocks.
1546 (vpt_block_state): Global struct to keep track of state.
1547 (mve_extract_pred_mask): New helper function.
1548 (num_instructions_vpt_block): Likewise.
1549 (mark_outside_vpt_block): Likewise.
1550 (mark_inside_vpt_block): Likewise.
1551 (invert_next_predicate_state): Likewise.
1552 (update_next_predicate_state): Likewise.
1553 (update_vpt_block_state): Likewise.
1554 (is_vpt_instruction): Likewise.
1555 (is_mve_encoding_conflict): Add entries for new instructions.
1556 (is_mve_unpredictable): Likewise.
1557 (print_mve_unpredictable): Handle new cases.
1558 (print_instruction_predicate): Likewise.
1559 (print_mve_size): New function.
1560 (print_vec_condition): New function.
1561 (print_insn_mve): Handle vpt blocks and new print operands.
1563 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1565 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1566 8, 14 and 15 for Armv8.1-M Mainline.
1568 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1569 Michael Collison <michael.collison@arm.com>
1571 * arm-dis.c (enum mve_instructions): New enum.
1572 (enum mve_unpredictable): Likewise.
1573 (enum mve_undefined): Likewise.
1574 (struct mopcode32): New struct.
1575 (is_mve_okay_in_it): New function.
1576 (is_mve_architecture): Likewise.
1577 (arm_decode_field): Likewise.
1578 (arm_decode_field_multiple): Likewise.
1579 (is_mve_encoding_conflict): Likewise.
1580 (is_mve_undefined): Likewise.
1581 (is_mve_unpredictable): Likewise.
1582 (print_mve_undefined): Likewise.
1583 (print_mve_unpredictable): Likewise.
1584 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1585 (print_insn_mve): New function.
1586 (print_insn_thumb32): Handle MVE architecture.
1587 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1589 2019-05-10 Nick Clifton <nickc@redhat.com>
1592 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1593 end of the table prematurely.
1595 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1597 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1600 2019-05-11 Alan Modra <amodra@gmail.com>
1602 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1603 when -Mraw is in effect.
1605 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1607 * aarch64-dis-2.c: Regenerate.
1608 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1609 (OP_SVE_BBB): New variant set.
1610 (OP_SVE_DDDD): New variant set.
1611 (OP_SVE_HHH): New variant set.
1612 (OP_SVE_HHHU): New variant set.
1613 (OP_SVE_SSS): New variant set.
1614 (OP_SVE_SSSU): New variant set.
1615 (OP_SVE_SHH): New variant set.
1616 (OP_SVE_SBBU): New variant set.
1617 (OP_SVE_DSS): New variant set.
1618 (OP_SVE_DHHU): New variant set.
1619 (OP_SVE_VMV_HSD_BHS): New variant set.
1620 (OP_SVE_VVU_HSD_BHS): New variant set.
1621 (OP_SVE_VVVU_SD_BH): New variant set.
1622 (OP_SVE_VVVU_BHSD): New variant set.
1623 (OP_SVE_VVV_QHD_DBS): New variant set.
1624 (OP_SVE_VVV_HSD_BHS): New variant set.
1625 (OP_SVE_VVV_HSD_BHS2): New variant set.
1626 (OP_SVE_VVV_BHS_HSD): New variant set.
1627 (OP_SVE_VV_BHS_HSD): New variant set.
1628 (OP_SVE_VVV_SD): New variant set.
1629 (OP_SVE_VVU_BHS_HSD): New variant set.
1630 (OP_SVE_VZVV_SD): New variant set.
1631 (OP_SVE_VZVV_BH): New variant set.
1632 (OP_SVE_VZV_SD): New variant set.
1633 (aarch64_opcode_table): Add sve2 instructions.
1635 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1637 * aarch64-asm-2.c: Regenerated.
1638 * aarch64-dis-2.c: Regenerated.
1639 * aarch64-opc-2.c: Regenerated.
1640 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1641 for SVE_SHLIMM_UNPRED_22.
1642 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1643 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1646 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1648 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1649 sve_size_tsz_bhs iclass encode.
1650 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1651 sve_size_tsz_bhs iclass decode.
1653 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1655 * aarch64-asm-2.c: Regenerated.
1656 * aarch64-dis-2.c: Regenerated.
1657 * aarch64-opc-2.c: Regenerated.
1658 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1659 for SVE_Zm4_11_INDEX.
1660 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1661 (fields): Handle SVE_i2h field.
1662 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1663 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1665 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1667 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1668 sve_shift_tsz_bhsd iclass encode.
1669 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1670 sve_shift_tsz_bhsd iclass decode.
1672 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1674 * aarch64-asm-2.c: Regenerated.
1675 * aarch64-dis-2.c: Regenerated.
1676 * aarch64-opc-2.c: Regenerated.
1677 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1678 (aarch64_encode_variant_using_iclass): Handle
1679 sve_shift_tsz_hsd iclass encode.
1680 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1681 sve_shift_tsz_hsd iclass decode.
1682 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1683 for SVE_SHRIMM_UNPRED_22.
1684 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1685 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1688 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1690 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1691 sve_size_013 iclass encode.
1692 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1693 sve_size_013 iclass decode.
1695 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1697 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1698 sve_size_bh iclass encode.
1699 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1700 sve_size_bh iclass decode.
1702 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1704 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1705 sve_size_sd2 iclass encode.
1706 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1707 sve_size_sd2 iclass decode.
1708 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1709 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1711 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1713 * aarch64-asm-2.c: Regenerated.
1714 * aarch64-dis-2.c: Regenerated.
1715 * aarch64-opc-2.c: Regenerated.
1716 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1718 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1719 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1721 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1723 * aarch64-asm-2.c: Regenerated.
1724 * aarch64-dis-2.c: Regenerated.
1725 * aarch64-opc-2.c: Regenerated.
1726 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1727 for SVE_Zm3_11_INDEX.
1728 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1729 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1730 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1732 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1734 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1736 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1737 sve_size_hsd2 iclass encode.
1738 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1739 sve_size_hsd2 iclass decode.
1740 * aarch64-opc.c (fields): Handle SVE_size field.
1741 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1743 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1745 * aarch64-asm-2.c: Regenerated.
1746 * aarch64-dis-2.c: Regenerated.
1747 * aarch64-opc-2.c: Regenerated.
1748 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1750 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1751 (fields): Handle SVE_rot3 field.
1752 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1753 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1755 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1757 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1760 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1763 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1764 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1765 aarch64_feature_sve2bitperm): New feature sets.
1766 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1767 for feature set addresses.
1768 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1769 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1771 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1772 Faraz Shahbazker <fshahbazker@wavecomp.com>
1774 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1775 argument and set ASE_EVA_R6 appropriately.
1776 (set_default_mips_dis_options): Pass ISA to above.
1777 (parse_mips_dis_option): Likewise.
1778 * mips-opc.c (EVAR6): New macro.
1779 (mips_builtin_opcodes): Add llwpe, scwpe.
1781 2019-05-01 Sudakshina Das <sudi.das@arm.com>
1783 * aarch64-asm-2.c: Regenerated.
1784 * aarch64-dis-2.c: Regenerated.
1785 * aarch64-opc-2.c: Regenerated.
1786 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1787 AARCH64_OPND_TME_UIMM16.
1788 (aarch64_print_operand): Likewise.
1789 * aarch64-tbl.h (QL_IMM_NIL): New.
1792 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1794 2019-04-29 John Darrington <john@darrington.wattle.id.au>
1796 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1798 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1799 Faraz Shahbazker <fshahbazker@wavecomp.com>
1801 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1803 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1805 * s12z-opc.h: Add extern "C" bracketing to help
1806 users who wish to use this interface in c++ code.
1808 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1810 * s12z-opc.c (bm_decode): Handle bit map operations with the
1813 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1815 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1816 specifier. Add entries for VLDR and VSTR of system registers.
1817 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1818 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1819 of %J and %K format specifier.
1821 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1823 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1824 Add new entries for VSCCLRM instruction.
1825 (print_insn_coprocessor): Handle new %C format control code.
1827 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1829 * arm-dis.c (enum isa): New enum.
1830 (struct sopcode32): New structure.
1831 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1832 set isa field of all current entries to ANY.
1833 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1834 Only match an entry if its isa field allows the current mode.
1836 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1838 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1840 (print_insn_thumb32): Add logic to print %n CLRM register list.
1842 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1844 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1847 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1849 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1850 (print_insn_thumb32): Edit the switch case for %Z.
1852 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1854 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1856 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1858 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1860 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1862 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1864 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1866 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1867 Arm register with r13 and r15 unpredictable.
1868 (thumb32_opcodes): New instructions for bfx and bflx.
1870 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1872 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1874 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1876 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1878 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1880 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1882 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1884 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1886 2019-04-12 John Darrington <john@darrington.wattle.id.au>
1888 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1889 "optr". ("operator" is a reserved word in c++).
1891 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1893 * aarch64-opc.c (aarch64_print_operand): Add case for
1895 (verify_constraints): Likewise.
1896 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1897 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1898 to accept Rt|SP as first operand.
1899 (AARCH64_OPERANDS): Add new Rt_SP.
1900 * aarch64-asm-2.c: Regenerated.
1901 * aarch64-dis-2.c: Regenerated.
1902 * aarch64-opc-2.c: Regenerated.
1904 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1906 * aarch64-asm-2.c: Regenerated.
1907 * aarch64-dis-2.c: Likewise.
1908 * aarch64-opc-2.c: Likewise.
1909 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1911 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1913 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1915 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1917 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1918 * i386-init.h: Regenerated.
1920 2019-04-07 Alan Modra <amodra@gmail.com>
1922 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1923 op_separator to control printing of spaces, comma and parens
1924 rather than need_comma, need_paren and spaces vars.
1926 2019-04-07 Alan Modra <amodra@gmail.com>
1929 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1930 (print_insn_neon, print_insn_arm): Likewise.
1932 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1934 * i386-dis-evex.h (evex_table): Updated to support BF16
1936 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1937 and EVEX_W_0F3872_P_3.
1938 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1939 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1940 * i386-opc.h (enum): Add CpuAVX512_BF16.
1941 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1942 * i386-opc.tbl: Add AVX512 BF16 instructions.
1943 * i386-init.h: Regenerated.
1944 * i386-tbl.h: Likewise.
1946 2019-04-05 Alan Modra <amodra@gmail.com>
1948 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1949 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1950 to favour printing of "-" branch hint when using the "y" bit.
1951 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1953 2019-04-05 Alan Modra <amodra@gmail.com>
1955 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1956 opcode until first operand is output.
1958 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
1961 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1962 (valid_bo_post_v2): Add support for 'at' branch hints.
1963 (insert_bo): Only error on branch on ctr.
1964 (get_bo_hint_mask): New function.
1965 (insert_boe): Add new 'branch_taken' formal argument. Add support
1966 for inserting 'at' branch hints.
1967 (extract_boe): Add new 'branch_taken' formal argument. Add support
1968 for extracting 'at' branch hints.
1969 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1970 (BOE): Delete operand.
1971 (BOM, BOP): New operands.
1973 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1974 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1975 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1976 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1977 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1978 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1979 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1980 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1981 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1982 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1983 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1984 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1985 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1986 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1987 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1988 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1989 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1990 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1991 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1992 bttarl+>: New extended mnemonics.
1994 2019-03-28 Alan Modra <amodra@gmail.com>
1997 * ppc-opc.c (BTF): Define.
1998 (powerpc_opcodes): Use for mtfsb*.
1999 * ppc-dis.c (print_insn_powerpc): Print fields with both
2000 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2002 2019-03-25 Tamar Christina <tamar.christina@arm.com>
2004 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2005 (mapping_symbol_for_insn): Implement new algorithm.
2006 (print_insn): Remove duplicate code.
2008 2019-03-25 Tamar Christina <tamar.christina@arm.com>
2010 * aarch64-dis.c (print_insn_aarch64):
2013 2019-03-25 Tamar Christina <tamar.christina@arm.com>
2015 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2018 2019-03-25 Tamar Christina <tamar.christina@arm.com>
2020 * aarch64-dis.c (last_stop_offset): New.
2021 (print_insn_aarch64): Use stop_offset.
2023 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
2026 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2028 * i386-init.h: Regenerated.
2030 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
2033 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2034 vmovdqu16, vmovdqu32 and vmovdqu64.
2035 * i386-tbl.h: Regenerated.
2037 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2039 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
2040 from vstrszb, vstrszh, and vstrszf.
2042 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2044 * s390-opc.txt: Add instruction descriptions.
2046 2019-02-08 Jim Wilson <jimw@sifive.com>
2048 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2051 2019-02-07 Tamar Christina <tamar.christina@arm.com>
2053 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2055 2019-02-07 Tamar Christina <tamar.christina@arm.com>
2058 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2059 * aarch64-opc.c (verify_elem_sd): New.
2060 (fields): Add FLD_sz entr.
2061 * aarch64-tbl.h (_SIMD_INSN): New.
2062 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2063 fmulx scalar and vector by element isns.
2065 2019-02-07 Nick Clifton <nickc@redhat.com>
2067 * po/sv.po: Updated Swedish translation.
2069 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
2071 * s390-mkopc.c (main): Accept arch13 as cpu string.
2072 * s390-opc.c: Add new instruction formats and instruction opcode
2074 * s390-opc.txt: Add new arch13 instructions.
2076 2019-01-25 Sudakshina Das <sudi.das@arm.com>
2078 * aarch64-tbl.h (QL_LDST_AT): Update macro.
2079 (aarch64_opcode): Change encoding for stg, stzg
2081 * aarch64-asm-2.c: Regenerated.
2082 * aarch64-dis-2.c: Regenerated.
2083 * aarch64-opc-2.c: Regenerated.
2085 2019-01-25 Sudakshina Das <sudi.das@arm.com>
2087 * aarch64-asm-2.c: Regenerated.
2088 * aarch64-dis-2.c: Likewise.
2089 * aarch64-opc-2.c: Likewise.
2090 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2092 2019-01-25 Sudakshina Das <sudi.das@arm.com>
2093 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
2095 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2096 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2097 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2098 * aarch64-dis.h (ext_addr_simple_2): Likewise.
2099 * aarch64-opc.c (operand_general_constraint_met_p): Remove
2100 case for ldstgv_indexed.
2101 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2102 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2103 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2104 * aarch64-asm-2.c: Regenerated.
2105 * aarch64-dis-2.c: Regenerated.
2106 * aarch64-opc-2.c: Regenerated.
2108 2019-01-23 Nick Clifton <nickc@redhat.com>
2110 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2112 2019-01-21 Nick Clifton <nickc@redhat.com>
2114 * po/de.po: Updated German translation.
2115 * po/uk.po: Updated Ukranian translation.
2117 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
2118 * mips-dis.c (mips_arch_choices): Fix typo in
2119 gs464, gs464e and gs264e descriptors.
2121 2019-01-19 Nick Clifton <nickc@redhat.com>
2123 * configure: Regenerate.
2124 * po/opcodes.pot: Regenerate.
2126 2018-06-24 Nick Clifton <nickc@redhat.com>
2128 2.32 branch created.
2130 2019-01-09 John Darrington <john@darrington.wattle.id.au>
2132 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
2134 -dis.c (opr_emit_disassembly): Do not omit an index if it is
2137 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
2139 * configure: Regenerate.
2141 2019-01-07 Alan Modra <amodra@gmail.com>
2143 * configure: Regenerate.
2144 * po/POTFILES.in: Regenerate.
2146 2019-01-03 John Darrington <john@darrington.wattle.id.au>
2148 * s12z-opc.c: New file.
2149 * s12z-opc.h: New file.
2150 * s12z-dis.c: Removed all code not directly related to display
2151 of instructions. Used the interface provided by the new files
2153 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
2154 * Makefile.in: Regenerate.
2155 * configure.ac (bfd_s12z_arch): Correct the dependencies.
2156 * configure: Regenerate.
2158 2019-01-01 Alan Modra <amodra@gmail.com>
2160 Update year range in copyright notice of all files.
2162 For older changes see ChangeLog-2018
2164 Copyright (C) 2019 Free Software Foundation, Inc.
2166 Copying and distribution of this file, with or without modification,
2167 are permitted in any medium without royalty provided the copyright
2168 notice and this notice are preserved.
2174 version-control: never