opcodes/ChangeLog

   1 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
   2
   3         * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
   4         (aarch64_opcode_table): Add data gathering hint mnemonic.
   5         * opcodes/aarch64-dis-2.c: Account for new instruction.
   6
   7 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
   8
   9         * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
  10
  11
  12 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
  13
  14         * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
  15         aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
  16         aarch64_feature_f64mm): New feature sets.
  17         (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
  18         F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
  19         instructions.
  20         (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
  21         macros.
  22         (QL_MMLA64, OP_SVE_SBB): New qualifiers.
  23         (OP_SVE_QQQ): New qualifier.
  24         (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
  25         F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
  26         the movprfx constraint.
  27         (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
  28         (aarch64_opcode_table): Define new instructions smmla,
  29         ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
  30         uzip{1/2}, trn{1/2}.
  31         * aarch64-opc.c (operand_general_constraint_met_p): Handle
  32         AARCH64_OPND_SVE_ADDR_RI_S4x32.
  33         (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
  34         * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
  35         Account for new instructions.
  36         * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
  37         S4x32 operand.
  38         * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
  39
  40 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
  41 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
  42
  43         * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
  44         Armv8.6-A.
  45         (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
  46         (neon_opcodes): Add bfloat SIMD instructions.
  47         (print_insn_coprocessor): Add new control character %b to print
  48         condition code without checking cp_num.
  49         (print_insn_neon): Account for BFloat16 instructions that have no
  50         special top-byte handling.
  51
  52 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
  53 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
  54
  55         * arm-dis.c (print_insn_coprocessor,
  56         print_insn_generic_coprocessor): Create wrapper functions around
  57         the implementation of the print_insn_coprocessor control codes.
  58         (print_insn_coprocessor_1): Original print_insn_coprocessor
  59         function that now takes which array to look at as an argument.
  60         (print_insn_arm): Use both print_insn_coprocessor and
  61         print_insn_generic_coprocessor.
  62         (print_insn_thumb32): As above.
  63
  64 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
  65 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
  66
  67         * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
  68         in reglane special case.
  69         * aarch64-dis-2.c (aarch64_opcode_lookup_1,
  70         aarch64_find_next_opcode): Account for new instructions.
  71         * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
  72         in reglane special case.
  73         * aarch64-opc.c (struct operand_qualifier_data): Add data for
  74         new AARCH64_OPND_QLF_S_2H qualifier.
  75         * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
  76         QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
  77         (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
  78         sets.
  79         (BFLOAT_SVE, BFLOAT): New feature set macros.
  80         (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
  81         instructions.
  82         (aarch64_opcode_table): Define new instructions bfdot,
  83         bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
  84         bfcvtn2, bfcvt.
  85
  86 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
  87 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
  88
  89         * aarch64-tbl.h (ARMV8_6): New macro.
  90
  91 2019-11-07  Jan Beulich  <jbeulich@suse.com>
  92
  93         * i386-dis.c (prefix_table): Add mcommit.
  94         (rm_table): Add rdpru.
  95         * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
  96         CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
  97         (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
  98         * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
  99         (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
 100         * i386-opc.tbl (mcommit, rdpru): New.
 101         * i386-init.h, i386-tbl.h: Re-generate.
 102
 103 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 104
 105         * i386-dis.c (OP_Mwait): Drop local variable "names", use
 106         "names32" instead.
 107         (OP_Monitor): Drop local variable "op1_names", re-purpose
 108         "names" for it instead, and replace former "names" uses by
 109         "names32" ones.
 110
 111 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 112
 113         PR/gas 25167
 114         * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
 115         operand-less forms.
 116         * opcodes/i386-tbl.h: Re-generate.
 117
 118 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 119
 120         * i386-dis.c (OP_Mwaitx): Delete.
 121         (prefix_table): Use OP_Mwait for mwaitx entry.
 122         (OP_Mwait): Also handle mwaitx.
 123
 124 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 125
 126         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
 127         PREFIX_0F01_REG_7_MOD_3_RM_3): New.
 128         (prefix_table): Add respective entries.
 129         (rm_table): Link to those entries.
 130
 131 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 132
 133         * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
 134         (REG_0F1C_P_0_MOD_0): ... this.
 135         (REG_0F1E_MOD_3): Rename to ...
 136         (REG_0F1E_P_1_MOD_3): ... this.
 137         (RM_0F01_REG_5): Rename to ...
 138         (RM_0F01_REG_5_MOD_3): ... this.
 139         (RM_0F01_REG_7): Rename to ...
 140         (RM_0F01_REG_7_MOD_3): ... this.
 141         (RM_0F1E_MOD_3_REG_7): Rename to ...
 142         (RM_0F1E_P_1_MOD_3_REG_7): ... this.
 143         (RM_0FAE_REG_6): Rename to ...
 144         (RM_0FAE_REG_6_MOD_3_P_0): ... this.
 145         (RM_0FAE_REG_7): Rename to ...
 146         (RM_0FAE_REG_7_MOD_3): ... this.
 147         (PREFIX_MOD_0_0F01_REG_5): Rename to ...
 148         (PREFIX_0F01_REG_5_MOD_0): ... this.
 149         (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
 150         (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
 151         (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
 152         (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
 153         (PREFIX_0FAE_REG_0): Rename to ...
 154         (PREFIX_0FAE_REG_0_MOD_3): ... this.
 155         (PREFIX_0FAE_REG_1): Rename to ...
 156         (PREFIX_0FAE_REG_1_MOD_3): ... this.
 157         (PREFIX_0FAE_REG_2): Rename to ...
 158         (PREFIX_0FAE_REG_2_MOD_3): ... this.
 159         (PREFIX_0FAE_REG_3): Rename to ...
 160         (PREFIX_0FAE_REG_3_MOD_3): ... this.
 161         (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
 162         (PREFIX_0FAE_REG_4_MOD_0): ... this.
 163         (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
 164         (PREFIX_0FAE_REG_4_MOD_3): ... this.
 165         (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
 166         (PREFIX_0FAE_REG_5_MOD_0): ... this.
 167         (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
 168         (PREFIX_0FAE_REG_5_MOD_3): ... this.
 169         (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
 170         (PREFIX_0FAE_REG_6_MOD_0): ... this.
 171         (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
 172         (PREFIX_0FAE_REG_6_MOD_3): ... this.
 173         (PREFIX_0FAE_REG_7): Rename to ...
 174         (PREFIX_0FAE_REG_7_MOD_0): ... this.
 175         (PREFIX_MOD_0_0FC3): Rename to ...
 176         (PREFIX_0FC3_MOD_0): ... this.
 177         (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
 178         (PREFIX_0FC7_REG_6_MOD_0): ... this.
 179         (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
 180         (PREFIX_0FC7_REG_6_MOD_3): ... this.
 181         (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
 182         (PREFIX_0FC7_REG_7_MOD_3): ... this.
 183         (reg_table, prefix_table, mod_table, rm_table): Adjust
 184         accordingly.
 185
 186 2019-11-04  Nick Clifton  <nickc@redhat.com>
 187
 188         * v850-dis.c (get_v850_sreg_name): New function.  Returns the name
 189         of a v850 system register.  Move the v850_sreg_names array into
 190         this function.
 191         (get_v850_reg_name): Likewise for ordinary register names.
 192         (get_v850_vreg_name): Likewise for vector register names.
 193         (get_v850_cc_name): Likewise for condition codes.
 194         * get_v850_float_cc_name): Likewise for floating point condition
 195         codes.
 196         (get_v850_cacheop_name): Likewise for cache-ops.
 197         (get_v850_prefop_name): Likewise for pref-ops.
 198         (disassemble): Use the new accessor functions.
 199
 200 2019-10-30  Delia Burduv   <delia.burduv@arm.com>
 201
 202         * aarch64-opc.c (print_immediate_offset_address): Don't print the
 203         immediate for the writeback form of ldraa/ldrab if it is 0.
 204         * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
 205         * aarch64-opc-2.c: Regenerated.
 206
 207 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 208
 209         * i386-gen.c (operand_type_shorthands): Delete.
 210         (operand_type_init): Expand previous shorthands.
 211         (set_bitfield_from_shorthand): Rename back to ...
 212         (set_bitfield_from_cpu_flag_init): ... this.  Drop processing
 213         of operand_type_init[].
 214         (set_bitfield): Adjust call to the above function.
 215         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
 216         RegXMM, RegYMM, RegZMM): Define.
 217         * i386-reg.tbl: Expand prior shorthands.
 218
 219 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 220
 221         * i386-gen.c (output_i386_opcode): Change order of fields
 222         emitted to output.
 223         * i386-opc.h (struct insn_template): Move operands field.
 224         Convert extension_opcode field to unsigned short.
 225         * i386-tbl.h: Re-generate.
 226
 227 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 228
 229         * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
 230         of W.
 231         * i386-opc.h (W): Extend comment.
 232         * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
 233         general purpose variants not allowing for byte operands.
 234         * i386-tbl.h: Re-generate.
 235
 236 2019-10-29  Nick Clifton  <nickc@redhat.com>
 237
 238         * tic30-dis.c (print_branch): Correct size of operand array.
 239
 240 2019-10-29  Nick Clifton  <nickc@redhat.com>
 241
 242         * d30v-dis.c (print_insn): Check that operand index is valid
 243         before attempting to access the operands array.
 244
 245 2019-10-29  Nick Clifton  <nickc@redhat.com>
 246
 247         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
 248         locating the bit to be tested.
 249
 250 2019-10-29  Nick Clifton  <nickc@redhat.com>
 251
 252         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
 253         values.
 254         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
 255         (print_insn_s12z):  Check for illegal size values.
 256
 257 2019-10-28  Nick Clifton  <nickc@redhat.com>
 258
 259         * csky-dis.c (csky_chars_to_number): Check for a negative
 260         count. Use an unsigned integer to construct the return value.
 261
 262 2019-10-28  Nick Clifton  <nickc@redhat.com>
 263
 264         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
 265         operand buffer.  Set value to 15 not 13.
 266         (get_register_operand): Use OPERAND_BUFFER_LEN.
 267         (get_indirect_operand): Likewise.
 268         (print_two_operand): Likewise.
 269         (print_three_operand): Likewise.
 270         (print_oar_insn): Likewise.
 271
 272 2019-10-28  Nick Clifton  <nickc@redhat.com>
 273
 274         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
 275         (bit_extract_simple): Likewise.
 276         (bit_copy): Likewise.
 277         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
 278         index_offset array are not accessed.
 279
 280 2019-10-28  Nick Clifton  <nickc@redhat.com>
 281
 282         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
 283         operand.
 284
 285 2019-10-25  Nick Clifton  <nickc@redhat.com>
 286
 287         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
 288         access to opcodes.op array element.
 289
 290 2019-10-23  Nick Clifton  <nickc@redhat.com>
 291
 292         * rx-dis.c (get_register_name): Fix spelling typo in error
 293         message.
 294         (get_condition_name, get_flag_name, get_double_register_name)
 295         (get_double_register_high_name, get_double_register_low_name)
 296         (get_double_control_register_name, get_double_condition_name)
 297         (get_opsize_name, get_size_name): Likewise.
 298
 299 2019-10-22  Nick Clifton  <nickc@redhat.com>
 300
 301         * rx-dis.c (get_size_name): New function.  Provides safe
 302         access to name array.
 303         (get_opsize_name): Likewise.
 304         (print_insn_rx): Use the accessor functions.
 305
 306 2019-10-16  Nick Clifton  <nickc@redhat.com>
 307
 308         * rx-dis.c (get_register_name): New function.  Provides safe
 309         access to name array.
 310         (get_condition_name, get_flag_name, get_double_register_name)
 311         (get_double_register_high_name, get_double_register_low_name)
 312         (get_double_control_register_name, get_double_condition_name):
 313         Likewise.
 314         (print_insn_rx): Use the accessor functions.
 315
 316 2019-10-09  Nick Clifton  <nickc@redhat.com>
 317
 318         PR 25041
 319         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
 320         instructions.
 321
 322 2019-10-07  Jan Beulich  <jbeulich@suse.com>
 323
 324         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
 325         (cmpsd): Likewise. Move EsSeg to other operand.
 326         * opcodes/i386-tbl.h: Re-generate.
 327
 328 2019-09-23  Alan Modra  <amodra@gmail.com>
 329
 330         * m68k-dis.c: Include cpu-m68k.h
 331
 332 2019-09-23  Alan Modra  <amodra@gmail.com>
 333
 334         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
 335         "elf/mips.h" earlier.
 336
 337 2018-09-20  Jan Beulich  <jbeulich@suse.com>
 338
 339         PR gas/25012
 340         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 341         with SReg operand.
 342         * i386-tbl.h: Re-generate.
 343
 344 2019-09-18  Alan Modra  <amodra@gmail.com>
 345
 346         * arc-ext.c: Update throughout for bfd section macro changes.
 347
 348 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 349
 350         * Makefile.in: Re-generate.
 351         * configure: Re-generate.
 352
 353 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 354
 355         * riscv-opc.c (riscv_opcodes): Change subset field
 356         to insn_class field for all instructions.
 357         (riscv_insn_types): Likewise.
 358
 359 2019-09-16  Phil Blundell  <pb@pbcl.net>
 360
 361         * configure: Regenerated.
 362
 363 2019-09-10  Miod Vallat  <miod@online.fr>
 364
 365         PR 24982
 366         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 367
 368 2019-09-09  Phil Blundell  <pb@pbcl.net>
 369
 370         binutils 2.33 branch created.
 371
 372 2019-09-03  Nick Clifton  <nickc@redhat.com>
 373
 374         PR 24961
 375         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 376         greater than zero before indexing via (bufcnt -1).
 377
 378 2019-09-03  Nick Clifton  <nickc@redhat.com>
 379
 380         PR 24958
 381         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 382         (MAX_SPEC_REG_NAME_LEN): Define.
 383         (struct mmix_dis_info): Use defined constants for array lengths.
 384         (get_reg_name): New function.
 385         (get_sprec_reg_name): New function.
 386         (print_insn_mmix): Use new functions.
 387
 388 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 389
 390         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 391         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 392         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 393
 394 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 395
 396         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 397         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 398         (aarch64_sys_reg_supported_p): Update checks for the above.
 399
 400 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 401
 402         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 403         cases MVE_SQRSHRL and MVE_UQRSHLL.
 404         (print_insn_mve): Add case for specifier 'k' to check
 405         specific bit of the instruction.
 406
 407 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 408
 409         PR 24854
 410         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 411         encountering an unknown machine type.
 412         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 413         cases return -1 rather than calling abort.
 414
 415 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 416
 417         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 418         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 419         IgnoreSize.
 420         * i386-tbl.h: Re-generate.
 421
 422 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 423
 424         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 425         instructions.
 426
 427 2019-07-30  Mel Chen <mel.chen@sifive.com>
 428
 429         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 430         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 431
 432         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 433         fscsr.
 434
 435 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 436
 437         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 438         and MPY class instructions.
 439         (parse_option): Add nps400 option.
 440         (print_arc_disassembler_options): Add nps400 info.
 441
 442 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 443
 444         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 445         (bspop): Likewise.
 446         (modapp): Likewise.
 447         * arc-opc.c (RAD_CHK): Add.
 448         * arc-tbl.h: Regenerate.
 449
 450 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 451
 452         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 453         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 454
 455 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 456
 457         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 458         instructions as UNPREDICTABLE.
 459
 460 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 461
 462         * bpf-desc.c: Regenerated.
 463
 464 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 465
 466         * i386-gen.c (static_assert): Define.
 467         (main): Use it.
 468         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 469         (Opcode_Modifier_Num): ... this.
 470         (Mem): Delete.
 471
 472 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 473
 474         * i386-gen.c (operand_types): Move RegMem ...
 475         (opcode_modifiers): ... here.
 476         * i386-opc.h (RegMem): Move to opcode modifer enum.
 477         (union i386_operand_type): Move regmem field ...
 478         (struct i386_opcode_modifier): ... here.
 479         * i386-opc.tbl (RegMem): Define.
 480         (mov, movq): Move RegMem on segment, control, debug, and test
 481         register flavors.
 482         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 483         to non-SSE2AVX flavor.
 484         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 485         Move RegMem on register only flavors. Drop IgnoreSize from
 486         legacy encoding flavors.
 487         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 488         flavors.
 489         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 490         register only flavors.
 491         (vmovd): Move RegMem and drop IgnoreSize on register only
 492         flavor. Change opcode and operand order to store form.
 493         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 494
 495 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 496
 497         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 498         entries.
 499         * i386-opc.h (SReg2, SReg3): Replace by ...
 500         (SReg): ... this.
 501         (union i386_operand_type): Replace sreg fields.
 502         * i386-opc.tbl (mov, ): Use SReg.
 503         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 504         register flavors.
 505         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 506         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 507
 508 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 509
 510         * bpf-desc.c: Regenerate.
 511         * bpf-opc.c: Likewise.
 512         * bpf-opc.h: Likewise.
 513
 514 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 515
 516         * bpf-desc.c: Regenerate.
 517         * bpf-opc.c: Likewise.
 518
 519 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 520
 521         * arm-dis.c (print_insn_coprocessor): Rename index to
 522         index_operand.
 523
 524 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 525
 526         * riscv-opc.c (riscv_insn_types): Add r4 type.
 527
 528         * riscv-opc.c (riscv_insn_types): Add b and j type.
 529
 530         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 531         format for sb type and correct s type.
 532
 533 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 534
 535         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 536         SVE FMOV alias of FCPY.
 537
 538 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 539
 540         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 541         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 542
 543 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 544
 545         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 546         registers in an instruction prefixed by MOVPRFX.
 547
 548 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 549
 550         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 551         sve_size_13 icode to account for variant behaviour of
 552         pmull{t,b}.
 553         * aarch64-dis-2.c: Regenerate.
 554         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 555         sve_size_13 icode to account for variant behaviour of
 556         pmull{t,b}.
 557         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 558         (OP_SVE_VVV_Q_D): Add new qualifier.
 559         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 560         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 561         AES and those not.
 562
 563 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 564
 565         * opcodes/i386-gen.c (operand_type_init): Remove
 566         OPERAND_TYPE_VEC_IMM4 entry.
 567         (operand_types): Remove Vec_Imm4.
 568         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 569         (union i386_operand_type): Remove vec_imm4.
 570         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 571         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 572
 573 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 574
 575         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 576         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 577         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 578         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 579         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 580         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 581         * i386-tbl.h: Re-generate.
 582
 583 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 584
 585         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 586         register operands.
 587         * i386-tbl.h: Re-generate.
 588
 589 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 590
 591         * i386-opc.tbl (C): New.
 592         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 593         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 594         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 595         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 596         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 597         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 598         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 599         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 600         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 601         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 602         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 603         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 604         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 605         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 606         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 607         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 608         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 609         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 610         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 611         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 612         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 613         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 614         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 615         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 616         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 617         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 618         flavors.
 619         * i386-tbl.h: Re-generate.
 620
 621 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 622
 623         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 624         register operands.
 625         * i386-tbl.h: Re-generate.
 626
 627 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 628
 629         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 630         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 631         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 632         * i386-tbl.h: Re-generate.
 633
 634 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 635
 636         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 637         Disp8MemShift from register only templates.
 638         * i386-tbl.h: Re-generate.
 639
 640 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 641
 642         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 643         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 644         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 645         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 646         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 647         EVEX_W_0F11_P_3_M_1): Delete.
 648         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 649         EVEX_W_0F11_P_3): New.
 650         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 651         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 652         MOD_EVEX_0F11_PREFIX_3 table entries.
 653         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 654         PREFIX_EVEX_0F11 table entries.
 655         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 656         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 657         EVEX_W_0F11_P_3_M_{0,1} table entries.
 658
 659 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 660
 661         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 662         Delete.
 663
 664 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 665
 666         PR binutils/24719
 667         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 668         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 669         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 670         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 671         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 672         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 673         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 674         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 675         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 676         PREFIX_EVEX_0F38C6_REG_6 entries.
 677         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 678         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 679         EVEX_W_0F38C7_R_6_P_2 entries.
 680         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 681         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 682         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 683         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 684         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 685         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 686         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 687
 688 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 689
 690         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 691         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 692         VEX_LEN_0F2D_P_3): Delete.
 693         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 694         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 695         (prefix_table): ... here.
 696
 697 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 698
 699         * i386-dis.c (Iq): Delete.
 700         (Id): New.
 701         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 702         TBM insns.
 703         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 704         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 705         (OP_E_memory): Also honor needindex when deciding whether an
 706         address size prefix needs printing.
 707         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 708
 709 2019-06-26  Jim Wilson  <jimw@sifive.com>
 710
 711         PR binutils/24739
 712         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 713         Set info->display_endian to info->endian_code.
 714
 715 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 716
 717         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 718         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 719         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 720         OPERAND_TYPE_ACC64 entries.
 721         * i386-init.h: Re-generate.
 722
 723 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 724
 725         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 726         Delete.
 727         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 728         of dqa_mode.
 729         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 730         entries here.
 731         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 732         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 733
 734 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 735
 736         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 737         variables.
 738
 739 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 740
 741         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 742         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 743         movnti.
 744         * i386-opc.tbl (movnti): Add IgnoreSize.
 745         * i386-tbl.h: Re-generate.
 746
 747 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 748
 749         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 750         * i386-tbl.h: Re-generate.
 751
 752 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 753
 754         * i386-dis-evex.h: Break into ...
 755         * i386-dis-evex-len.h: New file.
 756         * i386-dis-evex-mod.h: Likewise.
 757         * i386-dis-evex-prefix.h: Likewise.
 758         * i386-dis-evex-reg.h: Likewise.
 759         * i386-dis-evex-w.h: Likewise.
 760         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 761         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 762         i386-dis-evex-mod.h.
 763
 764 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 765
 766         PR binutils/24700
 767         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 768         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 769         EVEX_W_0F385B_P_2.
 770         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 771         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 772         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 773         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 774         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 775         EVEX_LEN_0F385B_P_2_W_1.
 776         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 777         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 778         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 779         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 780         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 781         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 782         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 783         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 784         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 785         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 786
 787 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 788
 789         PR binutils/24691
 790         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 791         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 792         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 793         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 794         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 795         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 796         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 797         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 798         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 799         EVEX_LEN_0F3A43_P_2_W_1.
 800         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 801         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 802         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 803         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 804         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 805         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 806         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 807         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 808         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 809         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 810         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 811         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 812
 813 2019-06-14  Nick Clifton  <nickc@redhat.com>
 814
 815         * po/fr.po; Updated French translation.
 816
 817 2019-06-13  Stafford Horne  <shorne@gmail.com>
 818
 819         * or1k-asm.c: Regenerated.
 820         * or1k-desc.c: Regenerated.
 821         * or1k-desc.h: Regenerated.
 822         * or1k-dis.c: Regenerated.
 823         * or1k-ibld.c: Regenerated.
 824         * or1k-opc.c: Regenerated.
 825         * or1k-opc.h: Regenerated.
 826         * or1k-opinst.c: Regenerated.
 827
 828 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 829
 830         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 831
 832 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 833
 834         PR binutils/24633
 835         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 836         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 837         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 838         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 839         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 840         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 841         EVEX_LEN_0F3A1B_P_2_W_1.
 842         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 843         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 844         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 845         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 846         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 847         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 848         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 849         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 850
 851 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 852
 853         PR binutils/24626
 854         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 855         EVEX.vvvv when disassembling VEX and EVEX instructions.
 856         (OP_VEX): Set vex.register_specifier to 0 after readding
 857         vex.register_specifier.
 858         (OP_Vex_2src_1): Likewise.
 859         (OP_Vex_2src_2): Likewise.
 860         (OP_LWP_E): Likewise.
 861         (OP_EX_Vex): Don't check vex.register_specifier.
 862         (OP_XMM_Vex): Likewise.
 863
 864 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 865             Lili Cui  <lili.cui@intel.com>
 866
 867         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 868         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 869         instructions.
 870         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 871         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 872         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 873         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 874         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 875         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 876         * i386-init.h: Regenerated.
 877         * i386-tbl.h: Likewise.
 878
 879 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 880             Lili Cui  <lili.cui@intel.com>
 881
 882         * doc/c-i386.texi: Document enqcmd.
 883         * testsuite/gas/i386/enqcmd-intel.d: New file.
 884         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 885         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 886         * testsuite/gas/i386/enqcmd.d: Likewise.
 887         * testsuite/gas/i386/enqcmd.s: Likewise.
 888         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 889         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 890         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 891         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 892         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 893         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 894         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 895         and x86-64-enqcmd.
 896
 897 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 898
 899         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 900
 901 2019-06-03  Alan Modra  <amodra@gmail.com>
 902
 903         * ppc-dis.c (prefix_opcd_indices): Correct size.
 904
 905 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 906
 907         PR gas/24625
 908         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 909         Disp8ShiftVL.
 910         * i386-tbl.h: Regenerated.
 911
 912 2019-05-24  Alan Modra  <amodra@gmail.com>
 913
 914         * po/POTFILES.in: Regenerate.
 915
 916 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 917             Alan Modra  <amodra@gmail.com>
 918
 919         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 920         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 921         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 922         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 923         XTOP>): Define and add entries.
 924         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 925         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 926         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 927         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 928
 929 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 930             Alan Modra  <amodra@gmail.com>
 931
 932         * ppc-dis.c (ppc_opts): Add "future" entry.
 933         (PREFIX_OPCD_SEGS): Define.
 934         (prefix_opcd_indices): New array.
 935         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 936         (lookup_prefix): New function.
 937         (print_insn_powerpc): Handle 64-bit prefix instructions.
 938         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 939         (PMRR, POWERXX): Define.
 940         (prefix_opcodes): New instruction table.
 941         (prefix_num_opcodes): New constant.
 942
 943 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 944
 945         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 946         * configure: Regenerated.
 947         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 948         and cpu/bpf.opc.
 949         (HFILES): Add bpf-desc.h and bpf-opc.h.
 950         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 951         bpf-ibld.c and bpf-opc.c.
 952         (BPF_DEPS): Define.
 953         * Makefile.in: Regenerated.
 954         * disassemble.c (ARCH_bpf): Define.
 955         (disassembler): Add case for bfd_arch_bpf.
 956         (disassemble_init_for_target): Likewise.
 957         (enum epbf_isa_attr): Define.
 958         * disassemble.h: extern print_insn_bpf.
 959         * bpf-asm.c: Generated.
 960         * bpf-opc.h: Likewise.
 961         * bpf-opc.c: Likewise.
 962         * bpf-ibld.c: Likewise.
 963         * bpf-dis.c: Likewise.
 964         * bpf-desc.h: Likewise.
 965         * bpf-desc.c: Likewise.
 966
 967 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 968
 969         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 970         and VMSR with the new operands.
 971
 972 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 973
 974         * arm-dis.c (enum mve_instructions): New enum
 975         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 976         and cneg.
 977         (mve_opcodes): New instructions as above.
 978         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 979         csneg and csel.
 980         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 981
 982 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 983
 984         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 985         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 986         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 987         uqshl, urshrl and urshr.
 988         (is_mve_okay_in_it): Add new instructions to TRUE list.
 989         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 990         (print_insn_mve): Updated to accept new %j,
 991         %<bitfield>m and %<bitfield>n patterns.
 992
 993 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 994
 995         * mips-opc.c (mips_builtin_opcodes): Change source register
 996         constraint for DAUI.
 997
 998 2019-05-20  Nick Clifton  <nickc@redhat.com>
 999
1000         * po/fr.po: Updated French translation.
1001
1002 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1003             Michael Collison <michael.collison@arm.com>
1004
1005         * arm-dis.c (thumb32_opcodes): Add new instructions.
1006         (enum mve_instructions): Likewise.
1007         (enum mve_undefined): Add new reasons.
1008         (is_mve_encoding_conflict): Handle new instructions.
1009         (is_mve_undefined): Likewise.
1010         (is_mve_unpredictable): Likewise.
1011         (print_mve_undefined): Likewise.
1012         (print_mve_size): Likewise.
1013
1014 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1015             Michael Collison <michael.collison@arm.com>
1016
1017         * arm-dis.c (thumb32_opcodes): Add new instructions.
1018         (enum mve_instructions): Likewise.
1019         (is_mve_encoding_conflict): Handle new instructions.
1020         (is_mve_undefined): Likewise.
1021         (is_mve_unpredictable): Likewise.
1022         (print_mve_size): Likewise.
1023
1024 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1025             Michael Collison <michael.collison@arm.com>
1026
1027         * arm-dis.c (thumb32_opcodes): Add new instructions.
1028         (enum mve_instructions): Likewise.
1029         (is_mve_encoding_conflict): Likewise.
1030         (is_mve_unpredictable): Likewise.
1031         (print_mve_size): Likewise.
1032
1033 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1034             Michael Collison <michael.collison@arm.com>
1035
1036         * arm-dis.c (thumb32_opcodes): Add new instructions.
1037         (enum mve_instructions): Likewise.
1038         (is_mve_encoding_conflict): Handle new instructions.
1039         (is_mve_undefined): Likewise.
1040         (is_mve_unpredictable): Likewise.
1041         (print_mve_size): Likewise.
1042
1043 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1044             Michael Collison <michael.collison@arm.com>
1045
1046         * arm-dis.c (thumb32_opcodes): Add new instructions.
1047         (enum mve_instructions): Likewise.
1048         (is_mve_encoding_conflict): Handle new instructions.
1049         (is_mve_undefined): Likewise.
1050         (is_mve_unpredictable): Likewise.
1051         (print_mve_size): Likewise.
1052         (print_insn_mve): Likewise.
1053
1054 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1055             Michael Collison <michael.collison@arm.com>
1056
1057         * arm-dis.c (thumb32_opcodes): Add new instructions.
1058         (print_insn_thumb32): Handle new instructions.
1059
1060 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1061             Michael Collison <michael.collison@arm.com>
1062
1063         * arm-dis.c (enum mve_instructions): Add new instructions.
1064         (enum mve_undefined): Add new reasons.
1065         (is_mve_encoding_conflict): Handle new instructions.
1066         (is_mve_undefined): Likewise.
1067         (is_mve_unpredictable): Likewise.
1068         (print_mve_undefined): Likewise.
1069         (print_mve_size): Likewise.
1070         (print_mve_shift_n): Likewise.
1071         (print_insn_mve): Likewise.
1072
1073 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1074             Michael Collison <michael.collison@arm.com>
1075
1076         * arm-dis.c (enum mve_instructions): Add new instructions.
1077         (is_mve_encoding_conflict): Handle new instructions.
1078         (is_mve_unpredictable): Likewise.
1079         (print_mve_rotate): Likewise.
1080         (print_mve_size): Likewise.
1081         (print_insn_mve): Likewise.
1082
1083 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1084             Michael Collison <michael.collison@arm.com>
1085
1086         * arm-dis.c (enum mve_instructions): Add new instructions.
1087         (is_mve_encoding_conflict): Handle new instructions.
1088         (is_mve_unpredictable): Likewise.
1089         (print_mve_size): Likewise.
1090         (print_insn_mve): Likewise.
1091
1092 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1093             Michael Collison <michael.collison@arm.com>
1094
1095         * arm-dis.c (enum mve_instructions): Add new instructions.
1096         (enum mve_undefined): Add new reasons.
1097         (is_mve_encoding_conflict): Handle new instructions.
1098         (is_mve_undefined): Likewise.
1099         (is_mve_unpredictable): Likewise.
1100         (print_mve_undefined): Likewise.
1101         (print_mve_size): Likewise.
1102         (print_insn_mve): Likewise.
1103
1104 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1105             Michael Collison <michael.collison@arm.com>
1106
1107         * arm-dis.c (enum mve_instructions): Add new instructions.
1108         (is_mve_encoding_conflict): Handle new instructions.
1109         (is_mve_undefined): Likewise.
1110         (is_mve_unpredictable): Likewise.
1111         (print_mve_size): Likewise.
1112         (print_insn_mve): Likewise.
1113
1114 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1115             Michael Collison <michael.collison@arm.com>
1116
1117         * arm-dis.c (enum mve_instructions): Add new instructions.
1118         (enum mve_unpredictable): Add new reasons.
1119         (enum mve_undefined): Likewise.
1120         (is_mve_okay_in_it): Handle new isntructions.
1121         (is_mve_encoding_conflict): Likewise.
1122         (is_mve_undefined): Likewise.
1123         (is_mve_unpredictable): Likewise.
1124         (print_mve_vmov_index): Likewise.
1125         (print_simd_imm8): Likewise.
1126         (print_mve_undefined): Likewise.
1127         (print_mve_unpredictable): Likewise.
1128         (print_mve_size): Likewise.
1129         (print_insn_mve): Likewise.
1130
1131 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1132             Michael Collison <michael.collison@arm.com>
1133
1134         * arm-dis.c (enum mve_instructions): Add new instructions.
1135         (enum mve_unpredictable): Add new reasons.
1136         (enum mve_undefined): Likewise.
1137         (is_mve_encoding_conflict): Handle new instructions.
1138         (is_mve_undefined): Likewise.
1139         (is_mve_unpredictable): Likewise.
1140         (print_mve_undefined): Likewise.
1141         (print_mve_unpredictable): Likewise.
1142         (print_mve_rounding_mode): Likewise.
1143         (print_mve_vcvt_size): Likewise.
1144         (print_mve_size): Likewise.
1145         (print_insn_mve): Likewise.
1146
1147 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1148             Michael Collison <michael.collison@arm.com>
1149
1150         * arm-dis.c (enum mve_instructions): Add new instructions.
1151         (enum mve_unpredictable): Add new reasons.
1152         (enum mve_undefined): Likewise.
1153         (is_mve_undefined): Handle new instructions.
1154         (is_mve_unpredictable): Likewise.
1155         (print_mve_undefined): Likewise.
1156         (print_mve_unpredictable): Likewise.
1157         (print_mve_size): Likewise.
1158         (print_insn_mve): Likewise.
1159
1160 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1161             Michael Collison <michael.collison@arm.com>
1162
1163         * arm-dis.c (enum mve_instructions): Add new instructions.
1164         (enum mve_undefined): Add new reasons.
1165         (insns): Add new instructions.
1166         (is_mve_encoding_conflict):
1167         (print_mve_vld_str_addr): New print function.
1168         (is_mve_undefined): Handle new instructions.
1169         (is_mve_unpredictable): Likewise.
1170         (print_mve_undefined): Likewise.
1171         (print_mve_size): Likewise.
1172         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1173         (print_insn_mve):  Handle new operands.
1174
1175 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1176             Michael Collison <michael.collison@arm.com>
1177
1178         * arm-dis.c (enum mve_instructions): Add new instructions.
1179         (enum mve_unpredictable): Add new reasons.
1180         (is_mve_encoding_conflict): Handle new instructions.
1181         (is_mve_unpredictable): Likewise.
1182         (mve_opcodes): Add new instructions.
1183         (print_mve_unpredictable): Handle new reasons.
1184         (print_mve_register_blocks): New print function.
1185         (print_mve_size): Handle new instructions.
1186         (print_insn_mve): Likewise.
1187
1188 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1189             Michael Collison <michael.collison@arm.com>
1190
1191         * arm-dis.c (enum mve_instructions): Add new instructions.
1192         (enum mve_unpredictable): Add new reasons.
1193         (enum mve_undefined): Likewise.
1194         (is_mve_encoding_conflict): Handle new instructions.
1195         (is_mve_undefined): Likewise.
1196         (is_mve_unpredictable): Likewise.
1197         (coprocessor_opcodes): Move NEON VDUP from here...
1198         (neon_opcodes): ... to here.
1199         (mve_opcodes): Add new instructions.
1200         (print_mve_undefined):  Handle new reasons.
1201         (print_mve_unpredictable): Likewise.
1202         (print_mve_size): Handle new instructions.
1203         (print_insn_neon): Handle vdup.
1204         (print_insn_mve): Handle new operands.
1205
1206 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1207             Michael Collison <michael.collison@arm.com>
1208
1209         * arm-dis.c (enum mve_instructions): Add new instructions.
1210         (enum mve_unpredictable): Add new values.
1211         (mve_opcodes): Add new instructions.
1212         (vec_condnames): New array with vector conditions.
1213         (mve_predicatenames): New array with predicate suffixes.
1214         (mve_vec_sizename): New array with vector sizes.
1215         (enum vpt_pred_state): New enum with vector predication states.
1216         (struct vpt_block): New struct type for vpt blocks.
1217         (vpt_block_state): Global struct to keep track of state.
1218         (mve_extract_pred_mask): New helper function.
1219         (num_instructions_vpt_block): Likewise.
1220         (mark_outside_vpt_block): Likewise.
1221         (mark_inside_vpt_block): Likewise.
1222         (invert_next_predicate_state): Likewise.
1223         (update_next_predicate_state): Likewise.
1224         (update_vpt_block_state): Likewise.
1225         (is_vpt_instruction): Likewise.
1226         (is_mve_encoding_conflict): Add entries for new instructions.
1227         (is_mve_unpredictable): Likewise.
1228         (print_mve_unpredictable): Handle new cases.
1229         (print_instruction_predicate): Likewise.
1230         (print_mve_size): New function.
1231         (print_vec_condition): New function.
1232         (print_insn_mve): Handle vpt blocks and new print operands.
1233
1234 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1235
1236         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1237         8, 14 and 15 for Armv8.1-M Mainline.
1238
1239 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1240             Michael Collison <michael.collison@arm.com>
1241
1242         * arm-dis.c (enum mve_instructions): New enum.
1243         (enum mve_unpredictable): Likewise.
1244         (enum mve_undefined): Likewise.
1245         (struct mopcode32): New struct.
1246         (is_mve_okay_in_it): New function.
1247         (is_mve_architecture): Likewise.
1248         (arm_decode_field): Likewise.
1249         (arm_decode_field_multiple): Likewise.
1250         (is_mve_encoding_conflict): Likewise.
1251         (is_mve_undefined): Likewise.
1252         (is_mve_unpredictable): Likewise.
1253         (print_mve_undefined): Likewise.
1254         (print_mve_unpredictable): Likewise.
1255         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1256         (print_insn_mve): New function.
1257         (print_insn_thumb32): Handle MVE architecture.
1258         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1259
1260 2019-05-10  Nick Clifton  <nickc@redhat.com>
1261
1262         PR 24538
1263         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1264         end of the table prematurely.
1265
1266 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1267
1268         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1269         macros for R6.
1270
1271 2019-05-11  Alan Modra  <amodra@gmail.com>
1272
1273         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1274         when -Mraw is in effect.
1275
1276 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1277
1278         * aarch64-dis-2.c: Regenerate.
1279         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1280         (OP_SVE_BBB): New variant set.
1281         (OP_SVE_DDDD): New variant set.
1282         (OP_SVE_HHH): New variant set.
1283         (OP_SVE_HHHU): New variant set.
1284         (OP_SVE_SSS): New variant set.
1285         (OP_SVE_SSSU): New variant set.
1286         (OP_SVE_SHH): New variant set.
1287         (OP_SVE_SBBU): New variant set.
1288         (OP_SVE_DSS): New variant set.
1289         (OP_SVE_DHHU): New variant set.
1290         (OP_SVE_VMV_HSD_BHS): New variant set.
1291         (OP_SVE_VVU_HSD_BHS): New variant set.
1292         (OP_SVE_VVVU_SD_BH): New variant set.
1293         (OP_SVE_VVVU_BHSD): New variant set.
1294         (OP_SVE_VVV_QHD_DBS): New variant set.
1295         (OP_SVE_VVV_HSD_BHS): New variant set.
1296         (OP_SVE_VVV_HSD_BHS2): New variant set.
1297         (OP_SVE_VVV_BHS_HSD): New variant set.
1298         (OP_SVE_VV_BHS_HSD): New variant set.
1299         (OP_SVE_VVV_SD): New variant set.
1300         (OP_SVE_VVU_BHS_HSD): New variant set.
1301         (OP_SVE_VZVV_SD): New variant set.
1302         (OP_SVE_VZVV_BH): New variant set.
1303         (OP_SVE_VZV_SD): New variant set.
1304         (aarch64_opcode_table): Add sve2 instructions.
1305
1306 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1307
1308         * aarch64-asm-2.c: Regenerated.
1309         * aarch64-dis-2.c: Regenerated.
1310         * aarch64-opc-2.c: Regenerated.
1311         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1312         for SVE_SHLIMM_UNPRED_22.
1313         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1314         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1315         operand.
1316
1317 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1318
1319         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1320         sve_size_tsz_bhs iclass encode.
1321         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1322         sve_size_tsz_bhs iclass decode.
1323
1324 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1325
1326         * aarch64-asm-2.c: Regenerated.
1327         * aarch64-dis-2.c: Regenerated.
1328         * aarch64-opc-2.c: Regenerated.
1329         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1330         for SVE_Zm4_11_INDEX.
1331         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1332         (fields): Handle SVE_i2h field.
1333         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1334         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1335
1336 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1337
1338         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1339         sve_shift_tsz_bhsd iclass encode.
1340         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1341         sve_shift_tsz_bhsd iclass decode.
1342
1343 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1344
1345         * aarch64-asm-2.c: Regenerated.
1346         * aarch64-dis-2.c: Regenerated.
1347         * aarch64-opc-2.c: Regenerated.
1348         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1349         (aarch64_encode_variant_using_iclass): Handle
1350         sve_shift_tsz_hsd iclass encode.
1351         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1352         sve_shift_tsz_hsd iclass decode.
1353         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1354         for SVE_SHRIMM_UNPRED_22.
1355         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1356         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1357         operand.
1358
1359 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1360
1361         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1362         sve_size_013 iclass encode.
1363         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1364         sve_size_013 iclass decode.
1365
1366 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1367
1368         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1369         sve_size_bh iclass encode.
1370         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1371         sve_size_bh iclass decode.
1372
1373 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1374
1375         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1376         sve_size_sd2 iclass encode.
1377         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1378         sve_size_sd2 iclass decode.
1379         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1380         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1381
1382 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1383
1384         * aarch64-asm-2.c: Regenerated.
1385         * aarch64-dis-2.c: Regenerated.
1386         * aarch64-opc-2.c: Regenerated.
1387         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1388         for SVE_ADDR_ZX.
1389         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1390         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1391
1392 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1393
1394         * aarch64-asm-2.c: Regenerated.
1395         * aarch64-dis-2.c: Regenerated.
1396         * aarch64-opc-2.c: Regenerated.
1397         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1398         for SVE_Zm3_11_INDEX.
1399         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1400         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1401         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1402         fields.
1403         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1404
1405 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1406
1407         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1408         sve_size_hsd2 iclass encode.
1409         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1410         sve_size_hsd2 iclass decode.
1411         * aarch64-opc.c (fields): Handle SVE_size field.
1412         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1413
1414 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1415
1416         * aarch64-asm-2.c: Regenerated.
1417         * aarch64-dis-2.c: Regenerated.
1418         * aarch64-opc-2.c: Regenerated.
1419         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1420         for SVE_IMM_ROT3.
1421         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1422         (fields): Handle SVE_rot3 field.
1423         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1424         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1425
1426 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1427
1428         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1429         instructions.
1430
1431 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1432
1433         * aarch64-tbl.h
1434         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1435         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1436         aarch64_feature_sve2bitperm): New feature sets.
1437         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1438         for feature set addresses.
1439         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1440         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1441
1442 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1443             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1444
1445         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1446         argument and set ASE_EVA_R6 appropriately.
1447         (set_default_mips_dis_options): Pass ISA to above.
1448         (parse_mips_dis_option): Likewise.
1449         * mips-opc.c (EVAR6): New macro.
1450         (mips_builtin_opcodes): Add llwpe, scwpe.
1451
1452 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1453
1454         * aarch64-asm-2.c: Regenerated.
1455         * aarch64-dis-2.c: Regenerated.
1456         * aarch64-opc-2.c: Regenerated.
1457         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1458         AARCH64_OPND_TME_UIMM16.
1459         (aarch64_print_operand): Likewise.
1460         * aarch64-tbl.h (QL_IMM_NIL): New.
1461         (TME): New.
1462         (_TME_INSN): New.
1463         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1464
1465 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1466
1467         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1468
1469 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1470             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1471
1472         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1473
1474 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1475
1476         * s12z-opc.h: Add extern "C" bracketing to help
1477         users who wish to use this interface in c++ code.
1478
1479 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1480
1481         * s12z-opc.c (bm_decode): Handle bit map operations with the
1482         "reserved0" mode.
1483
1484 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1485
1486         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1487         specifier.  Add entries for VLDR and VSTR of system registers.
1488         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1489         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1490         of %J and %K format specifier.
1491
1492 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1493
1494         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1495         Add new entries for VSCCLRM instruction.
1496         (print_insn_coprocessor): Handle new %C format control code.
1497
1498 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1499
1500         * arm-dis.c (enum isa): New enum.
1501         (struct sopcode32): New structure.
1502         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1503         set isa field of all current entries to ANY.
1504         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1505         Only match an entry if its isa field allows the current mode.
1506
1507 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1508
1509         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1510         CLRM.
1511         (print_insn_thumb32): Add logic to print %n CLRM register list.
1512
1513 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1514
1515         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1516         and %Q patterns.
1517
1518 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1519
1520         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1521         (print_insn_thumb32): Edit the switch case for %Z.
1522
1523 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1524
1525         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1526
1527 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1528
1529         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1530
1531 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1532
1533         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1534
1535 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1536
1537         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1538         Arm register with r13 and r15 unpredictable.
1539         (thumb32_opcodes): New instructions for bfx and bflx.
1540
1541 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1542
1543         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1544
1545 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1546
1547         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1548
1549 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1550
1551         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1552
1553 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1554
1555         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1556
1557 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1558
1559         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1560         "optr". ("operator" is a reserved word in c++).
1561
1562 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1563
1564         * aarch64-opc.c (aarch64_print_operand): Add case for
1565         AARCH64_OPND_Rt_SP.
1566         (verify_constraints): Likewise.
1567         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1568         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1569         to accept Rt|SP as first operand.
1570         (AARCH64_OPERANDS): Add new Rt_SP.
1571         * aarch64-asm-2.c: Regenerated.
1572         * aarch64-dis-2.c: Regenerated.
1573         * aarch64-opc-2.c: Regenerated.
1574
1575 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1576
1577         * aarch64-asm-2.c: Regenerated.
1578         * aarch64-dis-2.c: Likewise.
1579         * aarch64-opc-2.c: Likewise.
1580         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1581
1582 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1583
1584         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1585
1586 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1587
1588         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1589         * i386-init.h: Regenerated.
1590
1591 2019-04-07  Alan Modra  <amodra@gmail.com>
1592
1593         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1594         op_separator to control printing of spaces, comma and parens
1595         rather than need_comma, need_paren and spaces vars.
1596
1597 2019-04-07  Alan Modra  <amodra@gmail.com>
1598
1599         PR 24421
1600         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1601         (print_insn_neon, print_insn_arm): Likewise.
1602
1603 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1604
1605         * i386-dis-evex.h (evex_table): Updated to support BF16
1606         instructions.
1607         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1608         and EVEX_W_0F3872_P_3.
1609         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1610         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1611         * i386-opc.h (enum): Add CpuAVX512_BF16.
1612         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1613         * i386-opc.tbl: Add AVX512 BF16 instructions.
1614         * i386-init.h: Regenerated.
1615         * i386-tbl.h: Likewise.
1616
1617 2019-04-05  Alan Modra  <amodra@gmail.com>
1618
1619         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1620         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1621         to favour printing of "-" branch hint when using the "y" bit.
1622         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1623
1624 2019-04-05  Alan Modra  <amodra@gmail.com>
1625
1626         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1627         opcode until first operand is output.
1628
1629 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1630
1631         PR gas/24349
1632         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1633         (valid_bo_post_v2): Add support for 'at' branch hints.
1634         (insert_bo): Only error on branch on ctr.
1635         (get_bo_hint_mask): New function.
1636         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1637         for inserting 'at' branch hints.
1638         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1639         for extracting 'at' branch hints.
1640         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1641         (BOE): Delete operand.
1642         (BOM, BOP): New operands.
1643         (RM): Update value.
1644         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1645         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1646         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1647         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1648         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1649         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1650         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1651         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1652         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1653         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1654         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1655         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1656         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1657         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1658         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1659         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1660         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1661         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1662         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1663         bttarl+>: New extended mnemonics.
1664
1665 2019-03-28  Alan Modra  <amodra@gmail.com>
1666
1667         PR 24390
1668         * ppc-opc.c (BTF): Define.
1669         (powerpc_opcodes): Use for mtfsb*.
1670         * ppc-dis.c (print_insn_powerpc): Print fields with both
1671         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1672
1673 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1674
1675         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1676         (mapping_symbol_for_insn): Implement new algorithm.
1677         (print_insn): Remove duplicate code.
1678
1679 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1680
1681         * aarch64-dis.c (print_insn_aarch64):
1682         Implement override.
1683
1684 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1685
1686         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1687         order.
1688
1689 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1690
1691         * aarch64-dis.c (last_stop_offset): New.
1692         (print_insn_aarch64): Use stop_offset.
1693
1694 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1695
1696         PR gas/24359
1697         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1698         CPU_ANY_AVX2_FLAGS.
1699         * i386-init.h: Regenerated.
1700
1701 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1702
1703         PR gas/24348
1704         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1705         vmovdqu16, vmovdqu32 and vmovdqu64.
1706         * i386-tbl.h: Regenerated.
1707
1708 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1709
1710         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1711         from vstrszb, vstrszh, and vstrszf.
1712
1713 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1714
1715         * s390-opc.txt: Add instruction descriptions.
1716
1717 2019-02-08  Jim Wilson  <jimw@sifive.com>
1718
1719         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1720         <bne>: Likewise.
1721
1722 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1723
1724         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1725
1726 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1727
1728         PR binutils/23212
1729         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1730         * aarch64-opc.c (verify_elem_sd): New.
1731         (fields): Add FLD_sz entr.
1732         * aarch64-tbl.h (_SIMD_INSN): New.
1733         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1734         fmulx scalar and vector by element isns.
1735
1736 2019-02-07  Nick Clifton  <nickc@redhat.com>
1737
1738         * po/sv.po: Updated Swedish translation.
1739
1740 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1741
1742         * s390-mkopc.c (main): Accept arch13 as cpu string.
1743         * s390-opc.c: Add new instruction formats and instruction opcode
1744         masks.
1745         * s390-opc.txt: Add new arch13 instructions.
1746
1747 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1748
1749         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1750         (aarch64_opcode): Change encoding for stg, stzg
1751         st2g and st2zg.
1752         * aarch64-asm-2.c: Regenerated.
1753         * aarch64-dis-2.c: Regenerated.
1754         * aarch64-opc-2.c: Regenerated.
1755
1756 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1757
1758         * aarch64-asm-2.c: Regenerated.
1759         * aarch64-dis-2.c: Likewise.
1760         * aarch64-opc-2.c: Likewise.
1761         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1762
1763 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1764             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1765
1766         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1767         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1768         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1769         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1770         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1771         case for ldstgv_indexed.
1772         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1773         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1774         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1775         * aarch64-asm-2.c: Regenerated.
1776         * aarch64-dis-2.c: Regenerated.
1777         * aarch64-opc-2.c: Regenerated.
1778
1779 2019-01-23  Nick Clifton  <nickc@redhat.com>
1780
1781         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1782
1783 2019-01-21  Nick Clifton  <nickc@redhat.com>
1784
1785         * po/de.po: Updated German translation.
1786         * po/uk.po: Updated Ukranian translation.
1787
1788 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1789         * mips-dis.c (mips_arch_choices): Fix typo in
1790         gs464, gs464e and gs264e descriptors.
1791
1792 2019-01-19  Nick Clifton  <nickc@redhat.com>
1793
1794         * configure: Regenerate.
1795         * po/opcodes.pot: Regenerate.
1796
1797 2018-06-24  Nick Clifton  <nickc@redhat.com>
1798
1799         2.32 branch created.
1800
1801 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1802
1803         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1804         if it is null.
1805         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1806         zero.
1807
1808 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1809
1810         * configure: Regenerate.
1811
1812 2019-01-07  Alan Modra  <amodra@gmail.com>
1813
1814         * configure: Regenerate.
1815         * po/POTFILES.in: Regenerate.
1816
1817 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1818
1819         * s12z-opc.c: New file.
1820         * s12z-opc.h: New file.
1821         * s12z-dis.c: Removed all code not directly related to display
1822         of instructions.  Used the interface provided by the new files
1823         instead.
1824         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1825         * Makefile.in: Regenerate.
1826         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1827         * configure: Regenerate.
1828
1829 2019-01-01  Alan Modra  <amodra@gmail.com>
1830
1831         Update year range in copyright notice of all files.
1832
1833 For older changes see ChangeLog-2018
1834 \f
1835 Copyright (C) 2019 Free Software Foundation, Inc.
1836
1837 Copying and distribution of this file, with or without modification,
1838 are permitted in any medium without royalty provided the copyright
1839 notice and this notice are preserved.
1840
1841 Local Variables:
1842 mode: change-log
1843 left-margin: 8
1844 fill-column: 74
1845 version-control: never
1846 End: