opcodes/ChangeLog

   1 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
   2
   3         * arc-tbl.h (vewt): Allow it for ARC EM family.
   4
   5 2018-07-23  Alan Modra  <amodra@gmail.com>
   6
   7         PR 23419
   8         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
   9         opcode variants for mtspr/mfspr encodings.
  10
  11 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
  12             Maciej W. Rozycki  <macro@mips.com>
  13
  14         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
  15         loongson3a descriptors.
  16         (parse_mips_ase_option): Handle -M loongson-mmi option.
  17         (print_mips_disassembler_options): Document -M loongson-mmi.
  18         * mips-opc.c (LMMI): New macro.
  19         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
  20         instructions.
  21
  22 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  23
  24         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
  25         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
  26         IgnoreSize and [XYZ]MMword where applicable.
  27         * i386-tbl.h: Re-generate.
  28
  29 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  30
  31         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
  32         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
  33         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
  34         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
  35         * i386-tbl.h: Re-generate.
  36
  37 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  38
  39         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
  40         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
  41         VPCLMULQDQ templates into their respective AVX512VL counterparts
  42         where possible, using Disp8ShiftVL and CheckRegSize instead of
  43         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
  44         * i386-tbl.h: Re-generate.
  45
  46 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  47
  48         * i386-opc.tbl: Fold AVX512DQ templates into their respective
  49         AVX512VL counterparts where possible, using Disp8ShiftVL and
  50         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
  51         IgnoreSize) as appropriate.
  52         * i386-tbl.h: Re-generate.
  53
  54 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  55
  56         * i386-opc.tbl: Fold AVX512BW templates into their respective
  57         AVX512VL counterparts where possible, using Disp8ShiftVL and
  58         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
  59         IgnoreSize) as appropriate.
  60         * i386-tbl.h: Re-generate.
  61
  62 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  63
  64         * i386-opc.tbl: Fold AVX512CD templates into their respective
  65         AVX512VL counterparts where possible, using Disp8ShiftVL and
  66         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
  67         IgnoreSize) as appropriate.
  68         * i386-tbl.h: Re-generate.
  69
  70 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  71
  72         * i386-opc.h (DISP8_SHIFT_VL): New.
  73         * i386-opc.tbl (Disp8ShiftVL):  Define.
  74         (various): Fold AVX512VL templates into their respective
  75         AVX512F counterparts where possible, using Disp8ShiftVL and
  76         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
  77         IgnoreSize) as appropriate.
  78         * i386-tbl.h: Re-generate.
  79
  80 2018-07-19  Jan Beulich  <jbeulich@suse.com>
  81
  82         * Makefile.am: Change dependencies and rule for
  83         $(srcdir)/i386-init.h.
  84         * Makefile.in: Re-generate.
  85         * i386-gen.c (process_i386_opcodes): New local variable
  86         "marker". Drop opening of input file. Recognize marker and line
  87         number directives.
  88         * i386-opc.tbl (OPCODE_I386_H): Define.
  89         (i386-opc.h): Include it.
  90         (None): Undefine.
  91
  92 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
  93
  94         PR gas/23418
  95         * i386-opc.h (Byte): Update comments.
  96         (Word): Likewise.
  97         (Dword): Likewise.
  98         (Fword): Likewise.
  99         (Qword): Likewise.
 100         (Tbyte): Likewise.
 101         (Xmmword): Likewise.
 102         (Ymmword): Likewise.
 103         (Zmmword): Likewise.
 104         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
 105         vcvttps2uqq.
 106         * i386-tbl.h: Regenerated.
 107
 108 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
 109
 110         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
 111         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
 112         * aarch64-asm-2.c: Regenerate.
 113         * aarch64-dis-2.c: Regenerate.
 114         * aarch64-opc-2.c: Regenerate.
 115
 116 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
 117
 118         PR binutils/23192
 119         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
 120         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
 121         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
 122         sqdmulh, sqrdmulh): Use Em16.
 123
 124 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
 125
 126         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
 127         csdb together with them.
 128         (thumb32_opcodes): Likewise.
 129
 130 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 131
 132         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
 133         requiring 32-bit registers as operands 2 and 3. Improve
 134         comments.
 135         (mwait, mwaitx): Fold templates. Improve comments.
 136         OPERAND_TYPE_INOUTPORTREG.
 137         * i386-tbl.h: Re-generate.
 138
 139 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 140
 141         * i386-gen.c (operand_type_init): Remove
 142         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
 143         OPERAND_TYPE_INOUTPORTREG.
 144         * i386-init.h: Re-generate.
 145
 146 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 147
 148         * i386-opc.tbl (wrssd, wrussd): Add Dword.
 149         (wrssq, wrussq): Add Qword.
 150         * i386-tbl.h: Re-generate.
 151
 152 2018-07-11  Jan Beulich  <jbeulich@suse.com>
 153
 154         * i386-opc.h: Rename OTMax to OTNum.
 155         (OTNumOfUints): Adjust calculation.
 156         (OTUnused): Directly alias to OTNum.
 157
 158 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
 159
 160         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
 161         `reg_xys'.
 162         (lea_reg_xys): Likewise.
 163         (print_insn_loop_primitive): Rename `reg' local variable to
 164         `reg_dxy'.
 165
 166 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 167
 168         PR binutils/23242
 169         * aarch64-tbl.h (ldarh): Fix disassembly mask.
 170
 171 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
 172
 173         PR binutils/23369
 174         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
 175         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
 176
 177 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
 178
 179         PR tdep/8282
 180         * mips-dis.c (mips_option_arg_t): New enumeration.
 181         (mips_options): New variable.
 182         (disassembler_options_mips): New function.
 183         (print_mips_disassembler_options): Reimplement in terms of
 184         `disassembler_options_mips'.
 185         * arm-dis.c (disassembler_options_arm): Adapt to using the
 186         `disasm_options_and_args_t' structure.
 187         * ppc-dis.c (disassembler_options_powerpc): Likewise.
 188         * s390-dis.c (disassembler_options_s390): Likewise.
 189
 190 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 191
 192         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
 193         expected result.
 194         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
 195         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
 196         * testsuite/ld-arm/tls-longplt.d: Likewise.
 197
 198 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
 199
 200         PR binutils/23192
 201         * aarch64-asm-2.c: Regenerate.
 202         * aarch64-dis-2.c: Likewise.
 203         * aarch64-opc-2.c: Likewise.
 204         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
 205         * aarch64-opc.c (operand_general_constraint_met_p,
 206         aarch64_print_operand): Likewise.
 207         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
 208         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
 209         fmlal2, fmlsl2.
 210         (AARCH64_OPERANDS): Add Em2.
 211
 212 2018-06-26  Nick Clifton  <nickc@redhat.com>
 213
 214         * po/uk.po: Updated Ukranian translation.
 215         * po/de.po: Updated German translation.
 216         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 217
 218 2018-06-26  Nick Clifton  <nickc@redhat.com>
 219
 220         * nfp-dis.c: Fix spelling mistake.
 221
 222 2018-06-24  Nick Clifton  <nickc@redhat.com>
 223
 224         * configure: Regenerate.
 225         * po/opcodes.pot: Regenerate.
 226
 227 2018-06-24  Nick Clifton  <nickc@redhat.com>
 228
 229         2.31 branch created.
 230
 231 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
 232
 233         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
 234         * aarch64-asm-2.c: Regenerate.
 235         * aarch64-dis-2.c: Likewise.
 236
 237 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
 238
 239         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
 240         `-M ginv' option description.
 241
 242 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
 243
 244         PR gas/23305
 245         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
 246         la and lla.
 247
 248 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
 249
 250         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
 251         * configure.ac: Remove AC_PREREQ.
 252         * Makefile.in: Re-generate.
 253         * aclocal.m4: Re-generate.
 254         * configure: Re-generate.
 255
 256 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 257
 258         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
 259         mips64r6 descriptors.
 260         (parse_mips_ase_option): Handle -Mginv option.
 261         (print_mips_disassembler_options): Document -Mginv.
 262         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
 263         (GINV): New macro.
 264         (mips_opcodes): Define ginvi and ginvt.
 265
 266 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
 267             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 268
 269         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
 270         * mips-opc.c (CRC, CRC64): New macros.
 271         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
 272         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
 273         crc32cd for CRC64.
 274
 275 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
 276
 277         PR 20319
 278         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 279         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 280
 281 2018-06-06  Alan Modra  <amodra@gmail.com>
 282
 283         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
 284         setjmp.  Move init for some other vars later too.
 285
 286 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
 287
 288         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
 289         (dis_private): Add new fields for property section tracking.
 290         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
 291         (xtensa_instruction_fits): New functions.
 292         (fetch_data): Bump minimal fetch size to 4.
 293         (print_insn_xtensa): Make struct dis_private static.
 294         Load and prepare property table on section change.
 295         Don't disassemble literals. Don't disassemble instructions that
 296         cross property table boundaries.
 297
 298 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
 299
 300         * configure: Regenerated.
 301
 302 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 303
 304         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
 305         * i386-tbl.h: Re-generate.
 306
 307 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 308
 309         * i386-opc.tbl (sldt, str): Add NoRex64.
 310         * i386-tbl.h: Re-generate.
 311
 312 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 313
 314         * i386-opc.tbl (invpcid): Add Oword.
 315         * i386-tbl.h: Re-generate.
 316
 317 2018-06-01  Alan Modra  <amodra@gmail.com>
 318
 319         * sysdep.h (_bfd_error_handler): Don't declare.
 320         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
 321         * rl78-decode.opc: Likewise.
 322         * msp430-decode.c: Regenerate.
 323         * rl78-decode.c: Regenerate.
 324
 325 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 326
 327         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
 328         * i386-init.h : Regenerated.
 329
 330 2018-05-25  Alan Modra  <amodra@gmail.com>
 331
 332         * Makefile.in: Regenerate.
 333         * po/POTFILES.in: Regenerate.
 334
 335 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 336
 337         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 338         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 339         (insert_bab, extract_bab, insert_btab, extract_btab,
 340         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 341         (BAT, BBA VBA RBS XB6S): Delete macros.
 342         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 343         (BB, BD, RBX, XC6): Update for new macros.
 344         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 345         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 346         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 347         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 348
 349 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 350
 351         * Makefile.am: Add support for s12z architecture.
 352         * configure.ac: Likewise.
 353         * disassemble.c: Likewise.
 354         * disassemble.h: Likewise.
 355         * Makefile.in: Regenerate.
 356         * configure: Regenerate.
 357         * s12z-dis.c: New file.
 358         * s12z.h: New file.
 359
 360 2018-05-18  Alan Modra  <amodra@gmail.com>
 361
 362         * nfp-dis.c: Don't #include libbfd.h.
 363         (init_nfp3200_priv): Use bfd_get_section_contents.
 364         (nit_nfp6000_mecsr_sec): Likewise.
 365
 366 2018-05-17  Nick Clifton  <nickc@redhat.com>
 367
 368         * po/zh_CN.po: Updated simplified Chinese translation.
 369
 370 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 371
 372         PR binutils/23109
 373         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 374         * aarch64-dis-2.c: Regenerate.
 375
 376 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 377
 378         PR binutils/21446
 379         * aarch64-asm.c (opintl.h): Include.
 380         (aarch64_ins_sysreg): Enforce read/write constraints.
 381         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 382         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 383         (F_REG_READ, F_REG_WRITE): New.
 384         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 385         AARCH64_OPND_SYSREG.
 386         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 387         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 388         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 389         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 390         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 391         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 392         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 393         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 394         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 395         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 396         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 397         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 398         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 399         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 400         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 401         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 402         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 403
 404 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 405
 406         PR binutils/21446
 407         * aarch64-dis.c (no_notes: New.
 408         (parse_aarch64_dis_option): Support notes.
 409         (aarch64_decode_insn, print_operands): Likewise.
 410         (print_aarch64_disassembler_options): Document notes.
 411         * aarch64-opc.c (aarch64_print_operand): Support notes.
 412
 413 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 414
 415         PR binutils/21446
 416         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 417         and take error struct.
 418         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 419         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 420         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 421         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 422         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 423         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 424         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 425         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 426         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 427         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 428         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 429         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 430         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 431         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 432         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 433         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 434         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 435         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 436         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 437         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 438         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 439         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 440         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 441         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 442         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 443         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 444         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 445         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 446         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 447         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 448         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 449         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 450         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 451         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 452         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 453         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 454         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 455         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 456         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 457         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 458         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 459         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 460         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 461         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 462         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 463         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 464         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 465         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 466         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 467         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 468         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 469         (determine_disassembling_preference, aarch64_decode_insn,
 470         print_insn_aarch64_word, print_insn_data): Take errors struct.
 471         (print_insn_aarch64): Use errors.
 472         * aarch64-asm-2.c: Regenerate.
 473         * aarch64-dis-2.c: Regenerate.
 474         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 475         boolean in aarch64_insert_operan.
 476         (print_operand_extractor): Likewise.
 477         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 478
 479 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 480
 481         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 482
 483 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 484
 485         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 486
 487 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 488
 489         * cr16-opc.c (cr16_instruction): Comment typo fix.
 490         * hppa-dis.c (print_insn_hppa): Likewise.
 491
 492 2018-05-08  Jim Wilson  <jimw@sifive.com>
 493
 494         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 495         (match_c_slli64, match_srxi_as_c_srxi): New.
 496         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 497         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 498         <c.slli, c.srli, c.srai>: Use match_s_slli.
 499         <c.slli64, c.srli64, c.srai64>: New.
 500
 501 2018-05-08  Alan Modra  <amodra@gmail.com>
 502
 503         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 504         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 505         partition opcode space for index lookup.
 506
 507 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 508
 509         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 510         <insn_length>: ...with this.  Update usage.
 511         Remove duplicate call to *info->memory_error_func.
 512
 513 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 514             H.J. Lu  <hongjiu.lu@intel.com>
 515
 516         * i386-dis.c (Gva): New.
 517         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 518         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 519         (prefix_table): New instructions (see prefix above).
 520         (mod_table): New instructions (see prefix above).
 521         (OP_G): Handle va_mode.
 522         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 523         CPU_MOVDIR64B_FLAGS.
 524         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 525         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 526         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 527         * i386-opc.tbl: Add movidir{i,64b}.
 528         * i386-init.h: Regenerated.
 529         * i386-tbl.h: Likewise.
 530
 531 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 532
 533         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 534         AddrPrefixOpReg.
 535         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 536         (AddrPrefixOpReg): This.
 537         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 538         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 539
 540 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 541
 542         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 543         (vle_num_opcodes): Likewise.
 544         (spe2_num_opcodes): Likewise.
 545         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 546         initialization loop.
 547         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 548         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 549         only once.
 550
 551 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 552
 553         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 554
 555 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 556
 557         Makefile.am: Added nfp-dis.c.
 558         configure.ac: Added bfd_nfp_arch.
 559         disassemble.h: Added print_insn_nfp prototype.
 560         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 561         nfp-dis.c: New, for NFP support.
 562         po/POTFILES.in: Added nfp-dis.c to the list.
 563         Makefile.in: Regenerate.
 564         configure: Regenerate.
 565
 566 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 567
 568         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 569         templates into their base ones.
 570         * i386-tlb.h: Re-generate.
 571
 572 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 573
 574         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 575         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 576         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 577         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 578         * i386-init.h: Re-generate.
 579
 580 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 581
 582         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 583         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 584         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 585         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 586         comment.
 587         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 588         and CpuRegMask.
 589         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 590         CpuRegMask: Delete.
 591         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 592         cpuregzmm, and cpuregmask.
 593         * i386-init.h: Re-generate.
 594         * i386-tbl.h: Re-generate.
 595
 596 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 597
 598         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 599         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 600         * i386-init.h: Re-generate.
 601
 602 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 603
 604         * i386-gen.c (VexImmExt): Delete.
 605         * i386-opc.h (VexImmExt, veximmext): Delete.
 606         * i386-opc.tbl: Drop all VexImmExt uses.
 607         * i386-tlb.h: Re-generate.
 608
 609 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 610
 611         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 612         register-only forms.
 613         * i386-tlb.h: Re-generate.
 614
 615 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 616
 617         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 618
 619 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 620
 621         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 622         PREFIX_0F1C.
 623         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 624         (cpu_flags): Add CpuCLDEMOTE.
 625         * i386-init.h: Regenerate.
 626         * i386-opc.h (enum): Add CpuCLDEMOTE,
 627         (i386_cpu_flags): Add cpucldemote.
 628         * i386-opc.tbl: Add cldemote.
 629         * i386-tbl.h: Regenerate.
 630
 631 2018-04-16  Alan Modra  <amodra@gmail.com>
 632
 633         * Makefile.am: Remove sh5 and sh64 support.
 634         * configure.ac: Likewise.
 635         * disassemble.c: Likewise.
 636         * disassemble.h: Likewise.
 637         * sh-dis.c: Likewise.
 638         * sh64-dis.c: Delete.
 639         * sh64-opc.c: Delete.
 640         * sh64-opc.h: Delete.
 641         * Makefile.in: Regenerate.
 642         * configure: Regenerate.
 643         * po/POTFILES.in: Regenerate.
 644
 645 2018-04-16  Alan Modra  <amodra@gmail.com>
 646
 647         * Makefile.am: Remove w65 support.
 648         * configure.ac: Likewise.
 649         * disassemble.c: Likewise.
 650         * disassemble.h: Likewise.
 651         * w65-dis.c: Delete.
 652         * w65-opc.h: Delete.
 653         * Makefile.in: Regenerate.
 654         * configure: Regenerate.
 655         * po/POTFILES.in: Regenerate.
 656
 657 2018-04-16  Alan Modra  <amodra@gmail.com>
 658
 659         * configure.ac: Remove we32k support.
 660         * configure: Regenerate.
 661
 662 2018-04-16  Alan Modra  <amodra@gmail.com>
 663
 664         * Makefile.am: Remove m88k support.
 665         * configure.ac: Likewise.
 666         * disassemble.c: Likewise.
 667         * disassemble.h: Likewise.
 668         * m88k-dis.c: Delete.
 669         * Makefile.in: Regenerate.
 670         * configure: Regenerate.
 671         * po/POTFILES.in: Regenerate.
 672
 673 2018-04-16  Alan Modra  <amodra@gmail.com>
 674
 675         * Makefile.am: Remove i370 support.
 676         * configure.ac: Likewise.
 677         * disassemble.c: Likewise.
 678         * disassemble.h: Likewise.
 679         * i370-dis.c: Delete.
 680         * i370-opc.c: Delete.
 681         * Makefile.in: Regenerate.
 682         * configure: Regenerate.
 683         * po/POTFILES.in: Regenerate.
 684
 685 2018-04-16  Alan Modra  <amodra@gmail.com>
 686
 687         * Makefile.am: Remove h8500 support.
 688         * configure.ac: Likewise.
 689         * disassemble.c: Likewise.
 690         * disassemble.h: Likewise.
 691         * h8500-dis.c: Delete.
 692         * h8500-opc.h: Delete.
 693         * Makefile.in: Regenerate.
 694         * configure: Regenerate.
 695         * po/POTFILES.in: Regenerate.
 696
 697 2018-04-16  Alan Modra  <amodra@gmail.com>
 698
 699         * configure.ac: Remove tahoe support.
 700         * configure: Regenerate.
 701
 702 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 703
 704         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
 705         umwait.
 706         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
 707         64-bit mode.
 708         * i386-tbl.h: Regenerated.
 709
 710 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 711
 712         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
 713         PREFIX_MOD_1_0FAE_REG_6.
 714         (va_mode): New.
 715         (OP_E_register): Use va_mode.
 716         * i386-dis-evex.h (prefix_table):
 717         New instructions (see prefixes above).
 718         * i386-gen.c (cpu_flag_init): Add WAITPKG.
 719         (cpu_flags): Likewise.
 720         * i386-opc.h (enum): Likewise.
 721         (i386_cpu_flags): Likewise.
 722         * i386-opc.tbl: Add umonitor, umwait, tpause.
 723         * i386-init.h: Regenerate.
 724         * i386-tbl.h: Likewise.
 725
 726 2018-04-11  Alan Modra  <amodra@gmail.com>
 727
 728         * opcodes/i860-dis.c: Delete.
 729         * opcodes/i960-dis.c: Delete.
 730         * Makefile.am: Remove i860 and i960 support.
 731         * configure.ac: Likewise.
 732         * disassemble.c: Likewise.
 733         * disassemble.h: Likewise.
 734         * Makefile.in: Regenerate.
 735         * configure: Regenerate.
 736         * po/POTFILES.in: Regenerate.
 737
 738 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
 739
 740         PR binutils/23025
 741         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
 742         to 0.
 743         (print_insn): Clear vex instead of vex.evex.
 744
 745 2018-04-04  Nick Clifton  <nickc@redhat.com>
 746
 747         * po/es.po: Updated Spanish translation.
 748
 749 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 750
 751         * i386-gen.c (opcode_modifiers): Delete VecESize.
 752         * i386-opc.h (VecESize): Delete.
 753         (struct i386_opcode_modifier): Delete vecesize.
 754         * i386-opc.tbl: Drop VecESize.
 755         * i386-tlb.h: Re-generate.
 756
 757 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 758
 759         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
 760         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
 761         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
 762         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
 763         * i386-tlb.h: Re-generate.
 764
 765 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 766
 767         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
 768         Fold AVX512 forms
 769         * i386-tlb.h: Re-generate.
 770
 771 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 772
 773         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
 774         (vex_len_table): Drop Y for vcvt*2si.
 775         (putop): Replace plain 'Y' handling by abort().
 776
 777 2018-03-28  Nick Clifton  <nickc@redhat.com>
 778
 779         PR 22988
 780         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
 781         instructions with only a base address register.
 782         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
 783         handle AARHC64_OPND_SVE_ADDR_R.
 784         (aarch64_print_operand): Likewise.
 785         * aarch64-asm-2.c: Regenerate.
 786         * aarch64_dis-2.c: Regenerate.
 787         * aarch64-opc-2.c: Regenerate.
 788
 789 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 790
 791         * i386-opc.tbl: Drop VecESize from register only insn forms and
 792         memory forms not allowing broadcast.
 793         * i386-tlb.h: Re-generate.
 794
 795 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 796
 797         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
 798         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
 799         sha256*): Drop Disp<N>.
 800
 801 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 802
 803         * i386-dis.c (EbndS, bnd_swap_mode): New.
 804         (prefix_table): Use EbndS.
 805         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
 806         * i386-opc.tbl (bndmov): Move misplaced Load.
 807         * i386-tlb.h: Re-generate.
 808
 809 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 810
 811         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
 812         templates allowing memory operands and folded ones for register
 813         only flavors.
 814         * i386-tlb.h: Re-generate.
 815
 816 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 817
 818         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
 819         256-bit templates. Drop redundant leftover Disp<N>.
 820         * i386-tlb.h: Re-generate.
 821
 822 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
 823
 824         * riscv-opc.c (riscv_insn_types): New.
 825
 826 2018-03-13  Nick Clifton  <nickc@redhat.com>
 827
 828         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 829
 830 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 831
 832         * i386-opc.tbl: Add Optimize to clr.
 833         * i386-tbl.h: Regenerated.
 834
 835 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 836
 837         * i386-gen.c (opcode_modifiers): Remove OldGcc.
 838         * i386-opc.h (OldGcc): Removed.
 839         (i386_opcode_modifier): Remove oldgcc.
 840         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
 841         instructions for old (<= 2.8.1) versions of gcc.
 842         * i386-tbl.h: Regenerated.
 843
 844 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 845
 846         * i386-opc.h (EVEXDYN): New.
 847         * i386-opc.tbl: Fold various AVX512VL templates.
 848         * i386-tlb.h: Re-generate.
 849
 850 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 851
 852         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 853         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 854         vpexpandd, vpexpandq): Fold AFX512VF templates.
 855         * i386-tlb.h: Re-generate.
 856
 857 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 858
 859         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
 860         Fold 128- and 256-bit VEX-encoded templates.
 861         * i386-tlb.h: Re-generate.
 862
 863 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 864
 865         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 866         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 867         vpexpandd, vpexpandq): Fold AVX512F templates.
 868         * i386-tlb.h: Re-generate.
 869
 870 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 871
 872         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
 873         64-bit templates. Drop Disp<N>.
 874         * i386-tlb.h: Re-generate.
 875
 876 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 877
 878         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
 879         and 256-bit templates.
 880         * i386-tlb.h: Re-generate.
 881
 882 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 883
 884         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
 885         * i386-tlb.h: Re-generate.
 886
 887 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 888
 889         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
 890         Drop NoAVX.
 891         * i386-tlb.h: Re-generate.
 892
 893 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 894
 895         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
 896         * i386-tlb.h: Re-generate.
 897
 898 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 899
 900         * i386-gen.c (opcode_modifiers): Delete FloatD.
 901         * i386-opc.h (FloatD): Delete.
 902         (struct i386_opcode_modifier): Delete floatd.
 903         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
 904         FloatD by D.
 905         * i386-tlb.h: Re-generate.
 906
 907 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 908
 909         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
 910
 911 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 912
 913         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
 914         * i386-tlb.h: Re-generate.
 915
 916 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 917
 918         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
 919         forms.
 920         * i386-tlb.h: Re-generate.
 921
 922 2018-03-07  Alan Modra  <amodra@gmail.com>
 923
 924         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
 925         bfd_arch_rs6000.
 926         * disassemble.h (print_insn_rs6000): Delete.
 927         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
 928         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
 929         (print_insn_rs6000): Delete.
 930
 931 2018-03-03  Alan Modra  <amodra@gmail.com>
 932
 933         * sysdep.h (opcodes_error_handler): Define.
 934         (_bfd_error_handler): Declare.
 935         * Makefile.am: Remove stray #.
 936         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
 937         EDIT" comment.
 938         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
 939         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
 940         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
 941         opcodes_error_handler to print errors.  Standardize error messages.
 942         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
 943         and include opintl.h.
 944         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
 945         * i386-gen.c: Standardize error messages.
 946         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
 947         * Makefile.in: Regenerate.
 948         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
 949         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
 950         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
 951         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
 952         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
 953         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
 954         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
 955         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
 956         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
 957         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
 958         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
 959         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
 960         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
 961
 962 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 963
 964         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
 965         vpsub[bwdq] instructions.
 966         * i386-tbl.h: Regenerated.
 967
 968 2018-03-01  Alan Modra  <amodra@gmail.com>
 969
 970         * configure.ac (ALL_LINGUAS): Sort.
 971         * configure: Regenerate.
 972
 973 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 974
 975         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
 976         macro by assignements.
 977
 978 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
 979
 980         PR gas/22871
 981         * i386-gen.c (opcode_modifiers): Add Optimize.
 982         * i386-opc.h (Optimize): New enum.
 983         (i386_opcode_modifier): Add optimize.
 984         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
 985         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
 986         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
 987         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
 988         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
 989         vpxord and vpxorq.
 990         * i386-tbl.h: Regenerated.
 991
 992 2018-02-26  Alan Modra  <amodra@gmail.com>
 993
 994         * crx-dis.c (getregliststring): Allocate a large enough buffer
 995         to silence false positive gcc8 warning.
 996
 997 2018-02-22  Shea Levy <shea@shealevy.com>
 998
 999         * disassemble.c (ARCH_riscv): Define if ARCH_all.
1000
1001 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
1002
1003         * i386-opc.tbl: Add {rex},
1004         * i386-tbl.h: Regenerated.
1005
1006 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
1007
1008         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1009         (mips16_opcodes): Replace `M' with `m' for "restore".
1010
1011 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1012
1013         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1014
1015 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
1016
1017         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1018         variable to `function_index'.
1019
1020 2018-02-13  Nick Clifton  <nickc@redhat.com>
1021
1022         PR 22823
1023         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1024         about truncation of printing.
1025
1026 2018-02-12  Henry Wong <henry@stuffedcow.net>
1027
1028         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1029
1030 2018-02-05  Nick Clifton  <nickc@redhat.com>
1031
1032         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1033
1034 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1035
1036         * i386-dis.c (enum): Add pconfig.
1037         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1038         (cpu_flags): Add CpuPCONFIG.
1039         * i386-opc.h (enum): Add CpuPCONFIG.
1040         (i386_cpu_flags): Add cpupconfig.
1041         * i386-opc.tbl: Add PCONFIG instruction.
1042         * i386-init.h: Regenerate.
1043         * i386-tbl.h: Likewise.
1044
1045 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1046
1047         * i386-dis.c (enum): Add PREFIX_0F09.
1048         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1049         (cpu_flags): Add CpuWBNOINVD.
1050         * i386-opc.h (enum): Add CpuWBNOINVD.
1051         (i386_cpu_flags): Add cpuwbnoinvd.
1052         * i386-opc.tbl: Add WBNOINVD instruction.
1053         * i386-init.h: Regenerate.
1054         * i386-tbl.h: Likewise.
1055
1056 2018-01-17  Jim Wilson  <jimw@sifive.com>
1057
1058         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1059
1060 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1061
1062         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1063         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1064         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1065         (cpu_flags): Add CpuIBT, CpuSHSTK.
1066         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1067         (i386_cpu_flags): Add cpuibt, cpushstk.
1068         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1069         * i386-init.h: Regenerate.
1070         * i386-tbl.h: Likewise.
1071
1072 2018-01-16  Nick Clifton  <nickc@redhat.com>
1073
1074         * po/pt_BR.po: Updated Brazilian Portugese translation.
1075         * po/de.po: Updated German translation.
1076
1077 2018-01-15  Jim Wilson  <jimw@sifive.com>
1078
1079         * riscv-opc.c (match_c_nop): New.
1080         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1081
1082 2018-01-15  Nick Clifton  <nickc@redhat.com>
1083
1084         * po/uk.po: Updated Ukranian translation.
1085
1086 2018-01-13  Nick Clifton  <nickc@redhat.com>
1087
1088         * po/opcodes.pot: Regenerated.
1089
1090 2018-01-13  Nick Clifton  <nickc@redhat.com>
1091
1092         * configure: Regenerate.
1093
1094 2018-01-13  Nick Clifton  <nickc@redhat.com>
1095
1096         2.30 branch created.
1097
1098 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1099
1100         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1101         * i386-tbl.h: Regenerate.
1102
1103 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1104
1105         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1106         * i386-tbl.h: Re-generate.
1107
1108 2018-01-10  Jan Beulich  <jbeulich@suse.com>
1109
1110         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1111         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1112         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1113         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1114         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1115         Disp8MemShift of AVX512VL forms.
1116         * i386-tbl.h: Re-generate.
1117
1118 2018-01-09  Jim Wilson  <jimw@sifive.com>
1119
1120         * riscv-dis.c (maybe_print_address): If base_reg is zero,
1121         then the hi_addr value is zero.
1122
1123 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1124
1125         * arm-dis.c (arm_opcodes): Add csdb.
1126         (thumb32_opcodes): Add csdb.
1127
1128 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
1129
1130         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1131         * aarch64-asm-2.c: Regenerate.
1132         * aarch64-dis-2.c: Regenerate.
1133         * aarch64-opc-2.c: Regenerate.
1134
1135 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
1136
1137         PR gas/22681
1138         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1139         Remove AVX512 vmovd with 64-bit operands.
1140         * i386-tbl.h: Regenerated.
1141
1142 2018-01-05  Jim Wilson  <jimw@sifive.com>
1143
1144         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1145         jalr.
1146
1147 2018-01-03  Alan Modra  <amodra@gmail.com>
1148
1149         Update year range in copyright notice of all files.
1150
1151 2018-01-02  Jan Beulich  <jbeulich@suse.com>
1152
1153         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1154         and OPERAND_TYPE_REGZMM entries.
1155
1156 For older changes see ChangeLog-2017
1157 \f
1158 Copyright (C) 2018 Free Software Foundation, Inc.
1159
1160 Copying and distribution of this file, with or without modification,
1161 are permitted in any medium without royalty provided the copyright
1162 notice and this notice are preserved.
1163
1164 Local Variables:
1165 mode: change-log
1166 left-margin: 8
1167 fill-column: 74
1168 version-control: never
1169 End: