opcodes/ChangeLog

   1 2020-07-04  Nick Clifton  <nickc@redhat.com>
   2
   3         Binutils 2.35 branch created.
   4
   5 2020-07-02  H.J. Lu  <hongjiu.lu@intel.com>
   6
   7         * i386-gen.c (opcode_modifiers): Add VexSwapSources.
   8         * i386-opc.h (VexSwapSources): New.
   9         (i386_opcode_modifier): Add vexswapsources.
  10         * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
  11         with two source operands swapped.
  12         * i386-tbl.h: Regenerated.
  13
  14 2020-06-30  Nelson Chu  <nelson.chu@sifive.com>
  15
  16         * riscv-dis.c (print_insn_args, case 'E'): Updated.  Let the
  17         unprivileged CSR can also be initialized.
  18
  19 2020-06-29  Alan Modra  <amodra@gmail.com>
  20
  21         * arm-dis.c: Use C style comments.
  22         * cr16-opc.c: Likewise.
  23         * ft32-dis.c: Likewise.
  24         * moxie-opc.c: Likewise.
  25         * tic54x-dis.c: Likewise.
  26         * s12z-opc.c: Remove useless comment.
  27         * xgate-dis.c: Likewise.
  28
  29 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
  30
  31         * i386-opc.tbl: Add a blank line.
  32
  33 2020-06-26  H.J. Lu  <hongjiu.lu@intel.com>
  34
  35         * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
  36         (VecSIB128): Renamed to ...
  37         (VECSIB128): This.
  38         (VecSIB256): Renamed to ...
  39         (VECSIB256): This.
  40         (VecSIB512): Renamed to ...
  41         (VECSIB512): This.
  42         (VecSIB): Renamed to ...
  43         (SIB): This.
  44         (i386_opcode_modifier): Replace vecsib with sib.
  45         * i386-opc.tbl (VecSIB128): New.
  46         (VecSIB256): Likewise.
  47         (VecSIB512): Likewise.
  48         Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
  49         and VecSIB512, respectively.
  50
  51 2020-06-26  Jan Beulich  <jbeulich@suse.com>
  52
  53         * i386-dis.c: Adjust description of I macro.
  54         (x86_64_table): Drop use of I.
  55         (float_mem): Replace use of I.
  56         (putop): Remove handling of I. Adjust setting/clearing of "alt".
  57
  58 2020-06-26  Jan Beulich  <jbeulich@suse.com>
  59
  60         * i386-dis.c: (print_insn): Avoid straight assignment to
  61         priv.orig_sizeflag when processing -M sub-options.
  62
  63 2020-06-25  Jan Beulich  <jbeulich@suse.com>
  64
  65         * i386-dis.c: Adjust description of J macro.
  66         (dis386, x86_64_table, mod_table): Replace J.
  67         (putop): Remove handling of J.
  68
  69 2020-06-25  Jan Beulich  <jbeulich@suse.com>
  70
  71         * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
  72
  73 2020-06-25  Jan Beulich  <jbeulich@suse.com>
  74
  75         * i386-dis.c: Adjust description of "LQ" macro.
  76         (dis386_twobyte): Use LQ for sysret.
  77         (putop): Adjust handling of LQ.
  78
  79 2020-06-22  Nelson Chu  <nelson.chu@sifive.com>
  80
  81         * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
  82         * riscv-dis.c: Include elfxx-riscv.h.
  83
  84 2020-06-18  H.J. Lu  <hongjiu.lu@intel.com>
  85
  86         * i386-dis.c (prefix_table): Revert the last vmgexit change.
  87
  88 2020-06-17  Lili Cui  <lili.cui@intel.com>
  89
  90         * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
  91
  92 2020-06-14  H.J. Lu  <hongjiu.lu@intel.com>
  93
  94         PR gas/26115
  95         * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
  96         * i386-opc.tbl: Likewise.
  97         * i386-tbl.h: Regenerated.
  98
  99 2020-06-12  Nelson Chu  <nelson.chu@sifive.com>
 100
 101         * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
 102
 103 2020-06-11  Alex Coplan  <alex.coplan@arm.com>
 104
 105         * aarch64-opc.c (SYSREG): New macro for describing system registers.
 106         (SR_CORE): Likewise.
 107         (SR_FEAT): Likewise.
 108         (SR_RNG): Likewise.
 109         (SR_V8_1): Likewise.
 110         (SR_V8_2): Likewise.
 111         (SR_V8_3): Likewise.
 112         (SR_V8_4): Likewise.
 113         (SR_PAN): Likewise.
 114         (SR_RAS): Likewise.
 115         (SR_SSBS): Likewise.
 116         (SR_SVE): Likewise.
 117         (SR_ID_PFR2): Likewise.
 118         (SR_PROFILE): Likewise.
 119         (SR_MEMTAG): Likewise.
 120         (SR_SCXTNUM): Likewise.
 121         (aarch64_sys_regs): Refactor to store feature information in the table.
 122         (aarch64_sys_reg_supported_p): Collapse logic for system registers
 123         that now describe their own features.
 124         (aarch64_pstatefield_supported_p): Likewise.
 125
 126 2020-06-09  H.J. Lu  <hongjiu.lu@intel.com>
 127
 128         * i386-dis.c (prefix_table): Fix a typo in comments.
 129
 130 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 131
 132         * i386-dis.c (rex_ignored): Delete.
 133         (ckprefix): Drop rex_ignored initialization.
 134         (get_valid_dis386): Drop setting of rex_ignored.
 135         (print_insn): Drop checking of rex_ignored. Don't record data
 136         size prefix as used with VEX-and-alike encodings.
 137
 138 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 139
 140         * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
 141         MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
 142         (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
 143         (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
 144         (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
 145         VEX_0F12, and VEX_0F16.
 146         (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
 147         VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
 148         (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
 149         from movlps and movhlps. New MOD_0F12_PREFIX_2,
 150         MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
 151         MOD_VEX_0F16_PREFIX_2 entries.
 152
 153 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 154
 155         * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
 156         MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
 157         (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
 158         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
 159         PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
 160         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
 161         EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
 162         EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
 163         EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
 164         EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
 165         EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
 166         EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
 167         EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
 168         EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
 169         EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
 170         EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
 171         EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
 172         EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
 173         EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
 174         EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
 175         EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
 176         EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
 177         EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
 178         EVEX_W_0FC6_P_2): Delete.
 179         (print_insn): Add EVEX.W vs embedded prefix consistency check
 180         to prefix validation.
 181         * i386-dis-evex.h (evex_table): Don't further descend for
 182         vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
 183         and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
 184         and 0F2B.
 185         * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
 186         * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
 187         vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
 188         vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
 189         2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
 190         Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
 191         PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
 192         PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
 193         PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
 194         * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
 195         EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
 196         EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
 197         EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
 198         EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
 199         EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
 200         EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
 201         EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
 202         EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
 203         EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
 204         EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
 205         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
 206         EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
 207         EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
 208         EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
 209         EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
 210         EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
 211         EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
 212
 213 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 214
 215         * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
 216         vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
 217         (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
 218         vmovmskpX.
 219         (print_insn): Drop pointless check against bad_opcode. Split
 220         prefix validation into legacy and VEX-and-alike parts.
 221         (putop): Re-work 'X' macro handling.
 222
 223 2020-06-09  Jan Beulich  <jbeulich@suse.com>
 224
 225         * i386-dis.c (MOD_0F51): Rename to ...
 226         (MOD_0F50): ... this.
 227
 228 2020-06-08  Alex Coplan  <alex.coplan@arm.com>
 229
 230         * arm-dis.c (arm_opcodes): Add dfb.
 231         (thumb32_opcodes): Add dfb.
 232
 233 2020-06-08  Jan Beulich  <jbeulich@suse.com>
 234
 235         * i386-opc.h (reg_entry): Const-qualify reg_name field.
 236
 237 2020-06-06  Alan Modra  <amodra@gmail.com>
 238
 239         * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
 240
 241 2020-06-05  Alan Modra  <amodra@gmail.com>
 242
 243         * cgen-dis.c (hash_insn_array): Increase size of buf.  Assert
 244         size is large enough.
 245
 246 2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>
 247
 248         * disassemble.c (disassemble_init_for_target): Set endian_code for
 249         bpf targets.
 250         * bpf-desc.c: Regenerate.
 251         * bpf-opc.c: Likewise.
 252         * bpf-dis.c: Likewise.
 253
 254 2020-06-03  Jose E. Marchesi  <jose.marchesi@oracle.com>
 255
 256         * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
 257         (cgen_put_insn_value): Likewise.
 258         (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
 259         * cgen-dis.in (print_insn): Likewise.
 260         * cgen-ibld.in (insert_1): Likewise.
 261         (insert_1): Likewise.
 262         (insert_insn_normal): Likewise.
 263         (extract_1): Likewise.
 264         * bpf-dis.c: Regenerate.
 265         * bpf-ibld.c: Likewise.
 266         * bpf-ibld.c: Likewise.
 267         * cgen-dis.in: Likewise.
 268         * cgen-ibld.in: Likewise.
 269         * cgen-opc.c: Likewise.
 270         * epiphany-dis.c: Likewise.
 271         * epiphany-ibld.c: Likewise.
 272         * fr30-dis.c: Likewise.
 273         * fr30-ibld.c: Likewise.
 274         * frv-dis.c: Likewise.
 275         * frv-ibld.c: Likewise.
 276         * ip2k-dis.c: Likewise.
 277         * ip2k-ibld.c: Likewise.
 278         * iq2000-dis.c: Likewise.
 279         * iq2000-ibld.c: Likewise.
 280         * lm32-dis.c: Likewise.
 281         * lm32-ibld.c: Likewise.
 282         * m32c-dis.c: Likewise.
 283         * m32c-ibld.c: Likewise.
 284         * m32r-dis.c: Likewise.
 285         * m32r-ibld.c: Likewise.
 286         * mep-dis.c: Likewise.
 287         * mep-ibld.c: Likewise.
 288         * mt-dis.c: Likewise.
 289         * mt-ibld.c: Likewise.
 290         * or1k-dis.c: Likewise.
 291         * or1k-ibld.c: Likewise.
 292         * xc16x-dis.c: Likewise.
 293         * xc16x-ibld.c: Likewise.
 294         * xstormy16-dis.c: Likewise.
 295         * xstormy16-ibld.c: Likewise.
 296
 297 2020-06-04  Jose E. Marchesi  <jemarch@gnu.org>
 298
 299         * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
 300         (print_insn_): Handle instruction endian.
 301         * bpf-dis.c: Regenerate.
 302         * bpf-desc.c: Regenerate.
 303         * epiphany-dis.c: Likewise.
 304         * epiphany-desc.c: Likewise.
 305         * fr30-dis.c: Likewise.
 306         * fr30-desc.c: Likewise.
 307         * frv-dis.c: Likewise.
 308         * frv-desc.c: Likewise.
 309         * ip2k-dis.c: Likewise.
 310         * ip2k-desc.c: Likewise.
 311         * iq2000-dis.c: Likewise.
 312         * iq2000-desc.c: Likewise.
 313         * lm32-dis.c: Likewise.
 314         * lm32-desc.c: Likewise.
 315         * m32c-dis.c: Likewise.
 316         * m32c-desc.c: Likewise.
 317         * m32r-dis.c: Likewise.
 318         * m32r-desc.c: Likewise.
 319         * mep-dis.c: Likewise.
 320         * mep-desc.c: Likewise.
 321         * mt-dis.c: Likewise.
 322         * mt-desc.c: Likewise.
 323         * or1k-dis.c: Likewise.
 324         * or1k-desc.c: Likewise.
 325         * xc16x-dis.c: Likewise.
 326         * xc16x-desc.c: Likewise.
 327         * xstormy16-dis.c: Likewise.
 328         * xstormy16-desc.c: Likewise.
 329
 330 2020-06-03  Nick Clifton  <nickc@redhat.com>
 331
 332         * po/sr.po: Updated Serbian translation.
 333
 334 2020-06-03  Nelson Chu  <nelson.chu@sifive.com>
 335
 336         * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
 337         (riscv_get_priv_spec_class): Likewise.
 338
 339 2020-06-01  Alan Modra  <amodra@gmail.com>
 340
 341         * bpf-desc.c: Regenerate.
 342
 343 2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
 344             David Faust <david.faust@oracle.com>
 345
 346         * bpf-desc.c: Regenerate.
 347         * bpf-opc.h: Likewise.
 348         * bpf-opc.c: Likewise.
 349         * bpf-dis.c: Likewise.
 350
 351 2020-05-28  Alan Modra  <amodra@gmail.com>
 352
 353         * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
 354         values.
 355
 356 2020-05-28  Alan Modra  <amodra@gmail.com>
 357
 358         * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
 359         immediates.
 360         (print_insn_ns32k): Revert last change.
 361
 362 2020-05-28  Nick Clifton  <nickc@redhat.com>
 363
 364         * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
 365         static.
 366
 367 2020-05-26  Sandra Loosemore  <sandra@codesourcery.com>
 368
 369         Fix extraction of signed constants in nios2 disassembler (again).
 370
 371         * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
 372         extractions of signed fields.
 373
 374 2020-05-26  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
 375
 376         * s390-opc.txt: Relocate vector load/store instructions with
 377         additional alignment parameter and change architecture level
 378         constraint from z14 to z13.
 379
 380 2020-05-21  Alan Modra  <amodra@gmail.com>
 381
 382         * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
 383         * sparc-dis.c: Likewise.
 384         * tic4x-dis.c: Likewise.
 385         * xtensa-dis.c: Likewise.
 386         * bpf-desc.c: Regenerate.
 387         * epiphany-desc.c: Regenerate.
 388         * fr30-desc.c: Regenerate.
 389         * frv-desc.c: Regenerate.
 390         * ip2k-desc.c: Regenerate.
 391         * iq2000-desc.c: Regenerate.
 392         * lm32-desc.c: Regenerate.
 393         * m32c-desc.c: Regenerate.
 394         * m32r-desc.c: Regenerate.
 395         * mep-asm.c: Regenerate.
 396         * mep-desc.c: Regenerate.
 397         * mt-desc.c: Regenerate.
 398         * or1k-desc.c: Regenerate.
 399         * xc16x-desc.c: Regenerate.
 400         * xstormy16-desc.c: Regenerate.
 401
 402 2020-05-20  Nelson Chu  <nelson.chu@sifive.com>
 403
 404         * riscv-opc.c (riscv_ext_version_table): The table used to store
 405         all information about the supported spec and the corresponding ISA
 406         versions.  Currently, only Zicsr is supported to verify the
 407         correctness of Z sub extension settings.  Others will be supported
 408         in the future patches.
 409         (struct isa_spec_t, isa_specs): List for all supported ISA spec
 410         classes and the corresponding strings.
 411         (riscv_get_isa_spec_class): New function.  Get the corresponding ISA
 412         spec class by giving a ISA spec string.
 413         * riscv-opc.c (struct priv_spec_t): New structure.
 414         (struct priv_spec_t priv_specs): List for all supported privilege spec
 415         classes and the corresponding strings.
 416         (riscv_get_priv_spec_class): New function.  Get the corresponding
 417         privilege spec class by giving a spec string.
 418         (riscv_get_priv_spec_name): New function.  Get the corresponding
 419         privilege spec string by giving a CSR version class.
 420         * riscv-dis.c: Updated since DECLARE_CSR is changed.
 421         * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
 422         according to the chosen version.  Build a hash table riscv_csr_hash to
 423         store the valid CSR for the chosen pirv verison.  Dump the direct
 424         CSR address rather than it's name if it is invalid.
 425         (parse_riscv_dis_option_without_args): New function.  Parse the options
 426         without arguments.
 427         (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
 428         parse the options without arguments first, and then handle the options
 429         with arguments.  Add the new option -Mpriv-spec, which has argument.
 430         * riscv-dis.c (print_riscv_disassembler_options): Add description
 431         about the new OBJDUMP option.
 432
 433 2020-05-19  Peter Bergner  <bergner@linux.ibm.com>
 434
 435         * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
 436         WC values on POWER10 sync, dcbf  and wait instructions.
 437         (insert_pl, extract_pl): New functions.
 438         (L2OPT, LS, WC): Use insert_ls and extract_ls.
 439         (LS3): New , 3-bit L for sync.
 440         (LS3, L3OPT): New, 3-bit L for sync and dcbf.
 441         (SC2, PL): New, 2-bit SC and PL for sync and wait.
 442         (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
 443         (XOPL3, XWCPL, XSYNCLS): New opcode macros.
 444         (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
 445         plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
 446         <wait>: Enable PL operand on POWER10.
 447         <dcbf>: Enable L3OPT operand on POWER10.
 448         <sync>: Enable SC2 operand on POWER10.
 449
 450 2020-05-19  Stafford Horne  <shorne@gmail.com>
 451
 452         PR 25184
 453         * or1k-asm.c: Regenerate.
 454         * or1k-desc.c: Regenerate.
 455         * or1k-desc.h: Regenerate.
 456         * or1k-dis.c: Regenerate.
 457         * or1k-ibld.c: Regenerate.
 458         * or1k-opc.c: Regenerate.
 459         * or1k-opc.h: Regenerate.
 460         * or1k-opinst.c: Regenerate.
 461
 462 2020-05-11  Alan Modra  <amodra@gmail.com>
 463
 464         * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
 465         xsmaxcqp, xsmincqp.
 466
 467 2020-05-11  Alan Modra  <amodra@gmail.com>
 468
 469         * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
 470         stxvrbx, stxvrhx, stxvrwx, stxvrdx.
 471
 472 2020-05-11  Alan Modra  <amodra@gmail.com>
 473
 474         * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
 475
 476 2020-05-11  Alan Modra  <amodra@gmail.com>
 477
 478         * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
 479         vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
 480
 481 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 482
 483         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
 484         mnemonics.
 485
 486 2020-05-11  Alan Modra  <amodra@gmail.com>
 487
 488         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
 489         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
 490         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
 491         (prefix_opcodes): Add xxeval.
 492
 493 2020-05-11  Alan Modra  <amodra@gmail.com>
 494
 495         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
 496         xxgenpcvwm, xxgenpcvdm.
 497
 498 2020-05-11  Alan Modra  <amodra@gmail.com>
 499
 500         * ppc-opc.c (MP, VXVAM_MASK): Define.
 501         (VXVAPS_MASK): Use VXVA_MASK.
 502         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
 503         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
 504         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
 505         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
 506
 507 2020-05-11  Alan Modra  <amodra@gmail.com>
 508             Peter Bergner  <bergner@linux.ibm.com>
 509
 510         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
 511         New functions.
 512         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
 513         YMSK2, XA6a, XA6ap, XB6a entries.
 514         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
 515         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
 516         (PPCVSX4): Define.
 517         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
 518         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
 519         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
 520         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
 521         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
 522         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
 523         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
 524         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
 525         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
 526         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
 527         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
 528         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
 529         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
 530         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
 531
 532 2020-05-11  Alan Modra  <amodra@gmail.com>
 533
 534         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
 535         (insert_xts, extract_xts): New functions.
 536         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
 537         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
 538         (VXRC_MASK, VXSH_MASK): Define.
 539         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
 540         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
 541         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
 542         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
 543         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
 544         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
 545         xxblendvh, xxblendvw, xxblendvd, xxpermx.
 546
 547 2020-05-11  Alan Modra  <amodra@gmail.com>
 548
 549         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
 550         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
 551         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
 552         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
 553         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
 554
 555 2020-05-11  Alan Modra  <amodra@gmail.com>
 556
 557         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
 558         (XTP, DQXP, DQXP_MASK): Define.
 559         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
 560         (prefix_opcodes): Add plxvp and pstxvp.
 561
 562 2020-05-11  Alan Modra  <amodra@gmail.com>
 563
 564         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
 565         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
 566         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
 567
 568 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 569
 570         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
 571
 572 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 573
 574         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
 575         (L1OPT): Define.
 576         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
 577
 578 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 579
 580         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
 581
 582 2020-05-11  Alan Modra  <amodra@gmail.com>
 583
 584         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
 585
 586 2020-05-11  Alan Modra  <amodra@gmail.com>
 587
 588         * ppc-dis.c (ppc_opts): Add "power10" entry.
 589         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
 590         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
 591
 592 2020-05-11  Nick Clifton  <nickc@redhat.com>
 593
 594         * po/fr.po: Updated French translation.
 595
 596 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
 597
 598         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
 599         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
 600         (operand_general_constraint_met_p): validate
 601         AARCH64_OPND_UNDEFINED.
 602         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
 603         for FLD_imm16_2.
 604         * aarch64-asm-2.c: Regenerated.
 605         * aarch64-dis-2.c: Regenerated.
 606         * aarch64-opc-2.c: Regenerated.
 607
 608 2020-04-29  Nick Clifton  <nickc@redhat.com>
 609
 610         PR 22699
 611         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
 612         and SETRC insns.
 613
 614 2020-04-29  Nick Clifton  <nickc@redhat.com>
 615
 616         * po/sv.po: Updated Swedish translation.
 617
 618 2020-04-29  Nick Clifton  <nickc@redhat.com>
 619
 620         PR 22699
 621         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
 622         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
 623         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
 624         IMM0_8U case.
 625
 626 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
 627
 628         PR 25848
 629         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
 630         cmpi only on m68020up and cpu32.
 631
 632 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 633
 634         * aarch64-asm.c (aarch64_ins_none): New.
 635         * aarch64-asm.h (ins_none): New declaration.
 636         * aarch64-dis.c (aarch64_ext_none): New.
 637         * aarch64-dis.h (ext_none): New declaration.
 638         * aarch64-opc.c (aarch64_print_operand): Update case for
 639         AARCH64_OPND_BARRIER_PSB.
 640         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
 641         (AARCH64_OPERANDS): Update inserter/extracter for
 642         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
 643         * aarch64-asm-2.c: Regenerated.
 644         * aarch64-dis-2.c: Regenerated.
 645         * aarch64-opc-2.c: Regenerated.
 646
 647 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 648
 649         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
 650         (aarch64_feature_ras, RAS): Likewise.
 651         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
 652         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
 653         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
 654         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
 655         * aarch64-asm-2.c: Regenerated.
 656         * aarch64-dis-2.c: Regenerated.
 657         * aarch64-opc-2.c: Regenerated.
 658
 659 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
 660
 661         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
 662         (print_insn_neon): Support disassembly of conditional
 663         instructions.
 664
 665 2020-02-16  David Faust  <david.faust@oracle.com>
 666
 667         * bpf-desc.c: Regenerate.
 668         * bpf-desc.h: Likewise.
 669         * bpf-opc.c: Regenerate.
 670         * bpf-opc.h: Likewise.
 671
 672 2020-04-07  Lili Cui  <lili.cui@intel.com>
 673
 674         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
 675         (prefix_table): New instructions (see prefixes above).
 676         (rm_table): Likewise
 677         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
 678         CPU_ANY_TSXLDTRK_FLAGS.
 679         (cpu_flags): Add CpuTSXLDTRK.
 680         * i386-opc.h (enum): Add CpuTSXLDTRK.
 681         (i386_cpu_flags): Add cputsxldtrk.
 682         * i386-opc.tbl: Add XSUSPLDTRK insns.
 683         * i386-init.h: Regenerate.
 684         * i386-tbl.h: Likewise.
 685
 686 2020-04-02  Lili Cui  <lili.cui@intel.com>
 687
 688         * i386-dis.c (prefix_table): New instructions serialize.
 689         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
 690         CPU_ANY_SERIALIZE_FLAGS.
 691         (cpu_flags): Add CpuSERIALIZE.
 692         * i386-opc.h (enum): Add CpuSERIALIZE.
 693         (i386_cpu_flags): Add cpuserialize.
 694         * i386-opc.tbl: Add SERIALIZE insns.
 695         * i386-init.h: Regenerate.
 696         * i386-tbl.h: Likewise.
 697
 698 2020-03-26  Alan Modra  <amodra@gmail.com>
 699
 700         * disassemble.h (opcodes_assert): Declare.
 701         (OPCODES_ASSERT): Define.
 702         * disassemble.c: Don't include assert.h.  Include opintl.h.
 703         (opcodes_assert): New function.
 704         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 705         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 706         calculate maxlen.  Omit insn decoding when insn length exceeds
 707         maxlen.  Exit from nibble loop when looking for E, before
 708         accessing next data byte.  Move processing of E outside loop.
 709         Replace tests of maxlen in loop with assertions.
 710
 711 2020-03-26  Alan Modra  <amodra@gmail.com>
 712
 713         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 714
 715 2020-03-25  Alan Modra  <amodra@gmail.com>
 716
 717         * z80-dis.c (suffix): Init mybuf.
 718
 719 2020-03-22  Alan Modra  <amodra@gmail.com>
 720
 721         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 722         successflly read from section.
 723
 724 2020-03-22  Alan Modra  <amodra@gmail.com>
 725
 726         * arc-dis.c (find_format): Use ISO C string concatenation rather
 727         than line continuation within a string.  Don't access needs_limm
 728         before testing opcode != NULL.
 729
 730 2020-03-22  Alan Modra  <amodra@gmail.com>
 731
 732         * ns32k-dis.c (print_insn_arg): Update comment.
 733         (print_insn_ns32k): Reduce size of index_offset array, and
 734         initialize, passing -1 to print_insn_arg for args that are not
 735         an index.  Don't exit arg loop early.  Abort on bad arg number.
 736
 737 2020-03-22  Alan Modra  <amodra@gmail.com>
 738
 739         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 740         * s12z-opc.c: Formatting.
 741         (operands_f): Return an int.
 742         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 743         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 744         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 745         (exg_sex_discrim): Likewise.
 746         (create_immediate_operand, create_bitfield_operand),
 747         (create_register_operand_with_size, create_register_all_operand),
 748         (create_register_all16_operand, create_simple_memory_operand),
 749         (create_memory_operand, create_memory_auto_operand): Don't
 750         segfault on malloc failure.
 751         (z_ext24_decode): Return an int status, negative on fail, zero
 752         on success.
 753         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 754         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 755         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 756         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 757         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 758         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 759         (loop_primitive_decode, shift_decode, psh_pul_decode),
 760         (bit_field_decode): Similarly.
 761         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 762         to return value, update callers.
 763         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 764         Don't segfault on NULL operand.
 765         (decode_operation): Return OP_INVALID on first fail.
 766         (decode_s12z): Check all reads, returning -1 on fail.
 767
 768 2020-03-20  Alan Modra  <amodra@gmail.com>
 769
 770         * metag-dis.c (print_insn_metag): Don't ignore status from
 771         read_memory_func.
 772
 773 2020-03-20  Alan Modra  <amodra@gmail.com>
 774
 775         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 776         Initialize parts of buffer not written when handling a possible
 777         2-byte insn at end of section.  Don't attempt decoding of such
 778         an insn by the 4-byte machinery.
 779
 780 2020-03-20  Alan Modra  <amodra@gmail.com>
 781
 782         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 783         partially filled buffer.  Prevent lookup of 4-byte insns when
 784         only VLE 2-byte insns are possible due to section size.  Print
 785         ".word" rather than ".long" for 2-byte leftovers.
 786
 787 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 788
 789         PR 25641
 790         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 791
 792 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 793
 794         * i386-dis.c (X86_64_0D): Rename to ...
 795         (X86_64_0E): ... this.
 796
 797 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 798
 799         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 800         * Makefile.in: Regenerated.
 801
 802 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 803
 804         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 805         3-operand pseudos.
 806         * i386-tbl.h: Re-generate.
 807
 808 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 809
 810         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 811         vprot*, vpsha*, and vpshl*.
 812         * i386-tbl.h: Re-generate.
 813
 814 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 815
 816         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 817         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 818         * i386-tbl.h: Re-generate.
 819
 820 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 821
 822         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 823         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 824         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 825         * i386-tbl.h: Re-generate.
 826
 827 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 828
 829         * i386-gen.c (struct template_arg, struct template_instance,
 830         struct template_param, struct template, templates,
 831         parse_template, expand_templates): New.
 832         (process_i386_opcodes): Various local variables moved to
 833         expand_templates. Call parse_template and expand_templates.
 834         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 835         * i386-tbl.h: Re-generate.
 836
 837 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 838
 839         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 840         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 841         register and memory source templates. Replace VexW= by VexW*
 842         where applicable.
 843         * i386-tbl.h: Re-generate.
 844
 845 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 846
 847         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 848         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 849         * i386-tbl.h: Re-generate.
 850
 851 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 852
 853         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 854         * i386-tbl.h: Re-generate.
 855
 856 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 857
 858         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 859         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 860         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 861         VexW0 on SSE2AVX variants.
 862         (vmovq): Drop NoRex64 from XMM/XMM variants.
 863         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 864         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 865         applicable use VexW0.
 866         * i386-tbl.h: Re-generate.
 867
 868 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 869
 870         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 871         * i386-opc.h (Rex64): Delete.
 872         (struct i386_opcode_modifier): Remove rex64 field.
 873         * i386-opc.tbl (crc32): Drop Rex64.
 874         Replace Rex64 with Size64 everywhere else.
 875         * i386-tbl.h: Re-generate.
 876
 877 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 878
 879         * i386-dis.c (OP_E_memory): Exclude recording of used address
 880         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 881         addressed memory operands for MPX insns.
 882
 883 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 884
 885         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 886         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 887         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 888         (ptwrite): Split into non-64-bit and 64-bit forms.
 889         * i386-tbl.h: Re-generate.
 890
 891 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 892
 893         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 894         template.
 895         * i386-tbl.h: Re-generate.
 896
 897 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 898
 899         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 900         (prefix_table): Move vmmcall here. Add vmgexit.
 901         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 902         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 903         (cpu_flags): Add CpuSEV_ES entry.
 904         * i386-opc.h (CpuSEV_ES): New.
 905         (union i386_cpu_flags): Add cpusev_es field.
 906         * i386-opc.tbl (vmgexit): New.
 907         * i386-init.h, i386-tbl.h: Re-generate.
 908
 909 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 910
 911         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 912         with MnemonicSize.
 913         * i386-opc.h (IGNORESIZE): New.
 914         (DEFAULTSIZE): Likewise.
 915         (IgnoreSize): Removed.
 916         (DefaultSize): Likewise.
 917         (MnemonicSize): New.
 918         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 919         mnemonicsize.
 920         * i386-opc.tbl (IgnoreSize): New.
 921         (DefaultSize): Likewise.
 922         * i386-tbl.h: Regenerated.
 923
 924 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 925
 926         PR 25627
 927         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 928         instructions.
 929
 930 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 931
 932         PR gas/25622
 933         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 934         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 935         * i386-tbl.h: Regenerated.
 936
 937 2020-02-26  Alan Modra  <amodra@gmail.com>
 938
 939         * aarch64-asm.c: Indent labels correctly.
 940         * aarch64-dis.c: Likewise.
 941         * aarch64-gen.c: Likewise.
 942         * aarch64-opc.c: Likewise.
 943         * alpha-dis.c: Likewise.
 944         * i386-dis.c: Likewise.
 945         * nds32-asm.c: Likewise.
 946         * nfp-dis.c: Likewise.
 947         * visium-dis.c: Likewise.
 948
 949 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 950
 951         * arc-regs.h (int_vector_base): Make it available for all ARC
 952         CPUs.
 953
 954 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 955
 956         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 957         changed.
 958
 959 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 960
 961         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 962         c.mv/c.li if rs1 is zero.
 963
 964 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 965
 966         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 967         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 968         CPU_POPCNT_FLAGS.
 969         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 970         * i386-opc.h (CpuABM): Removed.
 971         (CpuPOPCNT): New.
 972         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 973         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 974         popcnt.  Remove CpuABM from lzcnt.
 975         * i386-init.h: Regenerated.
 976         * i386-tbl.h: Likewise.
 977
 978 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 979
 980         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 981         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 982         VexW1 instead of open-coding them.
 983         * i386-tbl.h: Re-generate.
 984
 985 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 986
 987         * i386-opc.tbl (AddrPrefixOpReg): Define.
 988         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 989         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 990         templates. Drop NoRex64.
 991         * i386-tbl.h: Re-generate.
 992
 993 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 994
 995         PR gas/6518
 996         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 997         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 998         into Intel syntax instance (with Unpsecified) and AT&T one
 999         (without).
1000         (vcvtneps2bf16): Likewise, along with folding the two so far
1001         separate ones.
1002         * i386-tbl.h: Re-generate.
1003
1004 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
1005
1006         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
1007         CPU_ANY_SSE4A_FLAGS.
1008
1009 2020-02-17  Alan Modra  <amodra@gmail.com>
1010
1011         * i386-gen.c (cpu_flag_init): Correct last change.
1012
1013 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
1014
1015         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
1016         CPU_ANY_SSE4_FLAGS.
1017
1018 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
1019
1020         * i386-opc.tbl (movsx): Remove Intel syntax comments.
1021         (movzx): Likewise.
1022
1023 2020-02-14  Jan Beulich  <jbeulich@suse.com>
1024
1025         PR gas/25438
1026         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
1027         destination for Cpu64-only variant.
1028         (movzx): Fold patterns.
1029         * i386-tbl.h: Re-generate.
1030
1031 2020-02-13  Jan Beulich  <jbeulich@suse.com>
1032
1033         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
1034         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
1035         CPU_ANY_SSE4_FLAGS entry.
1036         * i386-init.h: Re-generate.
1037
1038 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1039
1040         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
1041         with Unspecified, making the present one AT&T syntax only.
1042         * i386-tbl.h: Re-generate.
1043
1044 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1045
1046         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
1047         * i386-tbl.h: Re-generate.
1048
1049 2020-02-12  Jan Beulich  <jbeulich@suse.com>
1050
1051         PR gas/24546
1052         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
1053         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
1054         Amd64 and Intel64 templates.
1055         (call, jmp): Likewise for far indirect variants. Dro
1056         Unspecified.
1057         * i386-tbl.h: Re-generate.
1058
1059 2020-02-11  Jan Beulich  <jbeulich@suse.com>
1060
1061         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
1062         * i386-opc.h (ShortForm): Delete.
1063         (struct i386_opcode_modifier): Remove shortform field.
1064         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
1065         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
1066         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
1067         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
1068         Drop ShortForm.
1069         * i386-tbl.h: Re-generate.
1070
1071 2020-02-11  Jan Beulich  <jbeulich@suse.com>
1072
1073         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
1074         fucompi): Drop ShortForm from operand-less templates.
1075         * i386-tbl.h: Re-generate.
1076
1077 2020-02-11  Alan Modra  <amodra@gmail.com>
1078
1079         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
1080         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
1081         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
1082         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
1083         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
1084
1085 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
1086
1087         * arm-dis.c (print_insn_cde): Define 'V' parse character.
1088         (cde_opcodes): Add VCX* instructions.
1089
1090 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
1091             Matthew Malcomson  <matthew.malcomson@arm.com>
1092
1093         * arm-dis.c (struct cdeopcode32): New.
1094         (CDE_OPCODE): New macro.
1095         (cde_opcodes): New disassembly table.
1096         (regnames): New option to table.
1097         (cde_coprocs): New global variable.
1098         (print_insn_cde): New
1099         (print_insn_thumb32): Use print_insn_cde.
1100         (parse_arm_disassembler_options): Parse coprocN args.
1101
1102 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
1103
1104         PR gas/25516
1105         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1106         with ISA64.
1107         * i386-opc.h (AMD64): Removed.
1108         (Intel64): Likewose.
1109         (AMD64): New.
1110         (INTEL64): Likewise.
1111         (INTEL64ONLY): Likewise.
1112         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1113         * i386-opc.tbl (Amd64): New.
1114         (Intel64): Likewise.
1115         (Intel64Only): Likewise.
1116         Replace AMD64 with Amd64.  Update sysenter/sysenter with
1117         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
1118         * i386-tbl.h: Regenerated.
1119
1120 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
1121
1122         PR 25469
1123         * z80-dis.c: Add support for GBZ80 opcodes.
1124
1125 2020-02-04  Alan Modra  <amodra@gmail.com>
1126
1127         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1128
1129 2020-02-03  Alan Modra  <amodra@gmail.com>
1130
1131         * m32c-ibld.c: Regenerate.
1132
1133 2020-02-01  Alan Modra  <amodra@gmail.com>
1134
1135         * frv-ibld.c: Regenerate.
1136
1137 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1138
1139         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1140         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1141         (OP_E_memory): Replace xmm_mdq_mode case label by
1142         vex_scalar_w_dq_mode one.
1143         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1144
1145 2020-01-31  Jan Beulich  <jbeulich@suse.com>
1146
1147         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1148         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1149         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1150         (intel_operand_size): Drop vex_w_dq_mode case label.
1151
1152 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
1153
1154         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1155         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1156
1157 2020-01-30  Alan Modra  <amodra@gmail.com>
1158
1159         * m32c-ibld.c: Regenerate.
1160
1161 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
1162
1163         * bpf-opc.c: Regenerate.
1164
1165 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1166
1167         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1168         (dis386): Use them to replace C2/C3 table entries.
1169         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1170         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1171         ones. Use Size64 instead of DefaultSize on Intel64 ones.
1172         * i386-tbl.h: Re-generate.
1173
1174 2020-01-30  Jan Beulich  <jbeulich@suse.com>
1175
1176         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1177         forms.
1178         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1179         DefaultSize.
1180         * i386-tbl.h: Re-generate.
1181
1182 2020-01-30  Alan Modra  <amodra@gmail.com>
1183
1184         * tic4x-dis.c (tic4x_dp): Make unsigned.
1185
1186 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
1187             Jan Beulich  <jbeulich@suse.com>
1188
1189         PR binutils/25445
1190         * i386-dis.c (MOVSXD_Fixup): New function.
1191         (movsxd_mode): New enum.
1192         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1193         (intel_operand_size): Handle movsxd_mode.
1194         (OP_E_register): Likewise.
1195         (OP_G): Likewise.
1196         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1197         register on movsxd.  Add movsxd with 16-bit destination register
1198         for AMD64 and Intel64 ISAs.
1199         * i386-tbl.h: Regenerated.
1200
1201 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
1202
1203         PR 25403
1204         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1205         * aarch64-asm-2.c: Regenerate
1206         * aarch64-dis-2.c: Likewise.
1207         * aarch64-opc-2.c: Likewise.
1208
1209 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1210
1211         * i386-opc.tbl (sysret): Drop DefaultSize.
1212         * i386-tbl.h: Re-generate.
1213
1214 2020-01-21  Jan Beulich  <jbeulich@suse.com>
1215
1216         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1217         Dword.
1218         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1219         * i386-tbl.h: Re-generate.
1220
1221 2020-01-20  Nick Clifton  <nickc@redhat.com>
1222
1223         * po/de.po: Updated German translation.
1224         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1225         * po/uk.po: Updated Ukranian translation.
1226
1227 2020-01-20  Alan Modra  <amodra@gmail.com>
1228
1229         * hppa-dis.c (fput_const): Remove useless cast.
1230
1231 2020-01-20  Alan Modra  <amodra@gmail.com>
1232
1233         * arm-dis.c (print_insn_arm): Wrap 'T' value.
1234
1235 2020-01-18  Nick Clifton  <nickc@redhat.com>
1236
1237         * configure: Regenerate.
1238         * po/opcodes.pot: Regenerate.
1239
1240 2020-01-18  Nick Clifton  <nickc@redhat.com>
1241
1242         Binutils 2.34 branch created.
1243
1244 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
1245
1246         * opintl.h: Fix spelling error (seperate).
1247
1248 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
1249
1250         * i386-opc.tbl: Add {vex} pseudo prefix.
1251         * i386-tbl.h: Regenerated.
1252
1253 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1254
1255         PR 25376
1256         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1257         (neon_opcodes): Likewise.
1258         (select_arm_features): Make sure we enable MVE bits when selecting
1259         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
1260         any architecture.
1261
1262 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1263
1264         * i386-opc.tbl: Drop stale comment from XOP section.
1265
1266 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1267
1268         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1269         (extractps): Add VexWIG to SSE2AVX forms.
1270         * i386-tbl.h: Re-generate.
1271
1272 2020-01-16  Jan Beulich  <jbeulich@suse.com>
1273
1274         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1275         Size64 from and use VexW1 on SSE2AVX forms.
1276         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1277         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1278         * i386-tbl.h: Re-generate.
1279
1280 2020-01-15  Alan Modra  <amodra@gmail.com>
1281
1282         * tic4x-dis.c (tic4x_version): Make unsigned long.
1283         (optab, optab_special, registernames): New file scope vars.
1284         (tic4x_print_register): Set up registernames rather than
1285         malloc'd registertable.
1286         (tic4x_disassemble): Delete optable and optable_special.  Use
1287         optab and optab_special instead.  Throw away old optab,
1288         optab_special and registernames when info->mach changes.
1289
1290 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
1291
1292         PR 25377
1293         * z80-dis.c (suffix): Use .db instruction to generate double
1294         prefix.
1295
1296 2020-01-14  Alan Modra  <amodra@gmail.com>
1297
1298         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
1299         values to unsigned before shifting.
1300
1301 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
1302
1303         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1304         flow instructions.
1305         (print_insn_thumb16, print_insn_thumb32): Likewise.
1306         (print_insn): Initialize the insn info.
1307         * i386-dis.c (print_insn): Initialize the insn info fields, and
1308         detect jumps.
1309
1310 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1311
1312         * arc-opc.c (C_NE): Make it required.
1313
1314 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
1315
1316         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1317         reserved register name.
1318
1319 2020-01-13  Alan Modra  <amodra@gmail.com>
1320
1321         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1322         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1323
1324 2020-01-13  Alan Modra  <amodra@gmail.com>
1325
1326         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
1327         result of wasm_read_leb128 in a uint64_t and check that bits
1328         are not lost when copying to other locals.  Use uint32_t for
1329         most locals.  Use PRId64 when printing int64_t.
1330
1331 2020-01-13  Alan Modra  <amodra@gmail.com>
1332
1333         * score-dis.c: Formatting.
1334         * score7-dis.c: Formatting.
1335
1336 2020-01-13  Alan Modra  <amodra@gmail.com>
1337
1338         * score-dis.c (print_insn_score48): Use unsigned variables for
1339         unsigned values.  Don't left shift negative values.
1340         (print_insn_score32): Likewise.
1341         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1342
1343 2020-01-13  Alan Modra  <amodra@gmail.com>
1344
1345         * tic4x-dis.c (tic4x_print_register): Remove dead code.
1346
1347 2020-01-13  Alan Modra  <amodra@gmail.com>
1348
1349         * fr30-ibld.c: Regenerate.
1350
1351 2020-01-13  Alan Modra  <amodra@gmail.com>
1352
1353         * xgate-dis.c (print_insn): Don't left shift signed value.
1354         (ripBits): Formatting, use 1u.
1355
1356 2020-01-10  Alan Modra  <amodra@gmail.com>
1357
1358         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1359         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
1360
1361 2020-01-10  Alan Modra  <amodra@gmail.com>
1362
1363         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1364         and XRREG value earlier to avoid a shift with negative exponent.
1365         * m10200-dis.c (disassemble): Similarly.
1366
1367 2020-01-09  Nick Clifton  <nickc@redhat.com>
1368
1369         PR 25224
1370         * z80-dis.c (ld_ii_ii): Use correct cast.
1371
1372 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
1373
1374         PR 25224
1375         * z80-dis.c (ld_ii_ii): Use character constant when checking
1376         opcode byte value.
1377
1378 2020-01-09  Jan Beulich  <jbeulich@suse.com>
1379
1380         * i386-dis.c (SEP_Fixup): New.
1381         (SEP): Define.
1382         (dis386_twobyte): Use it for sysenter/sysexit.
1383         (enum x86_64_isa): Change amd64 enumerator to value 1.
1384         (OP_J): Compare isa64 against intel64 instead of amd64.
1385         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1386         forms.
1387         * i386-tbl.h: Re-generate.
1388
1389 2020-01-08  Alan Modra  <amodra@gmail.com>
1390
1391         * z8k-dis.c: Include libiberty.h
1392         (instr_data_s): Make max_fetched unsigned.
1393         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1394         Don't exceed byte_info bounds.
1395         (output_instr): Make num_bytes unsigned.
1396         (unpack_instr): Likewise for nibl_count and loop.
1397         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1398         idx unsigned.
1399         * z8k-opc.h: Regenerate.
1400
1401 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
1402
1403         * arc-tbl.h (llock): Use 'LLOCK' as class.
1404         (llockd): Likewise.
1405         (scond): Use 'SCOND' as class.
1406         (scondd): Likewise.
1407         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1408         (scondd): Likewise.
1409
1410 2020-01-06  Alan Modra  <amodra@gmail.com>
1411
1412         * m32c-ibld.c: Regenerate.
1413
1414 2020-01-06  Alan Modra  <amodra@gmail.com>
1415
1416         PR 25344
1417         * z80-dis.c (suffix): Don't use a local struct buffer copy.
1418         Peek at next byte to prevent recursion on repeated prefix bytes.
1419         Ensure uninitialised "mybuf" is not accessed.
1420         (print_insn_z80): Don't zero n_fetch and n_used here,..
1421         (print_insn_z80_buf): ..do it here instead.
1422
1423 2020-01-04  Alan Modra  <amodra@gmail.com>
1424
1425         * m32r-ibld.c: Regenerate.
1426
1427 2020-01-04  Alan Modra  <amodra@gmail.com>
1428
1429         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1430
1431 2020-01-04  Alan Modra  <amodra@gmail.com>
1432
1433         * crx-dis.c (match_opcode): Avoid shift left of signed value.
1434
1435 2020-01-04  Alan Modra  <amodra@gmail.com>
1436
1437         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1438
1439 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1440
1441         * aarch64-tbl.h (aarch64_opcode_table): Use
1442         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1443
1444 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1445
1446         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1447         forms of SUDOT and USDOT.
1448
1449 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1450
1451         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1452         uzip{1,2}.
1453         * opcodes/aarch64-dis-2.c: Re-generate.
1454
1455 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1456
1457         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1458         FMMLA encoding.
1459         * opcodes/aarch64-dis-2.c: Re-generate.
1460
1461 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
1462
1463         * z80-dis.c: Add support for eZ80 and Z80 instructions.
1464
1465 2020-01-01  Alan Modra  <amodra@gmail.com>
1466
1467         Update year range in copyright notice of all files.
1468
1469 For older changes see ChangeLog-2019
1470 \f
1471 Copyright (C) 2020 Free Software Foundation, Inc.
1472
1473 Copying and distribution of this file, with or without modification,
1474 are permitted in any medium without royalty provided the copyright
1475 notice and this notice are preserved.
1476
1477 Local Variables:
1478 mode: change-log
1479 left-margin: 8
1480 fill-column: 74
1481 version-control: never
1482 End: