opcodes/ChangeLog

   1 2020-02-12  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
   4         with Unspecified, making the present one AT&T syntax only.
   5         * i386-tbl.h: Re-generate.
   6
   7 2020-02-12  Jan Beulich  <jbeulich@suse.com>
   8
   9         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
  10         * i386-tbl.h: Re-generate.
  11
  12 2020-02-12  Jan Beulich  <jbeulich@suse.com>
  13
  14         PR gas/24546
  15         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
  16         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
  17         Amd64 and Intel64 templates.
  18         (call, jmp): Likewise for far indirect variants. Dro
  19         Unspecified.
  20         * i386-tbl.h: Re-generate.
  21
  22 2020-02-11  Jan Beulich  <jbeulich@suse.com>
  23
  24         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
  25         * i386-opc.h (ShortForm): Delete.
  26         (struct i386_opcode_modifier): Remove shortform field.
  27         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
  28         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
  29         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
  30         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
  31         Drop ShortForm.
  32         * i386-tbl.h: Re-generate.
  33
  34 2020-02-11  Jan Beulich  <jbeulich@suse.com>
  35
  36         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
  37         fucompi): Drop ShortForm from operand-less templates.
  38         * i386-tbl.h: Re-generate.
  39
  40 2020-02-11  Alan Modra  <amodra@gmail.com>
  41
  42         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
  43         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
  44         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
  45         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
  46         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
  47
  48 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
  49
  50         * arm-dis.c (print_insn_cde): Define 'V' parse character.
  51         (cde_opcodes): Add VCX* instructions.
  52
  53 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
  54             Matthew Malcomson  <matthew.malcomson@arm.com>
  55
  56         * arm-dis.c (struct cdeopcode32): New.
  57         (CDE_OPCODE): New macro.
  58         (cde_opcodes): New disassembly table.
  59         (regnames): New option to table.
  60         (cde_coprocs): New global variable.
  61         (print_insn_cde): New
  62         (print_insn_thumb32): Use print_insn_cde.
  63         (parse_arm_disassembler_options): Parse coprocN args.
  64
  65 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
  66
  67         PR gas/25516
  68         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
  69         with ISA64.
  70         * i386-opc.h (AMD64): Removed.
  71         (Intel64): Likewose.
  72         (AMD64): New.
  73         (INTEL64): Likewise.
  74         (INTEL64ONLY): Likewise.
  75         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
  76         * i386-opc.tbl (Amd64): New.
  77         (Intel64): Likewise.
  78         (Intel64Only): Likewise.
  79         Replace AMD64 with Amd64.  Update sysenter/sysenter with
  80         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
  81         * i386-tbl.h: Regenerated.
  82
  83 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
  84
  85         PR 25469
  86         * z80-dis.c: Add support for GBZ80 opcodes.
  87
  88 2020-02-04  Alan Modra  <amodra@gmail.com>
  89
  90         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
  91
  92 2020-02-03  Alan Modra  <amodra@gmail.com>
  93
  94         * m32c-ibld.c: Regenerate.
  95
  96 2020-02-01  Alan Modra  <amodra@gmail.com>
  97
  98         * frv-ibld.c: Regenerate.
  99
 100 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 101
 102         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 103         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 104         (OP_E_memory): Replace xmm_mdq_mode case label by
 105         vex_scalar_w_dq_mode one.
 106         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 107
 108 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 109
 110         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 111         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 112         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 113         (intel_operand_size): Drop vex_w_dq_mode case label.
 114
 115 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 116
 117         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 118         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 119
 120 2020-01-30  Alan Modra  <amodra@gmail.com>
 121
 122         * m32c-ibld.c: Regenerate.
 123
 124 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 125
 126         * bpf-opc.c: Regenerate.
 127
 128 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 129
 130         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 131         (dis386): Use them to replace C2/C3 table entries.
 132         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 133         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 134         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 135         * i386-tbl.h: Re-generate.
 136
 137 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 138
 139         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 140         forms.
 141         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 142         DefaultSize.
 143         * i386-tbl.h: Re-generate.
 144
 145 2020-01-30  Alan Modra  <amodra@gmail.com>
 146
 147         * tic4x-dis.c (tic4x_dp): Make unsigned.
 148
 149 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 150             Jan Beulich  <jbeulich@suse.com>
 151
 152         PR binutils/25445
 153         * i386-dis.c (MOVSXD_Fixup): New function.
 154         (movsxd_mode): New enum.
 155         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 156         (intel_operand_size): Handle movsxd_mode.
 157         (OP_E_register): Likewise.
 158         (OP_G): Likewise.
 159         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 160         register on movsxd.  Add movsxd with 16-bit destination register
 161         for AMD64 and Intel64 ISAs.
 162         * i386-tbl.h: Regenerated.
 163
 164 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 165
 166         PR 25403
 167         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 168         * aarch64-asm-2.c: Regenerate
 169         * aarch64-dis-2.c: Likewise.
 170         * aarch64-opc-2.c: Likewise.
 171
 172 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 173
 174         * i386-opc.tbl (sysret): Drop DefaultSize.
 175         * i386-tbl.h: Re-generate.
 176
 177 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 178
 179         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 180         Dword.
 181         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 182         * i386-tbl.h: Re-generate.
 183
 184 2020-01-20  Nick Clifton  <nickc@redhat.com>
 185
 186         * po/de.po: Updated German translation.
 187         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 188         * po/uk.po: Updated Ukranian translation.
 189
 190 2020-01-20  Alan Modra  <amodra@gmail.com>
 191
 192         * hppa-dis.c (fput_const): Remove useless cast.
 193
 194 2020-01-20  Alan Modra  <amodra@gmail.com>
 195
 196         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 197
 198 2020-01-18  Nick Clifton  <nickc@redhat.com>
 199
 200         * configure: Regenerate.
 201         * po/opcodes.pot: Regenerate.
 202
 203 2020-01-18  Nick Clifton  <nickc@redhat.com>
 204
 205         Binutils 2.34 branch created.
 206
 207 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 208
 209         * opintl.h: Fix spelling error (seperate).
 210
 211 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 212
 213         * i386-opc.tbl: Add {vex} pseudo prefix.
 214         * i386-tbl.h: Regenerated.
 215
 216 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 217
 218         PR 25376
 219         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 220         (neon_opcodes): Likewise.
 221         (select_arm_features): Make sure we enable MVE bits when selecting
 222         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 223         any architecture.
 224
 225 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 226
 227         * i386-opc.tbl: Drop stale comment from XOP section.
 228
 229 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 230
 231         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 232         (extractps): Add VexWIG to SSE2AVX forms.
 233         * i386-tbl.h: Re-generate.
 234
 235 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 236
 237         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 238         Size64 from and use VexW1 on SSE2AVX forms.
 239         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 240         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 241         * i386-tbl.h: Re-generate.
 242
 243 2020-01-15  Alan Modra  <amodra@gmail.com>
 244
 245         * tic4x-dis.c (tic4x_version): Make unsigned long.
 246         (optab, optab_special, registernames): New file scope vars.
 247         (tic4x_print_register): Set up registernames rather than
 248         malloc'd registertable.
 249         (tic4x_disassemble): Delete optable and optable_special.  Use
 250         optab and optab_special instead.  Throw away old optab,
 251         optab_special and registernames when info->mach changes.
 252
 253 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 254
 255         PR 25377
 256         * z80-dis.c (suffix): Use .db instruction to generate double
 257         prefix.
 258
 259 2020-01-14  Alan Modra  <amodra@gmail.com>
 260
 261         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 262         values to unsigned before shifting.
 263
 264 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 265
 266         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 267         flow instructions.
 268         (print_insn_thumb16, print_insn_thumb32): Likewise.
 269         (print_insn): Initialize the insn info.
 270         * i386-dis.c (print_insn): Initialize the insn info fields, and
 271         detect jumps.
 272
 273 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 274
 275         * arc-opc.c (C_NE): Make it required.
 276
 277 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 278
 279         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 280         reserved register name.
 281
 282 2020-01-13  Alan Modra  <amodra@gmail.com>
 283
 284         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 285         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 286
 287 2020-01-13  Alan Modra  <amodra@gmail.com>
 288
 289         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 290         result of wasm_read_leb128 in a uint64_t and check that bits
 291         are not lost when copying to other locals.  Use uint32_t for
 292         most locals.  Use PRId64 when printing int64_t.
 293
 294 2020-01-13  Alan Modra  <amodra@gmail.com>
 295
 296         * score-dis.c: Formatting.
 297         * score7-dis.c: Formatting.
 298
 299 2020-01-13  Alan Modra  <amodra@gmail.com>
 300
 301         * score-dis.c (print_insn_score48): Use unsigned variables for
 302         unsigned values.  Don't left shift negative values.
 303         (print_insn_score32): Likewise.
 304         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 305
 306 2020-01-13  Alan Modra  <amodra@gmail.com>
 307
 308         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 309
 310 2020-01-13  Alan Modra  <amodra@gmail.com>
 311
 312         * fr30-ibld.c: Regenerate.
 313
 314 2020-01-13  Alan Modra  <amodra@gmail.com>
 315
 316         * xgate-dis.c (print_insn): Don't left shift signed value.
 317         (ripBits): Formatting, use 1u.
 318
 319 2020-01-10  Alan Modra  <amodra@gmail.com>
 320
 321         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 322         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 323
 324 2020-01-10  Alan Modra  <amodra@gmail.com>
 325
 326         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 327         and XRREG value earlier to avoid a shift with negative exponent.
 328         * m10200-dis.c (disassemble): Similarly.
 329
 330 2020-01-09  Nick Clifton  <nickc@redhat.com>
 331
 332         PR 25224
 333         * z80-dis.c (ld_ii_ii): Use correct cast.
 334
 335 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 336
 337         PR 25224
 338         * z80-dis.c (ld_ii_ii): Use character constant when checking
 339         opcode byte value.
 340
 341 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 342
 343         * i386-dis.c (SEP_Fixup): New.
 344         (SEP): Define.
 345         (dis386_twobyte): Use it for sysenter/sysexit.
 346         (enum x86_64_isa): Change amd64 enumerator to value 1.
 347         (OP_J): Compare isa64 against intel64 instead of amd64.
 348         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 349         forms.
 350         * i386-tbl.h: Re-generate.
 351
 352 2020-01-08  Alan Modra  <amodra@gmail.com>
 353
 354         * z8k-dis.c: Include libiberty.h
 355         (instr_data_s): Make max_fetched unsigned.
 356         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 357         Don't exceed byte_info bounds.
 358         (output_instr): Make num_bytes unsigned.
 359         (unpack_instr): Likewise for nibl_count and loop.
 360         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 361         idx unsigned.
 362         * z8k-opc.h: Regenerate.
 363
 364 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 365
 366         * arc-tbl.h (llock): Use 'LLOCK' as class.
 367         (llockd): Likewise.
 368         (scond): Use 'SCOND' as class.
 369         (scondd): Likewise.
 370         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 371         (scondd): Likewise.
 372
 373 2020-01-06  Alan Modra  <amodra@gmail.com>
 374
 375         * m32c-ibld.c: Regenerate.
 376
 377 2020-01-06  Alan Modra  <amodra@gmail.com>
 378
 379         PR 25344
 380         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 381         Peek at next byte to prevent recursion on repeated prefix bytes.
 382         Ensure uninitialised "mybuf" is not accessed.
 383         (print_insn_z80): Don't zero n_fetch and n_used here,..
 384         (print_insn_z80_buf): ..do it here instead.
 385
 386 2020-01-04  Alan Modra  <amodra@gmail.com>
 387
 388         * m32r-ibld.c: Regenerate.
 389
 390 2020-01-04  Alan Modra  <amodra@gmail.com>
 391
 392         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 393
 394 2020-01-04  Alan Modra  <amodra@gmail.com>
 395
 396         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 397
 398 2020-01-04  Alan Modra  <amodra@gmail.com>
 399
 400         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 401
 402 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 403
 404         * aarch64-tbl.h (aarch64_opcode_table): Use
 405         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 406
 407 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 408
 409         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 410         forms of SUDOT and USDOT.
 411
 412 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 413
 414         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 415         uzip{1,2}.
 416         * opcodes/aarch64-dis-2.c: Re-generate.
 417
 418 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 419
 420         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 421         FMMLA encoding.
 422         * opcodes/aarch64-dis-2.c: Re-generate.
 423
 424 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 425
 426         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 427
 428 2020-01-01  Alan Modra  <amodra@gmail.com>
 429
 430         Update year range in copyright notice of all files.
 431
 432 For older changes see ChangeLog-2019
 433 \f
 434 Copyright (C) 2020 Free Software Foundation, Inc.
 435
 436 Copying and distribution of this file, with or without modification,
 437 are permitted in any medium without royalty provided the copyright
 438 notice and this notice are preserved.
 439
 440 Local Variables:
 441 mode: change-log
 442 left-margin: 8
 443 fill-column: 74
 444 version-control: never
 445 End: