opcodes/ChangeLog

   1 2013-04-17  Wei-chen Wang  <cole945@gmail.com>
   2
   3         PR binutils/15369
   4         * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
   5         of CGEN_CPU_ENDIAN.
   6         (hash_insns_list): Likewise.
   7
   8 2013-04-10  Jan Kratochvil  <jan.kratochvil@redhat.com>
   9
  10         * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
  11         warning workaround.
  12
  13 2013-04-08  Jan Beulich <jbeulich@suse.com>
  14
  15         * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
  16         * i386-tbl.h: Re-generate.
  17
  18 2013-04-06  David S. Miller  <davem@davemloft.net>
  19
  20         * sparc-dis.c (compare_opcodes): When encountering multiple aliases
  21         of an opcode, prefer the one with F_PREFERRED set.
  22         * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
  23         lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
  24         ops.  Make 64-bit VIS logical ops have "d" suffix in their names,
  25         mark existing mnenomics as aliases.  Add "cc" suffix to edge
  26         instructions generating condition codes, mark existing mnenomics
  27         as aliases.  Add "fp" prefix to VIS compare instructions, mark
  28         existing mnenomics as aliases.
  29
  30 2013-04-03  Nick Clifton  <nickc@redhat.com>
  31
  32         * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
  33         destination address by subtracting the operand from the current
  34         address.
  35         * v850-opc.c (insert_u16_loop): Disallow negative offsets.  Store
  36         a positive value in the insn.
  37         (extract_u16_loop): Do not negate the returned value.
  38         (D16_LOOP): Add V850_INVERSE_PCREL flag.
  39
  40         (ceilf.sw): Remove duplicate entry.
  41         (cvtf.hs): New entry.
  42         (cvtf.sh): Likewise.
  43         (fmaf.s): Likewise.
  44         (fmsf.s): Likewise.
  45         (fnmaf.s): Likewise.
  46         (fnmsf.s): Likewise.
  47         (maddf.s): Restrict to E3V5 architectures.
  48         (msubf.s): Likewise.
  49         (nmaddf.s): Likewise.
  50         (nmsubf.s): Likewise.
  51
  52 2013-03-27  H.J. Lu  <hongjiu.lu@intel.com>
  53
  54         * i386-dis.c (get_sib): Add the sizeflag argument.  Properly
  55         check address mode.
  56         (print_insn): Pass sizeflag to get_sib.
  57
  58 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
  59
  60         PR binutils/15068
  61         * tic6x-dis.c: Add support for displaying 16-bit insns.
  62
  63 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
  64
  65         PR gas/15095
  66         * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
  67         individual msb and lsb halves in src1 & src2 fields.  Discard the
  68         src1 (lsb) value and only use src2 (msb), discarding bit 0, to
  69         follow what Ti SDK does in that case as any value in the src1
  70         field yields the same output with SDK disassembler.
  71
  72 2013-03-12  Michael Eager <eager@eagercon.com>
  73
  74         * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
  75
  76 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
  77
  78         * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
  79
  80 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
  81
  82         * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
  83
  84 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
  85
  86         * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
  87
  88 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
  89
  90         * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
  91         (thumb32_opcodes): Likewise.
  92         (print_insn_thumb32): Handle 'S' control char.
  93
  94 2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>
  95
  96         * lm32-desc.c: Regenerate.
  97
  98 2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>
  99
 100         * i386-reg.tbl (riz): Add RegRex64.
 101         * i386-tbl.h: Regenerated.
 102
 103 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
 104
 105         * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
 106         (aarch64_feature_crc): New static.
 107         (CRC): New macro.
 108         (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
 109         crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
 110         * aarch64-asm-2.c: Re-generate.
 111         * aarch64-dis-2.c: Ditto.
 112         * aarch64-opc-2.c: Ditto.
 113
 114 2013-02-27  Alan Modra  <amodra@gmail.com>
 115
 116         * rl78-decode.opc (rl78_decode_opcode): Fix typo.
 117         * rl78-decode.c: Regenerate.
 118
 119 2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>
 120
 121         * rl78-decode.opc: Fix encoding of DIVWU insn.
 122         * rl78-decode.c: Regenerate.
 123
 124 2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>
 125
 126         PR gas/15159
 127         * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
 128
 129         * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
 130         (cpu_flags): Add CpuSMAP.
 131
 132         * i386-opc.h (CpuSMAP): New.
 133         (i386_cpu_flags): Add cpusmap.
 134
 135         * i386-opc.tbl: Add clac and stac.
 136
 137         * i386-init.h: Regenerated.
 138         * i386-tbl.h: Likewise.
 139
 140 2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>
 141
 142         * metag-dis.c: Initialize outf->bytes_per_chunk to 4
 143         which also makes the disassembler output be in little
 144         endian like it should be.
 145
 146 2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>
 147
 148         * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
 149         fields to NULL.
 150         (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
 151
 152 2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>
 153
 154         * mips-dis.c (is_compressed_mode_p): Only match symbols from the
 155         section disassembled.
 156
 157 2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 158
 159         * arm-dis.c: Update strht pattern.
 160
 161 2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>
 162
 163         * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
 164         single-float.  Disable ll, lld, sc and scd for EE.  Disable the
 165         trunc.w.s macro for EE.
 166
 167 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
 168             Andrew Jenner <andrew@codesourcery.com>
 169
 170         Based on patches from Altera Corporation.
 171
 172         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
 173         nios2-opc.c.
 174         * Makefile.in: Regenerated.
 175         * configure.in: Add case for bfd_nios2_arch.
 176         * configure: Regenerated.
 177         * disassemble.c (ARCH_nios2): Define.
 178         (disassembler): Add case for bfd_arch_nios2.
 179         * nios2-dis.c: New file.
 180         * nios2-opc.c: New file.
 181
 182 2013-02-04  Alan Modra  <amodra@gmail.com>
 183
 184         * po/POTFILES.in: Regenerate.
 185         * rl78-decode.c: Regenerate.
 186         * rx-decode.c: Regenerate.
 187
 188 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
 189
 190         * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
 191         ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
 192         * aarch64-asm.c (convert_xtl_to_shll): New function.
 193         (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
 194         calling convert_xtl_to_shll.
 195         * aarch64-dis.c (convert_shll_to_xtl): New function.
 196         (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
 197         calling convert_shll_to_xtl.
 198         * aarch64-gen.c: Update copyright year.
 199         * aarch64-asm-2.c: Re-generate.
 200         * aarch64-dis-2.c: Re-generate.
 201         * aarch64-opc-2.c: Re-generate.
 202
 203 2013-01-24  Nick Clifton  <nickc@redhat.com>
 204
 205         * v850-dis.c: Add support for e3v5 architecture.
 206         * v850-opc.c: Likewise.
 207
 208 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
 209
 210         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
 211         * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
 212         * aarch64-opc.c (operand_general_constraint_met_p): For
 213         AARCH64_MOD_LSL, move the range check on the shift amount before the
 214         alignment check; change to call set_sft_amount_out_of_range_error
 215         instead of set_imm_out_of_range_error.
 216         * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
 217         (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
 218         8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
 219         SIMD_IMM_SFT.
 220
 221 2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>
 222
 223         * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
 224
 225         * i386-init.h: Regenerated.
 226         * i386-tbl.h: Likewise.
 227
 228 2013-01-15  Nick Clifton  <nickc@redhat.com>
 229
 230         * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
 231         values.
 232         * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
 233
 234 2013-01-14  Will Newton <will.newton@imgtec.com>
 235
 236         * metag-dis.c (REG_WIDTH): Increase to 64.
 237
 238 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
 239
 240         * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
 241         * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
 242         XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
 243         (SH6): Update.
 244         <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
 245         "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
 246         "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
 247         <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
 248
 249 2013-01-10  Will Newton <will.newton@imgtec.com>
 250
 251         * Makefile.am: Add Meta.
 252         * configure.in: Add Meta.
 253         * disassemble.c: Add Meta support.
 254         * metag-dis.c: New file.
 255         * Makefile.in: Regenerate.
 256         * configure: Regenerate.
 257
 258 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 259
 260         * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
 261         (match_opcode): Rename to cr16_match_opcode.
 262
 263 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
 264
 265         * mips-dis.c: Add names for CP0 registers of r5900.
 266         * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
 267         instructions sq and lq.
 268         Add support for MIPS r5900 CPU.
 269         Add support for 128 bit MMI (Multimedia Instructions).
 270         Add support for EE instructions (Emotion Engine).
 271         Disable unsupported floating point instructions (64 bit and
 272         undefined compare operations).
 273         Enable instructions of MIPS ISA IV which are supported by r5900.
 274         Disable 64 bit co processor instructions.
 275         Disable 64 bit multiplication and division instructions.
 276         Disable instructions for co-processor 2 and 3, because these are
 277         not supported (preparation for later VU0 support (Vector Unit)).
 278         Disable cvt.w.s because this behaves like trunc.w.s and the
 279         correct execution can't be ensured on r5900.
 280         Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
 281         will confuse less developers and compilers.
 282
 283 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
 284
 285         * aarch64-opc.c (aarch64_print_operand): Change to print
 286         AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
 287         in comment.
 288         * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
 289         from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
 290         OP_MOV_IMM_WIDE.
 291
 292 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
 293
 294         * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
 295         PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
 296
 297 2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
 298
 299         * i386-gen.c (process_copyright): Update copyright year to 2013.
 300
 301 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 302
 303         * cr16-dis.c (match_opcode,make_instruction): Remove static
 304         declaration.
 305         (dwordU,wordU): Moved typedefs to opcode/cr16.h
 306         (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
 307
 308 For older changes see ChangeLog-2012
 309 \f
 310 Copyright (C) 2013 Free Software Foundation, Inc.
 311
 312 Copying and distribution of this file, with or without modification,
 313 are permitted in any medium without royalty provided the copyright
 314 notice and this notice are preserved.
 315
 316 Local Variables:
 317 mode: change-log
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 319 fill-column: 74
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 321 End: