opcodes/ChangeLog

   1 2018-10-05  Sudakshina Das  <sudi.das@arm.com>
   2
   3         * arm-dis.c (arm_opcodes): Add sb.
   4         (thumb32_opcodes): Likewise.
   5
   6 2018-10-05  Richard Henderson  <rth@twiddle.net>
   7             Stafford Horne  <shorne@gmail.com>
   8
   9         * or1k-desc.c: Regenerate.
  10         * or1k-desc.h: Regenerate.
  11         * or1k-opc.c: Regenerate.
  12         * or1k-opc.h: Regenerate.
  13         * or1k-opinst.c: Regenerate.
  14
  15 2018-10-05  Richard Henderson  <rth@twiddle.net>
  16
  17         * or1k-asm.c: Regenerated.
  18         * or1k-desc.c: Regenerated.
  19         * or1k-desc.h: Regenerated.
  20         * or1k-dis.c: Regenerated.
  21         * or1k-ibld.c: Regenerated.
  22         * or1k-opc.c: Regenerated.
  23         * or1k-opc.h: Regenerated.
  24         * or1k-opinst.c: Regenerated.
  25
  26 2018-10-05  Richard Henderson  <rth@twiddle.net>
  27
  28         * or1k-asm.c: Regenerate.
  29
  30 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
  31
  32         * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
  33         * aarch64-dis.c (print_operands): Refactor to take notes.
  34         (print_verifier_notes): New.
  35         (print_aarch64_insn): Apply constraint verifier.
  36         (print_insn_aarch64_word): Update call to print_aarch64_insn.
  37         * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
  38
  39 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
  40
  41         * aarch64-opc.c (init_insn_block): New.
  42         (verify_constraints, aarch64_is_destructive_by_operands): New.
  43         * aarch64-opc.h (verify_constraints): New.
  44
  45 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
  46
  47         * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
  48         * aarch64-opc.c (verify_ldpsw): Update arguments.
  49
  50 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
  51
  52         * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
  53         (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
  54
  55 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
  56
  57         * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
  58         * aarch64-dis.c (insn_sequence): New.
  59
  60 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
  61
  62         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
  63         _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
  64         _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
  65         V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
  66         constraints.
  67         (_SVE_INSNC): New.
  68         (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
  69         constraints.
  70         (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
  71         F_SCAN flags.
  72         (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
  73         sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
  74         sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
  75         sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
  76         uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
  77         uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
  78         C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
  79
  80 2018-10-02  Palmer Dabbelt  <palmer@sifive.com>
  81
  82         * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
  83
  84 2018-09-23  Sandra Loosemore  <sandra@codesourcery.com>
  85
  86         * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
  87         are used when extracting signed fields and converting them to
  88         potentially 64-bit types.
  89
  90 2018-09-21  Simon Marchi  <simon.marchi@ericsson.com>
  91
  92         * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
  93         * Makefile.in: Re-generate.
  94         * aclocal.m4: Re-generate.
  95         * configure: Re-generate.
  96         * configure.ac: Remove check for -Wno-missing-field-initializers.
  97         * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
  98         (csky_v2_opcodes): Likewise.
  99
 100 2018-09-20  Maciej W. Rozycki  <macro@linux-mips.org>
 101
 102         * arc-nps400-tbl.h: Append `ull' to large constants throughout.
 103
 104 2018-09-20  Nelson Chu <nelson.chu1990@gmail.com>
 105
 106         * nds32-asm.c (operand_fields): Remove the unused fields.
 107         (nds32_opcodes): Remove the unused instructions.
 108         * nds32-dis.c (nds32_ex9_info): Removed.
 109         (nds32_parse_opcode): Updated.
 110         (print_insn_nds32): Likewise.
 111         * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
 112         (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
 113         (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
 114         build_opcode_hash_table): New functions.
 115         (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
 116         nds32_opcode_table): New.
 117         (hw_ktabs): Declare it to a pointer rather than an array.
 118         (build_hash_table): Removed.
 119         * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
 120         SYN_ROPT and upadte HW_GPR and HW_INT.
 121         * nds32-dis.c (keywords): Remove const.
 122         (match_field): New function.
 123         (nds32_parse_opcode): Updated.
 124         * disassemble.c (disassemble_init_for_target):
 125         Add disassemble_init_nds32.
 126         * nds32-dis.c (eum map_type): New.
 127         (nds32_private_data): Likewise.
 128         (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
 129         nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
 130         (print_insn_nds32): Updated.
 131         * nds32-asm.c (parse_aext_reg): Add new parameter.
 132         (parse_re, parse_re2, parse_aext_reg): Only reduced registers
 133         are allowed to use.
 134         All callers changed.
 135         * nds32-asm.c (keyword_usr, keyword_sr): Updated.
 136         (operand_fields): Add new fields.
 137         (nds32_opcodes): Add new instructions.
 138         (keyword_aridxi_mx): New keyword.
 139         * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
 140         and NASM_ATTR_ZOL.
 141         (ALU2_1, ALU2_2, ALU2_3): New macros.
 142         * nds32-dis.c (nds32_filter_unknown_insn): Updated.
 143
 144 2018-09-17  Kito Cheng  <kito@andestech.com>
 145
 146         * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
 147
 148 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 149
 150         PR gas/23670
 151         * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
 152         EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
 153         (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
 154         (EVEX_LEN_0F7E_P_1): Likewise.
 155         (EVEX_LEN_0F7E_P_2): Likewise.
 156         (EVEX_LEN_0FD6_P_2): Likewise.
 157         * i386-dis.c (USE_EVEX_LEN_TABLE): New.
 158         (EVEX_LEN_TABLE): Likewise.
 159         (EVEX_LEN_0F6E_P_2): New enum.
 160         (EVEX_LEN_0F7E_P_1): Likewise.
 161         (EVEX_LEN_0F7E_P_2): Likewise.
 162         (EVEX_LEN_0FD6_P_2): Likewise.
 163         (evex_len_table): New.
 164         (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
 165         * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
 166         * i386-tbl.h: Regenerated.
 167
 168 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 169
 170         PR gas/23665
 171         * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
 172         VEX_LEN_0F7E_P_2 entries.
 173         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
 174         * i386-tbl.h: Regenerated.
 175
 176 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 177
 178         * i386-dis.c (VZERO_Fixup): Removed.
 179         (VZERO): Likewise.
 180         (VEX_LEN_0F10_P_1): Likewise.
 181         (VEX_LEN_0F10_P_3): Likewise.
 182         (VEX_LEN_0F11_P_1): Likewise.
 183         (VEX_LEN_0F11_P_3): Likewise.
 184         (VEX_LEN_0F2E_P_0): Likewise.
 185         (VEX_LEN_0F2E_P_2): Likewise.
 186         (VEX_LEN_0F2F_P_0): Likewise.
 187         (VEX_LEN_0F2F_P_2): Likewise.
 188         (VEX_LEN_0F51_P_1): Likewise.
 189         (VEX_LEN_0F51_P_3): Likewise.
 190         (VEX_LEN_0F52_P_1): Likewise.
 191         (VEX_LEN_0F53_P_1): Likewise.
 192         (VEX_LEN_0F58_P_1): Likewise.
 193         (VEX_LEN_0F58_P_3): Likewise.
 194         (VEX_LEN_0F59_P_1): Likewise.
 195         (VEX_LEN_0F59_P_3): Likewise.
 196         (VEX_LEN_0F5A_P_1): Likewise.
 197         (VEX_LEN_0F5A_P_3): Likewise.
 198         (VEX_LEN_0F5C_P_1): Likewise.
 199         (VEX_LEN_0F5C_P_3): Likewise.
 200         (VEX_LEN_0F5D_P_1): Likewise.
 201         (VEX_LEN_0F5D_P_3): Likewise.
 202         (VEX_LEN_0F5E_P_1): Likewise.
 203         (VEX_LEN_0F5E_P_3): Likewise.
 204         (VEX_LEN_0F5F_P_1): Likewise.
 205         (VEX_LEN_0F5F_P_3): Likewise.
 206         (VEX_LEN_0FC2_P_1): Likewise.
 207         (VEX_LEN_0FC2_P_3): Likewise.
 208         (VEX_LEN_0F3A0A_P_2): Likewise.
 209         (VEX_LEN_0F3A0B_P_2): Likewise.
 210         (VEX_W_0F10_P_0): Likewise.
 211         (VEX_W_0F10_P_1): Likewise.
 212         (VEX_W_0F10_P_2): Likewise.
 213         (VEX_W_0F10_P_3): Likewise.
 214         (VEX_W_0F11_P_0): Likewise.
 215         (VEX_W_0F11_P_1): Likewise.
 216         (VEX_W_0F11_P_2): Likewise.
 217         (VEX_W_0F11_P_3): Likewise.
 218         (VEX_W_0F12_P_0_M_0): Likewise.
 219         (VEX_W_0F12_P_0_M_1): Likewise.
 220         (VEX_W_0F12_P_1): Likewise.
 221         (VEX_W_0F12_P_2): Likewise.
 222         (VEX_W_0F12_P_3): Likewise.
 223         (VEX_W_0F13_M_0): Likewise.
 224         (VEX_W_0F14): Likewise.
 225         (VEX_W_0F15): Likewise.
 226         (VEX_W_0F16_P_0_M_0): Likewise.
 227         (VEX_W_0F16_P_0_M_1): Likewise.
 228         (VEX_W_0F16_P_1): Likewise.
 229         (VEX_W_0F16_P_2): Likewise.
 230         (VEX_W_0F17_M_0): Likewise.
 231         (VEX_W_0F28): Likewise.
 232         (VEX_W_0F29): Likewise.
 233         (VEX_W_0F2B_M_0): Likewise.
 234         (VEX_W_0F2E_P_0): Likewise.
 235         (VEX_W_0F2E_P_2): Likewise.
 236         (VEX_W_0F2F_P_0): Likewise.
 237         (VEX_W_0F2F_P_2): Likewise.
 238         (VEX_W_0F50_M_0): Likewise.
 239         (VEX_W_0F51_P_0): Likewise.
 240         (VEX_W_0F51_P_1): Likewise.
 241         (VEX_W_0F51_P_2): Likewise.
 242         (VEX_W_0F51_P_3): Likewise.
 243         (VEX_W_0F52_P_0): Likewise.
 244         (VEX_W_0F52_P_1): Likewise.
 245         (VEX_W_0F53_P_0): Likewise.
 246         (VEX_W_0F53_P_1): Likewise.
 247         (VEX_W_0F58_P_0): Likewise.
 248         (VEX_W_0F58_P_1): Likewise.
 249         (VEX_W_0F58_P_2): Likewise.
 250         (VEX_W_0F58_P_3): Likewise.
 251         (VEX_W_0F59_P_0): Likewise.
 252         (VEX_W_0F59_P_1): Likewise.
 253         (VEX_W_0F59_P_2): Likewise.
 254         (VEX_W_0F59_P_3): Likewise.
 255         (VEX_W_0F5A_P_0): Likewise.
 256         (VEX_W_0F5A_P_1): Likewise.
 257         (VEX_W_0F5A_P_3): Likewise.
 258         (VEX_W_0F5B_P_0): Likewise.
 259         (VEX_W_0F5B_P_1): Likewise.
 260         (VEX_W_0F5B_P_2): Likewise.
 261         (VEX_W_0F5C_P_0): Likewise.
 262         (VEX_W_0F5C_P_1): Likewise.
 263         (VEX_W_0F5C_P_2): Likewise.
 264         (VEX_W_0F5C_P_3): Likewise.
 265         (VEX_W_0F5D_P_0): Likewise.
 266         (VEX_W_0F5D_P_1): Likewise.
 267         (VEX_W_0F5D_P_2): Likewise.
 268         (VEX_W_0F5D_P_3): Likewise.
 269         (VEX_W_0F5E_P_0): Likewise.
 270         (VEX_W_0F5E_P_1): Likewise.
 271         (VEX_W_0F5E_P_2): Likewise.
 272         (VEX_W_0F5E_P_3): Likewise.
 273         (VEX_W_0F5F_P_0): Likewise.
 274         (VEX_W_0F5F_P_1): Likewise.
 275         (VEX_W_0F5F_P_2): Likewise.
 276         (VEX_W_0F5F_P_3): Likewise.
 277         (VEX_W_0F60_P_2): Likewise.
 278         (VEX_W_0F61_P_2): Likewise.
 279         (VEX_W_0F62_P_2): Likewise.
 280         (VEX_W_0F63_P_2): Likewise.
 281         (VEX_W_0F64_P_2): Likewise.
 282         (VEX_W_0F65_P_2): Likewise.
 283         (VEX_W_0F66_P_2): Likewise.
 284         (VEX_W_0F67_P_2): Likewise.
 285         (VEX_W_0F68_P_2): Likewise.
 286         (VEX_W_0F69_P_2): Likewise.
 287         (VEX_W_0F6A_P_2): Likewise.
 288         (VEX_W_0F6B_P_2): Likewise.
 289         (VEX_W_0F6C_P_2): Likewise.
 290         (VEX_W_0F6D_P_2): Likewise.
 291         (VEX_W_0F6F_P_1): Likewise.
 292         (VEX_W_0F6F_P_2): Likewise.
 293         (VEX_W_0F70_P_1): Likewise.
 294         (VEX_W_0F70_P_2): Likewise.
 295         (VEX_W_0F70_P_3): Likewise.
 296         (VEX_W_0F71_R_2_P_2): Likewise.
 297         (VEX_W_0F71_R_4_P_2): Likewise.
 298         (VEX_W_0F71_R_6_P_2): Likewise.
 299         (VEX_W_0F72_R_2_P_2): Likewise.
 300         (VEX_W_0F72_R_4_P_2): Likewise.
 301         (VEX_W_0F72_R_6_P_2): Likewise.
 302         (VEX_W_0F73_R_2_P_2): Likewise.
 303         (VEX_W_0F73_R_3_P_2): Likewise.
 304         (VEX_W_0F73_R_6_P_2): Likewise.
 305         (VEX_W_0F73_R_7_P_2): Likewise.
 306         (VEX_W_0F74_P_2): Likewise.
 307         (VEX_W_0F75_P_2): Likewise.
 308         (VEX_W_0F76_P_2): Likewise.
 309         (VEX_W_0F77_P_0): Likewise.
 310         (VEX_W_0F7C_P_2): Likewise.
 311         (VEX_W_0F7C_P_3): Likewise.
 312         (VEX_W_0F7D_P_2): Likewise.
 313         (VEX_W_0F7D_P_3): Likewise.
 314         (VEX_W_0F7E_P_1): Likewise.
 315         (VEX_W_0F7F_P_1): Likewise.
 316         (VEX_W_0F7F_P_2): Likewise.
 317         (VEX_W_0FAE_R_2_M_0): Likewise.
 318         (VEX_W_0FAE_R_3_M_0): Likewise.
 319         (VEX_W_0FC2_P_0): Likewise.
 320         (VEX_W_0FC2_P_1): Likewise.
 321         (VEX_W_0FC2_P_2): Likewise.
 322         (VEX_W_0FC2_P_3): Likewise.
 323         (VEX_W_0FD0_P_2): Likewise.
 324         (VEX_W_0FD0_P_3): Likewise.
 325         (VEX_W_0FD1_P_2): Likewise.
 326         (VEX_W_0FD2_P_2): Likewise.
 327         (VEX_W_0FD3_P_2): Likewise.
 328         (VEX_W_0FD4_P_2): Likewise.
 329         (VEX_W_0FD5_P_2): Likewise.
 330         (VEX_W_0FD6_P_2): Likewise.
 331         (VEX_W_0FD7_P_2_M_1): Likewise.
 332         (VEX_W_0FD8_P_2): Likewise.
 333         (VEX_W_0FD9_P_2): Likewise.
 334         (VEX_W_0FDA_P_2): Likewise.
 335         (VEX_W_0FDB_P_2): Likewise.
 336         (VEX_W_0FDC_P_2): Likewise.
 337         (VEX_W_0FDD_P_2): Likewise.
 338         (VEX_W_0FDE_P_2): Likewise.
 339         (VEX_W_0FDF_P_2): Likewise.
 340         (VEX_W_0FE0_P_2): Likewise.
 341         (VEX_W_0FE1_P_2): Likewise.
 342         (VEX_W_0FE2_P_2): Likewise.
 343         (VEX_W_0FE3_P_2): Likewise.
 344         (VEX_W_0FE4_P_2): Likewise.
 345         (VEX_W_0FE5_P_2): Likewise.
 346         (VEX_W_0FE6_P_1): Likewise.
 347         (VEX_W_0FE6_P_2): Likewise.
 348         (VEX_W_0FE6_P_3): Likewise.
 349         (VEX_W_0FE7_P_2_M_0): Likewise.
 350         (VEX_W_0FE8_P_2): Likewise.
 351         (VEX_W_0FE9_P_2): Likewise.
 352         (VEX_W_0FEA_P_2): Likewise.
 353         (VEX_W_0FEB_P_2): Likewise.
 354         (VEX_W_0FEC_P_2): Likewise.
 355         (VEX_W_0FED_P_2): Likewise.
 356         (VEX_W_0FEE_P_2): Likewise.
 357         (VEX_W_0FEF_P_2): Likewise.
 358         (VEX_W_0FF0_P_3_M_0): Likewise.
 359         (VEX_W_0FF1_P_2): Likewise.
 360         (VEX_W_0FF2_P_2): Likewise.
 361         (VEX_W_0FF3_P_2): Likewise.
 362         (VEX_W_0FF4_P_2): Likewise.
 363         (VEX_W_0FF5_P_2): Likewise.
 364         (VEX_W_0FF6_P_2): Likewise.
 365         (VEX_W_0FF7_P_2): Likewise.
 366         (VEX_W_0FF8_P_2): Likewise.
 367         (VEX_W_0FF9_P_2): Likewise.
 368         (VEX_W_0FFA_P_2): Likewise.
 369         (VEX_W_0FFB_P_2): Likewise.
 370         (VEX_W_0FFC_P_2): Likewise.
 371         (VEX_W_0FFD_P_2): Likewise.
 372         (VEX_W_0FFE_P_2): Likewise.
 373         (VEX_W_0F3800_P_2): Likewise.
 374         (VEX_W_0F3801_P_2): Likewise.
 375         (VEX_W_0F3802_P_2): Likewise.
 376         (VEX_W_0F3803_P_2): Likewise.
 377         (VEX_W_0F3804_P_2): Likewise.
 378         (VEX_W_0F3805_P_2): Likewise.
 379         (VEX_W_0F3806_P_2): Likewise.
 380         (VEX_W_0F3807_P_2): Likewise.
 381         (VEX_W_0F3808_P_2): Likewise.
 382         (VEX_W_0F3809_P_2): Likewise.
 383         (VEX_W_0F380A_P_2): Likewise.
 384         (VEX_W_0F380B_P_2): Likewise.
 385         (VEX_W_0F3817_P_2): Likewise.
 386         (VEX_W_0F381C_P_2): Likewise.
 387         (VEX_W_0F381D_P_2): Likewise.
 388         (VEX_W_0F381E_P_2): Likewise.
 389         (VEX_W_0F3820_P_2): Likewise.
 390         (VEX_W_0F3821_P_2): Likewise.
 391         (VEX_W_0F3822_P_2): Likewise.
 392         (VEX_W_0F3823_P_2): Likewise.
 393         (VEX_W_0F3824_P_2): Likewise.
 394         (VEX_W_0F3825_P_2): Likewise.
 395         (VEX_W_0F3828_P_2): Likewise.
 396         (VEX_W_0F3829_P_2): Likewise.
 397         (VEX_W_0F382A_P_2_M_0): Likewise.
 398         (VEX_W_0F382B_P_2): Likewise.
 399         (VEX_W_0F3830_P_2): Likewise.
 400         (VEX_W_0F3831_P_2): Likewise.
 401         (VEX_W_0F3832_P_2): Likewise.
 402         (VEX_W_0F3833_P_2): Likewise.
 403         (VEX_W_0F3834_P_2): Likewise.
 404         (VEX_W_0F3835_P_2): Likewise.
 405         (VEX_W_0F3837_P_2): Likewise.
 406         (VEX_W_0F3838_P_2): Likewise.
 407         (VEX_W_0F3839_P_2): Likewise.
 408         (VEX_W_0F383A_P_2): Likewise.
 409         (VEX_W_0F383B_P_2): Likewise.
 410         (VEX_W_0F383C_P_2): Likewise.
 411         (VEX_W_0F383D_P_2): Likewise.
 412         (VEX_W_0F383E_P_2): Likewise.
 413         (VEX_W_0F383F_P_2): Likewise.
 414         (VEX_W_0F3840_P_2): Likewise.
 415         (VEX_W_0F3841_P_2): Likewise.
 416         (VEX_W_0F38DB_P_2): Likewise.
 417         (VEX_W_0F3A08_P_2): Likewise.
 418         (VEX_W_0F3A09_P_2): Likewise.
 419         (VEX_W_0F3A0A_P_2): Likewise.
 420         (VEX_W_0F3A0B_P_2): Likewise.
 421         (VEX_W_0F3A0C_P_2): Likewise.
 422         (VEX_W_0F3A0D_P_2): Likewise.
 423         (VEX_W_0F3A0E_P_2): Likewise.
 424         (VEX_W_0F3A0F_P_2): Likewise.
 425         (VEX_W_0F3A21_P_2): Likewise.
 426         (VEX_W_0F3A40_P_2): Likewise.
 427         (VEX_W_0F3A41_P_2): Likewise.
 428         (VEX_W_0F3A42_P_2): Likewise.
 429         (VEX_W_0F3A62_P_2): Likewise.
 430         (VEX_W_0F3A63_P_2): Likewise.
 431         (VEX_W_0F3ADF_P_2): Likewise.
 432         (VEX_LEN_0F77_P_0): New.
 433         (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
 434         PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
 435         PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
 436         PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
 437         PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
 438         PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
 439         PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
 440         PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
 441         PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
 442         PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
 443         PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
 444         PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
 445         PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
 446         PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
 447         PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
 448         PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
 449         PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
 450         PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
 451         PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
 452         PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
 453         PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
 454         PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
 455         PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
 456         PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
 457         PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
 458         PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
 459         PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
 460         PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
 461         PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
 462         PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
 463         PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
 464         PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
 465         PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
 466         PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
 467         PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
 468         PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
 469         PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
 470         PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
 471         PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
 472         PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
 473         PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
 474         PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
 475         PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
 476         PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
 477         PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
 478         PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
 479         PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
 480         PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
 481         PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
 482         (vex_table): Update VEX 0F28 and 0F29 entries.
 483         (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
 484         VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
 485         VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
 486         VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
 487         VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
 488         VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
 489         VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
 490         VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
 491         VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
 492         VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
 493         VEX_LEN_0F3A0B_P_2 entries.
 494         (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
 495         VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
 496         VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
 497         VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
 498         VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
 499         VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
 500         VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
 501         VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
 502         VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
 503         VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
 504         VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
 505         VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
 506         VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
 507         VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
 508         VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
 509         VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
 510         VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
 511         VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
 512         VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
 513         VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
 514         VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
 515         VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
 516         VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
 517         VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
 518         VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
 519         VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
 520         VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
 521         VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
 522         VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
 523         VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
 524         VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
 525         VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
 526         VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
 527         VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
 528         VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
 529         VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
 530         VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
 531         VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
 532         VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
 533         VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
 534         VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
 535         VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
 536         VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
 537         VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
 538         VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
 539         VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
 540         VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
 541         VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
 542         VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
 543         VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
 544         VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
 545         VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
 546         VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
 547         VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
 548         VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
 549         VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
 550         VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
 551         VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
 552         VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
 553         VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
 554         VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
 555         VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
 556         VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
 557         VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
 558         VEX_W_0F3ADF_P_2 entries.
 559         (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
 560         MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
 561         MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
 562
 563 2018-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 564
 565         * i386-opc.tbl (VexWIG): New.
 566         Replace VexW=3 with VexWIG.
 567
 568 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 569
 570         * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
 571         * i386-tbl.h: Regenerated.
 572
 573 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 574
 575         PR gas/23665
 576         * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
 577         VEX_LEN_0FD6_P_2 entries.
 578         * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
 579         * i386-tbl.h: Regenerated.
 580
 581 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 582
 583         PR gas/23642
 584         * i386-opc.h (VEXWIG): New.
 585         * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
 586         * i386-tbl.h: Regenerated.
 587
 588 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 589
 590         PR binutils/23655
 591         * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
 592         vcvtsi2sd%LQ and vcvtusi2sd%LQ.
 593         * i386-dis.c (EXxEVexR64): New.
 594         (evex_rounding_64_mode): Likewise.
 595         (OP_Rounding): Handle evex_rounding_64_mode.
 596
 597 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 598
 599         PR binutils/23655
 600         * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
 601         vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
 602         * i386-dis.c (Edqa): New.
 603         (dqa_mode): Likewise.
 604         (intel_operand_size): Handle dqa_mode as m_mode.
 605         (OP_E_register): Handle dqa_mode as dq_mode.
 606         (OP_E_memory): Set shift for dqa_mode based on address_mode.
 607
 608 2018-09-14  H.J. Lu  <hongjiu.lu@intel.com>
 609
 610         * i386-dis.c (OP_E_memory): Reformat.
 611
 612 2018-09-14  Jan Beulich  <jbeulich@suse.com>
 613
 614         * i386-opc.tbl (crc32): Fold byte and word forms.
 615         * i386-tbl.h: Re-generate.
 616
 617 2018-09-13  H.J. Lu  <hongjiu.lu@intel.com>
 618
 619         * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
 620         pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
 621         Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
 622         vpinsrq.  Remove VexW=1 from WIG VEX movq and vmovq.
 623         * i386-tbl.h: Regenerated.
 624
 625 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 626
 627         * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
 628         meaningless.
 629         (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
 630         xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
 631         rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
 632         * i386-tbl.h: Re-generate.
 633
 634 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 635
 636         * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
 637         AVX512_4VNNIW insns.
 638         * i386-tbl.h: Re-generate.
 639
 640 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 641
 642         * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
 643         meaningless.
 644         * i386-tbl.h: Re-generate.
 645
 646 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 647
 648         * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
 649         meaningless.
 650         * i386-tbl.h: Re-generate.
 651
 652 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 653
 654         * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
 655         meaningless.
 656         * i386-tbl.h: Re-generate.
 657
 658 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 659
 660         * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
 661         meaningless.
 662         * i386-tbl.h: Re-generate.
 663
 664 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 665
 666         * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
 667         meaningless.
 668         * i386-tbl.h: Re-generate.
 669
 670 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 671
 672         * i386-opc.tbl: Drop IgnoreSize from SHA insns.
 673         * i386-tbl.h: Re-generate.
 674
 675 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 676
 677         * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
 678         * i386-tbl.h: Re-generate.
 679
 680 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 681
 682         * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
 683         meaningless.
 684         * i386-tbl.h: Re-generate.
 685
 686 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 687
 688         * i386-opc.tbl: Drop IgnoreSize from AVX insns where
 689         meaningless.
 690         * i386-tbl.h: Re-generate.
 691
 692 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 693
 694         * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
 695         * i386-tbl.h: Re-generate.
 696
 697 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 698
 699         * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
 700         * i386-tbl.h: Re-generate.
 701
 702 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 703
 704         * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
 705         * i386-tbl.h: Re-generate.
 706
 707 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 708
 709         * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
 710         meaningless.
 711         * i386-tbl.h: Re-generate.
 712
 713 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 714
 715         * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
 716         meaningless.
 717         * i386-tbl.h: Re-generate.
 718
 719 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 720
 721         * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
 722         meaningless.
 723         * i386-tbl.h: Re-generate.
 724
 725 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 726
 727         * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
 728         * i386-tbl.h: Re-generate.
 729
 730 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 731
 732         * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
 733         * i386-tbl.h: Re-generate.
 734
 735 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 736
 737         * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
 738         * i386-tbl.h: Re-generate.
 739
 740 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 741
 742         * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
 743         (vpbroadcastw, rdpid): Drop NoRex64.
 744         * i386-tbl.h: Re-generate.
 745
 746 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 747
 748         * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
 749         store templates, adding D.
 750         * i386-tbl.h: Re-generate.
 751
 752 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 753
 754         * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
 755         movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
 756         movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
 757         vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
 758         vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
 759         Fold load and store templates where possible, adding D. Drop
 760         IgnoreSize where it was pointlessly present. Drop redundant
 761         *word.
 762         * i386-tbl.h: Re-generate.
 763
 764 2018-09-13  Jan Beulich  <jbeulich@suse.com>
 765
 766         * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
 767         (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
 768         (intel_operand_size): Handle v_bndmk_mode.
 769         (OP_E_memory): Likewise. Produce (bad) when also riprel.
 770
 771 2018-09-08  John Darrington  <john@darrington.wattle.id.au>
 772
 773         * disassemble.c (ARCH_s12z): Define if ARCH_all.
 774
 775 2018-08-31  Kito Cheng  <kito@andestech.com>
 776
 777         * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
 778         compressed floating point instructions.
 779
 780 2018-08-30  Kito Cheng  <kito@andestech.com>
 781
 782         * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
 783         riscv_opcode.xlen_requirement.
 784         * riscv-opc.c (riscv_opcodes): Update for struct change.
 785
 786 2018-08-29  Martin Aberg  <maberg@gaisler.com>
 787
 788         * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
 789         psr (PWRPSR) instruction.
 790
 791 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 792
 793         * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
 794
 795 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 796
 797         * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
 798
 799 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 800
 801         * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
 802         loongson3a as an alias of gs464 for compatibility.
 803         * mips-opc.c (mips_opcodes): Change Comments.
 804
 805 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 806
 807         * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
 808         option.
 809         (print_mips_disassembler_options): Document -M loongson-ext.
 810         * mips-opc.c (LEXT2): New macro.
 811         (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
 812
 813 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 814
 815          * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
 816          descriptors.
 817          (parse_mips_ase_option): Handle -M loongson-ext option.
 818          (print_mips_disassembler_options): Document -M loongson-ext.
 819          * mips-opc.c (IL3A): Delete.
 820          * mips-opc.c (LEXT): New macro.
 821          (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
 822          instructions.
 823
 824 2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
 825
 826         * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
 827         descriptors.
 828         (parse_mips_ase_option): Handle -M loongson-cam option.
 829         (print_mips_disassembler_options): Document -M loongson-cam.
 830         * mips-opc.c (LCAM): New macro.
 831         (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
 832         instructions.
 833
 834 2018-08-21  Alan Modra  <amodra@gmail.com>
 835
 836         * ppc-dis.c (operand_value_powerpc): Init "invalid".
 837         (skip_optional_operands): Count optional operands, and update
 838         ppc_optional_operand_value call.
 839         * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
 840         (extract_vlensi): Likewise.
 841         (extract_fxm): Return default value for missing optional operand.
 842         (extract_ls, extract_raq, extract_tbr): Likewise.
 843         (insert_sxl, extract_sxl): New functions.
 844         (insert_esync, extract_esync): Remove Power9 handling and simplify.
 845         (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
 846         flag and extra entry.
 847         (powerpc_operands <SXL>): Likewise, and use insert_sxl and
 848         extract_sxl.
 849
 850 2018-08-20  Alan Modra  <amodra@gmail.com>
 851
 852         * sh-opc.h (MASK): Simplify.
 853
 854 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 855
 856         * s12z-dis.c (bm_decode): Deal with cases where the mode is
 857         BM_RESERVED0 or BM_RESERVED1
 858         (bm_rel_decode, bm_n_bytes): Ditto.
 859
 860 2018-08-18  John Darrington  <john@darrington.wattle.id.au>
 861
 862         * s12z.h: Delete.
 863
 864 2018-08-14  H.J. Lu  <hongjiu.lu@intel.com>
 865
 866         * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
 867         address with the addr32 prefix and without base nor index
 868         registers.
 869
 870 2018-08-11  H.J. Lu  <hongjiu.lu@intel.com>
 871
 872         * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
 873         CPU_I686_FLAGS.  Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
 874         CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
 875         (cpu_flags): Add CpuCMOV and CpuFXSR.
 876         * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
 877         fxrstor and fxrstor64.  Replace Cpu686 with CpuCMOV on cmovCC.
 878         * i386-init.h: Regenerated.
 879         * i386-tbl.h: Likewise.
 880
 881 2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
 882
 883         * arc-regs.h: Update auxiliary registers.
 884
 885 2018-08-06  Jan Beulich  <jbeulich@suse.com>
 886
 887         * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
 888         (RegIP, RegIZ): Define.
 889         * i386-reg.tbl: Adjust comments.
 890         (rip): Use Qword instead of BaseIndex. Use RegIP.
 891         (eip): Use Dword instead of BaseIndex. Use RegIP.
 892         (riz): Add Qword. Use RegIZ.
 893         (eiz): Add Dword. Use RegIZ.
 894         * i386-tbl.h: Re-generate.
 895
 896 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 897
 898         * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
 899         pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
 900         vpmovzxdq, vpmovzxwd): Remove NoRex64.
 901         * i386-tbl.h: Re-generate.
 902
 903 2018-08-03  Jan Beulich  <jbeulich@suse.com>
 904
 905         * i386-gen.c (operand_types): Remove Mem field.
 906         * i386-opc.h (union i386_operand_type): Remove mem field.
 907         * i386-init.h, i386-tbl.h: Re-generate.
 908
 909 2018-08-01  Alan Modra  <amodra@gmail.com>
 910
 911         * po/POTFILES.in: Regenerate.
 912
 913 2018-07-31  Nick Clifton  <nickc@redhat.com>
 914
 915         * po/sv.po: Updated Swedish translation.
 916
 917 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 918
 919         * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
 920         * i386-init.h, i386-tbl.h: Re-generate.
 921
 922 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 923
 924         * i386-opc.h (ZEROING_MASKING) Rename to ...
 925         (DYNAMIC_MASKING): ... this. Adjust comment.
 926         * i386-opc.tbl (MaskingMorZ): Define.
 927         (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
 928         vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
 929         vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
 930         vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
 931         vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
 932         vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
 933         vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
 934         vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
 935         vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
 936
 937 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 938
 939         * i386-opc.tbl: Use element rather than vector size for AVX512*
 940         scatter/gather insns.
 941         * i386-tbl.h: Re-generate.
 942
 943 2018-07-31  Jan Beulich  <jbeulich@suse.com>
 944
 945         * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
 946         (cpu_flags): Drop CpuVREX.
 947         * i386-opc.h (CpuVREX): Delete.
 948         (union i386_cpu_flags): Remove cpuvrex.
 949         * i386-init.h, i386-tbl.h: Re-generate.
 950
 951 2018-07-30  Jim Wilson  <jimw@sifive.com>
 952
 953         * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
 954         fields.
 955         * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
 956
 957 2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
 958
 959         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
 960         * Makefile.in: Regenerated.
 961         * configure.ac: Add C-SKY.
 962         * configure: Regenerated.
 963         * csky-dis.c: New file.
 964         * csky-opc.h: New file.
 965         * disassemble.c (ARCH_csky): Define.
 966         (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
 967         * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
 968
 969 2018-07-27  Alan Modra  <amodra@gmail.com>
 970
 971         * ppc-opc.c (insert_sprbat): Correct function parameter and
 972         return type.
 973         (extract_sprbat): Likewise, variable too.
 974
 975 2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
 976             Alan Modra  <amodra@gmail.com>
 977
 978         * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
 979         (powerpc_init_dialect): Handle bfd_mach_ppc_750.
 980         * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
 981         support disjointed BAT.
 982         (powerpc_operands): Allow extra bit in SPRBAT_MASK.  Add SPRGQR.
 983         (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
 984         (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
 985
 986 2018-07-25  H.J. Lu  <hongjiu.lu@intel.com>
 987             Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 988
 989         * i386-gen.c (adjust_broadcast_modifier): New function.
 990         (process_i386_opcode_modifier): Add an argument for operands.
 991         Adjust the Broadcast value based on operands.
 992         (output_i386_opcode): Pass operand_types to
 993         process_i386_opcode_modifier.
 994         (process_i386_opcodes): Pass NULL as operands to
 995         process_i386_opcode_modifier.
 996         * i386-opc.h (BYTE_BROADCAST): New.
 997         (WORD_BROADCAST): Likewise.
 998         (DWORD_BROADCAST): Likewise.
 999         (QWORD_BROADCAST): Likewise.
1000         (i386_opcode_modifier): Expand broadcast to 3 bits.
1001         * i386-tbl.h: Regenerated.
1002
1003 2018-07-24  Alan Modra  <amodra@gmail.com>
1004
1005         PR 23430
1006         * or1k-desc.h: Regenerate.
1007
1008 2018-07-24  Jan Beulich  <jbeulich@suse.com>
1009
1010         * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1011         vcvtusi2ss, and vcvtusi2sd.
1012         * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1013         Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1014         * i386-tbl.h: Re-generate.
1015
1016 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1017
1018         * arc-opc.c (extract_w6): Fix extending the sign.
1019
1020 2018-07-23  Claudiu Zissulescu <claziss@synopsys.com>
1021
1022         * arc-tbl.h (vewt): Allow it for ARC EM family.
1023
1024 2018-07-23  Alan Modra  <amodra@gmail.com>
1025
1026         PR 23419
1027         * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1028         opcode variants for mtspr/mfspr encodings.
1029
1030 2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1031             Maciej W. Rozycki  <macro@mips.com>
1032
1033         * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1034         loongson3a descriptors.
1035         (parse_mips_ase_option): Handle -M loongson-mmi option.
1036         (print_mips_disassembler_options): Document -M loongson-mmi.
1037         * mips-opc.c (LMMI): New macro.
1038         (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1039         instructions.
1040
1041 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1042
1043         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1044         vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1045         IgnoreSize and [XYZ]MMword where applicable.
1046         * i386-tbl.h: Re-generate.
1047
1048 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1049
1050         * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1051         (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1052         (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1053         (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1054         * i386-tbl.h: Re-generate.
1055
1056 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1057
1058         * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1059         AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1060         VPCLMULQDQ templates into their respective AVX512VL counterparts
1061         where possible, using Disp8ShiftVL and CheckRegSize instead of
1062         Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1063         * i386-tbl.h: Re-generate.
1064
1065 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1066
1067         * i386-opc.tbl: Fold AVX512DQ templates into their respective
1068         AVX512VL counterparts where possible, using Disp8ShiftVL and
1069         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1070         IgnoreSize) as appropriate.
1071         * i386-tbl.h: Re-generate.
1072
1073 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1074
1075         * i386-opc.tbl: Fold AVX512BW templates into their respective
1076         AVX512VL counterparts where possible, using Disp8ShiftVL and
1077         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1078         IgnoreSize) as appropriate.
1079         * i386-tbl.h: Re-generate.
1080
1081 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1082
1083         * i386-opc.tbl: Fold AVX512CD templates into their respective
1084         AVX512VL counterparts where possible, using Disp8ShiftVL and
1085         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1086         IgnoreSize) as appropriate.
1087         * i386-tbl.h: Re-generate.
1088
1089 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1090
1091         * i386-opc.h (DISP8_SHIFT_VL): New.
1092         * i386-opc.tbl (Disp8ShiftVL):  Define.
1093         (various): Fold AVX512VL templates into their respective
1094         AVX512F counterparts where possible, using Disp8ShiftVL and
1095         CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1096         IgnoreSize) as appropriate.
1097         * i386-tbl.h: Re-generate.
1098
1099 2018-07-19  Jan Beulich  <jbeulich@suse.com>
1100
1101         * Makefile.am: Change dependencies and rule for
1102         $(srcdir)/i386-init.h.
1103         * Makefile.in: Re-generate.
1104         * i386-gen.c (process_i386_opcodes): New local variable
1105         "marker". Drop opening of input file. Recognize marker and line
1106         number directives.
1107         * i386-opc.tbl (OPCODE_I386_H): Define.
1108         (i386-opc.h): Include it.
1109         (None): Undefine.
1110
1111 2018-07-18  H.J. Lu  <hongjiu.lu@intel.com>
1112
1113         PR gas/23418
1114         * i386-opc.h (Byte): Update comments.
1115         (Word): Likewise.
1116         (Dword): Likewise.
1117         (Fword): Likewise.
1118         (Qword): Likewise.
1119         (Tbyte): Likewise.
1120         (Xmmword): Likewise.
1121         (Ymmword): Likewise.
1122         (Zmmword): Likewise.
1123         * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1124         vcvttps2uqq.
1125         * i386-tbl.h: Regenerated.
1126
1127 2018-07-12  Sudakshina Das  <sudi.das@arm.com>
1128
1129         * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1130         ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1131         * aarch64-asm-2.c: Regenerate.
1132         * aarch64-dis-2.c: Regenerate.
1133         * aarch64-opc-2.c: Regenerate.
1134
1135 2018-07-12  Tamar Christina  <tamar.christina@arm.com>
1136
1137         PR binutils/23192
1138         * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1139         mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1140         umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1141         sqdmulh, sqrdmulh): Use Em16.
1142
1143 2018-07-11  Sudakshina Das  <sudi.das@arm.com>
1144
1145         * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1146         csdb together with them.
1147         (thumb32_opcodes): Likewise.
1148
1149 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1150
1151         * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1152         requiring 32-bit registers as operands 2 and 3. Improve
1153         comments.
1154         (mwait, mwaitx): Fold templates. Improve comments.
1155         OPERAND_TYPE_INOUTPORTREG.
1156         * i386-tbl.h: Re-generate.
1157
1158 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1159
1160         * i386-gen.c (operand_type_init): Remove
1161         OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1162         OPERAND_TYPE_INOUTPORTREG.
1163         * i386-init.h: Re-generate.
1164
1165 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1166
1167         * i386-opc.tbl (wrssd, wrussd): Add Dword.
1168         (wrssq, wrussq): Add Qword.
1169         * i386-tbl.h: Re-generate.
1170
1171 2018-07-11  Jan Beulich  <jbeulich@suse.com>
1172
1173         * i386-opc.h: Rename OTMax to OTNum.
1174         (OTNumOfUints): Adjust calculation.
1175         (OTUnused): Directly alias to OTNum.
1176
1177 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
1178
1179         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1180         `reg_xys'.
1181         (lea_reg_xys): Likewise.
1182         (print_insn_loop_primitive): Rename `reg' local variable to
1183         `reg_dxy'.
1184
1185 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1186
1187         PR binutils/23242
1188         * aarch64-tbl.h (ldarh): Fix disassembly mask.
1189
1190 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
1191
1192         PR binutils/23369
1193         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1194         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1195
1196 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
1197
1198         PR tdep/8282
1199         * mips-dis.c (mips_option_arg_t): New enumeration.
1200         (mips_options): New variable.
1201         (disassembler_options_mips): New function.
1202         (print_mips_disassembler_options): Reimplement in terms of
1203         `disassembler_options_mips'.
1204         * arm-dis.c (disassembler_options_arm): Adapt to using the
1205         `disasm_options_and_args_t' structure.
1206         * ppc-dis.c (disassembler_options_powerpc): Likewise.
1207         * s390-dis.c (disassembler_options_s390): Likewise.
1208
1209 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1210
1211         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1212         expected result.
1213         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1214         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1215         * testsuite/ld-arm/tls-longplt.d: Likewise.
1216
1217 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
1218
1219         PR binutils/23192
1220         * aarch64-asm-2.c: Regenerate.
1221         * aarch64-dis-2.c: Likewise.
1222         * aarch64-opc-2.c: Likewise.
1223         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1224         * aarch64-opc.c (operand_general_constraint_met_p,
1225         aarch64_print_operand): Likewise.
1226         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1227         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1228         fmlal2, fmlsl2.
1229         (AARCH64_OPERANDS): Add Em2.
1230
1231 2018-06-26  Nick Clifton  <nickc@redhat.com>
1232
1233         * po/uk.po: Updated Ukranian translation.
1234         * po/de.po: Updated German translation.
1235         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1236
1237 2018-06-26  Nick Clifton  <nickc@redhat.com>
1238
1239         * nfp-dis.c: Fix spelling mistake.
1240
1241 2018-06-24  Nick Clifton  <nickc@redhat.com>
1242
1243         * configure: Regenerate.
1244         * po/opcodes.pot: Regenerate.
1245
1246 2018-06-24  Nick Clifton  <nickc@redhat.com>
1247
1248         2.31 branch created.
1249
1250 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
1251
1252         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1253         * aarch64-asm-2.c: Regenerate.
1254         * aarch64-dis-2.c: Likewise.
1255
1256 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
1257
1258         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1259         `-M ginv' option description.
1260
1261 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
1262
1263         PR gas/23305
1264         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1265         la and lla.
1266
1267 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
1268
1269         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1270         * configure.ac: Remove AC_PREREQ.
1271         * Makefile.in: Re-generate.
1272         * aclocal.m4: Re-generate.
1273         * configure: Re-generate.
1274
1275 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1276
1277         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1278         mips64r6 descriptors.
1279         (parse_mips_ase_option): Handle -Mginv option.
1280         (print_mips_disassembler_options): Document -Mginv.
1281         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1282         (GINV): New macro.
1283         (mips_opcodes): Define ginvi and ginvt.
1284
1285 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
1286             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
1287
1288         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1289         * mips-opc.c (CRC, CRC64): New macros.
1290         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1291         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
1292         crc32cd for CRC64.
1293
1294 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
1295
1296         PR 20319
1297         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1298         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1299
1300 2018-06-06  Alan Modra  <amodra@gmail.com>
1301
1302         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1303         setjmp.  Move init for some other vars later too.
1304
1305 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
1306
1307         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1308         (dis_private): Add new fields for property section tracking.
1309         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1310         (xtensa_instruction_fits): New functions.
1311         (fetch_data): Bump minimal fetch size to 4.
1312         (print_insn_xtensa): Make struct dis_private static.
1313         Load and prepare property table on section change.
1314         Don't disassemble literals. Don't disassemble instructions that
1315         cross property table boundaries.
1316
1317 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
1318
1319         * configure: Regenerated.
1320
1321 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1322
1323         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1324         * i386-tbl.h: Re-generate.
1325
1326 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1327
1328         * i386-opc.tbl (sldt, str): Add NoRex64.
1329         * i386-tbl.h: Re-generate.
1330
1331 2018-06-01  Jan Beulich  <jbeulich@suse.com>
1332
1333         * i386-opc.tbl (invpcid): Add Oword.
1334         * i386-tbl.h: Re-generate.
1335
1336 2018-06-01  Alan Modra  <amodra@gmail.com>
1337
1338         * sysdep.h (_bfd_error_handler): Don't declare.
1339         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
1340         * rl78-decode.opc: Likewise.
1341         * msp430-decode.c: Regenerate.
1342         * rl78-decode.c: Regenerate.
1343
1344 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
1345
1346         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1347         * i386-init.h : Regenerated.
1348
1349 2018-05-25  Alan Modra  <amodra@gmail.com>
1350
1351         * Makefile.in: Regenerate.
1352         * po/POTFILES.in: Regenerate.
1353
1354 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
1355
1356         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1357         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1358         (insert_bab, extract_bab, insert_btab, extract_btab,
1359         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1360         (BAT, BBA VBA RBS XB6S): Delete macros.
1361         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1362         (BB, BD, RBX, XC6): Update for new macros.
1363         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1364         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1365         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1366         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1367
1368 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
1369
1370         * Makefile.am: Add support for s12z architecture.
1371         * configure.ac: Likewise.
1372         * disassemble.c: Likewise.
1373         * disassemble.h: Likewise.
1374         * Makefile.in: Regenerate.
1375         * configure: Regenerate.
1376         * s12z-dis.c: New file.
1377         * s12z.h: New file.
1378
1379 2018-05-18  Alan Modra  <amodra@gmail.com>
1380
1381         * nfp-dis.c: Don't #include libbfd.h.
1382         (init_nfp3200_priv): Use bfd_get_section_contents.
1383         (nit_nfp6000_mecsr_sec): Likewise.
1384
1385 2018-05-17  Nick Clifton  <nickc@redhat.com>
1386
1387         * po/zh_CN.po: Updated simplified Chinese translation.
1388
1389 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
1390
1391         PR binutils/23109
1392         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1393         * aarch64-dis-2.c: Regenerate.
1394
1395 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1396
1397         PR binutils/21446
1398         * aarch64-asm.c (opintl.h): Include.
1399         (aarch64_ins_sysreg): Enforce read/write constraints.
1400         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1401         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1402         (F_REG_READ, F_REG_WRITE): New.
1403         * aarch64-opc.c (aarch64_print_operand): Generate notes for
1404         AARCH64_OPND_SYSREG.
1405         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1406         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1407         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1408         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1409         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1410         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1411         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1412         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1413         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1414         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1415         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1416         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1417         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1418         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1419         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1420         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1421         msr (F_SYS_WRITE), mrs (F_SYS_READ).
1422
1423 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1424
1425         PR binutils/21446
1426         * aarch64-dis.c (no_notes: New.
1427         (parse_aarch64_dis_option): Support notes.
1428         (aarch64_decode_insn, print_operands): Likewise.
1429         (print_aarch64_disassembler_options): Document notes.
1430         * aarch64-opc.c (aarch64_print_operand): Support notes.
1431
1432 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
1433
1434         PR binutils/21446
1435         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1436         and take error struct.
1437         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1438         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1439         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1440         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1441         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1442         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1443         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1444         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1445         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1446         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1447         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1448         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1449         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1450         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1451         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1452         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1453         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1454         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1455         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1456         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1457         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1458         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1459         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1460         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1461         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1462         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1463         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1464         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1465         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1466         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1467         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1468         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1469         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1470         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1471         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1472         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1473         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1474         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1475         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1476         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1477         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1478         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1479         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1480         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1481         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1482         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1483         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1484         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1485         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1486         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1487         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1488         (determine_disassembling_preference, aarch64_decode_insn,
1489         print_insn_aarch64_word, print_insn_data): Take errors struct.
1490         (print_insn_aarch64): Use errors.
1491         * aarch64-asm-2.c: Regenerate.
1492         * aarch64-dis-2.c: Regenerate.
1493         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1494         boolean in aarch64_insert_operan.
1495         (print_operand_extractor): Likewise.
1496         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1497
1498 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
1499
1500         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1501
1502 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
1503
1504         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1505
1506 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
1507
1508         * cr16-opc.c (cr16_instruction): Comment typo fix.
1509         * hppa-dis.c (print_insn_hppa): Likewise.
1510
1511 2018-05-08  Jim Wilson  <jimw@sifive.com>
1512
1513         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1514         (match_c_slli64, match_srxi_as_c_srxi): New.
1515         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1516         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1517         <c.slli, c.srli, c.srai>: Use match_s_slli.
1518         <c.slli64, c.srli64, c.srai64>: New.
1519
1520 2018-05-08  Alan Modra  <amodra@gmail.com>
1521
1522         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1523         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1524         partition opcode space for index lookup.
1525
1526 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1527
1528         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1529         <insn_length>: ...with this.  Update usage.
1530         Remove duplicate call to *info->memory_error_func.
1531
1532 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1533             H.J. Lu  <hongjiu.lu@intel.com>
1534
1535         * i386-dis.c (Gva): New.
1536         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1537         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1538         (prefix_table): New instructions (see prefix above).
1539         (mod_table): New instructions (see prefix above).
1540         (OP_G): Handle va_mode.
1541         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1542         CPU_MOVDIR64B_FLAGS.
1543         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1544         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1545         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1546         * i386-opc.tbl: Add movidir{i,64b}.
1547         * i386-init.h: Regenerated.
1548         * i386-tbl.h: Likewise.
1549
1550 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
1551
1552         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1553         AddrPrefixOpReg.
1554         * i386-opc.h (AddrPrefixOp0): Renamed to ...
1555         (AddrPrefixOpReg): This.
1556         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1557         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1558
1559 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
1560
1561         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1562         (vle_num_opcodes): Likewise.
1563         (spe2_num_opcodes): Likewise.
1564         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1565         initialization loop.
1566         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1567         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
1568         only once.
1569
1570 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
1571
1572         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1573
1574 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
1575
1576         Makefile.am: Added nfp-dis.c.
1577         configure.ac: Added bfd_nfp_arch.
1578         disassemble.h: Added print_insn_nfp prototype.
1579         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1580         nfp-dis.c: New, for NFP support.
1581         po/POTFILES.in: Added nfp-dis.c to the list.
1582         Makefile.in: Regenerate.
1583         configure: Regenerate.
1584
1585 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1586
1587         * i386-opc.tbl: Fold various non-memory operand AVX512VL
1588         templates into their base ones.
1589         * i386-tlb.h: Re-generate.
1590
1591 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1592
1593         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1594         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1595         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1596         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1597         * i386-init.h: Re-generate.
1598
1599 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1600
1601         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1602         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1603         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1604         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1605         comment.
1606         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1607         and CpuRegMask.
1608         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1609         CpuRegMask: Delete.
1610         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1611         cpuregzmm, and cpuregmask.
1612         * i386-init.h: Re-generate.
1613         * i386-tbl.h: Re-generate.
1614
1615 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1616
1617         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1618         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1619         * i386-init.h: Re-generate.
1620
1621 2018-04-26  Jan Beulich  <jbeulich@suse.com>
1622
1623         * i386-gen.c (VexImmExt): Delete.
1624         * i386-opc.h (VexImmExt, veximmext): Delete.
1625         * i386-opc.tbl: Drop all VexImmExt uses.
1626         * i386-tlb.h: Re-generate.
1627
1628 2018-04-25  Jan Beulich  <jbeulich@suse.com>
1629
1630         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1631         register-only forms.
1632         * i386-tlb.h: Re-generate.
1633
1634 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
1635
1636         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1637
1638 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1639
1640         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1641         PREFIX_0F1C.
1642         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1643         (cpu_flags): Add CpuCLDEMOTE.
1644         * i386-init.h: Regenerate.
1645         * i386-opc.h (enum): Add CpuCLDEMOTE,
1646         (i386_cpu_flags): Add cpucldemote.
1647         * i386-opc.tbl: Add cldemote.
1648         * i386-tbl.h: Regenerate.
1649
1650 2018-04-16  Alan Modra  <amodra@gmail.com>
1651
1652         * Makefile.am: Remove sh5 and sh64 support.
1653         * configure.ac: Likewise.
1654         * disassemble.c: Likewise.
1655         * disassemble.h: Likewise.
1656         * sh-dis.c: Likewise.
1657         * sh64-dis.c: Delete.
1658         * sh64-opc.c: Delete.
1659         * sh64-opc.h: Delete.
1660         * Makefile.in: Regenerate.
1661         * configure: Regenerate.
1662         * po/POTFILES.in: Regenerate.
1663
1664 2018-04-16  Alan Modra  <amodra@gmail.com>
1665
1666         * Makefile.am: Remove w65 support.
1667         * configure.ac: Likewise.
1668         * disassemble.c: Likewise.
1669         * disassemble.h: Likewise.
1670         * w65-dis.c: Delete.
1671         * w65-opc.h: Delete.
1672         * Makefile.in: Regenerate.
1673         * configure: Regenerate.
1674         * po/POTFILES.in: Regenerate.
1675
1676 2018-04-16  Alan Modra  <amodra@gmail.com>
1677
1678         * configure.ac: Remove we32k support.
1679         * configure: Regenerate.
1680
1681 2018-04-16  Alan Modra  <amodra@gmail.com>
1682
1683         * Makefile.am: Remove m88k support.
1684         * configure.ac: Likewise.
1685         * disassemble.c: Likewise.
1686         * disassemble.h: Likewise.
1687         * m88k-dis.c: Delete.
1688         * Makefile.in: Regenerate.
1689         * configure: Regenerate.
1690         * po/POTFILES.in: Regenerate.
1691
1692 2018-04-16  Alan Modra  <amodra@gmail.com>
1693
1694         * Makefile.am: Remove i370 support.
1695         * configure.ac: Likewise.
1696         * disassemble.c: Likewise.
1697         * disassemble.h: Likewise.
1698         * i370-dis.c: Delete.
1699         * i370-opc.c: Delete.
1700         * Makefile.in: Regenerate.
1701         * configure: Regenerate.
1702         * po/POTFILES.in: Regenerate.
1703
1704 2018-04-16  Alan Modra  <amodra@gmail.com>
1705
1706         * Makefile.am: Remove h8500 support.
1707         * configure.ac: Likewise.
1708         * disassemble.c: Likewise.
1709         * disassemble.h: Likewise.
1710         * h8500-dis.c: Delete.
1711         * h8500-opc.h: Delete.
1712         * Makefile.in: Regenerate.
1713         * configure: Regenerate.
1714         * po/POTFILES.in: Regenerate.
1715
1716 2018-04-16  Alan Modra  <amodra@gmail.com>
1717
1718         * configure.ac: Remove tahoe support.
1719         * configure: Regenerate.
1720
1721 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1722
1723         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1724         umwait.
1725         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1726         64-bit mode.
1727         * i386-tbl.h: Regenerated.
1728
1729 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1730
1731         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1732         PREFIX_MOD_1_0FAE_REG_6.
1733         (va_mode): New.
1734         (OP_E_register): Use va_mode.
1735         * i386-dis-evex.h (prefix_table):
1736         New instructions (see prefixes above).
1737         * i386-gen.c (cpu_flag_init): Add WAITPKG.
1738         (cpu_flags): Likewise.
1739         * i386-opc.h (enum): Likewise.
1740         (i386_cpu_flags): Likewise.
1741         * i386-opc.tbl: Add umonitor, umwait, tpause.
1742         * i386-init.h: Regenerate.
1743         * i386-tbl.h: Likewise.
1744
1745 2018-04-11  Alan Modra  <amodra@gmail.com>
1746
1747         * opcodes/i860-dis.c: Delete.
1748         * opcodes/i960-dis.c: Delete.
1749         * Makefile.am: Remove i860 and i960 support.
1750         * configure.ac: Likewise.
1751         * disassemble.c: Likewise.
1752         * disassemble.h: Likewise.
1753         * Makefile.in: Regenerate.
1754         * configure: Regenerate.
1755         * po/POTFILES.in: Regenerate.
1756
1757 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
1758
1759         PR binutils/23025
1760         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1761         to 0.
1762         (print_insn): Clear vex instead of vex.evex.
1763
1764 2018-04-04  Nick Clifton  <nickc@redhat.com>
1765
1766         * po/es.po: Updated Spanish translation.
1767
1768 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1769
1770         * i386-gen.c (opcode_modifiers): Delete VecESize.
1771         * i386-opc.h (VecESize): Delete.
1772         (struct i386_opcode_modifier): Delete vecesize.
1773         * i386-opc.tbl: Drop VecESize.
1774         * i386-tlb.h: Re-generate.
1775
1776 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1777
1778         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1779         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1780         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1781         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1782         * i386-tlb.h: Re-generate.
1783
1784 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1785
1786         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1787         Fold AVX512 forms
1788         * i386-tlb.h: Re-generate.
1789
1790 2018-03-28  Jan Beulich  <jbeulich@suse.com>
1791
1792         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1793         (vex_len_table): Drop Y for vcvt*2si.
1794         (putop): Replace plain 'Y' handling by abort().
1795
1796 2018-03-28  Nick Clifton  <nickc@redhat.com>
1797
1798         PR 22988
1799         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1800         instructions with only a base address register.
1801         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1802         handle AARHC64_OPND_SVE_ADDR_R.
1803         (aarch64_print_operand): Likewise.
1804         * aarch64-asm-2.c: Regenerate.
1805         * aarch64_dis-2.c: Regenerate.
1806         * aarch64-opc-2.c: Regenerate.
1807
1808 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1809
1810         * i386-opc.tbl: Drop VecESize from register only insn forms and
1811         memory forms not allowing broadcast.
1812         * i386-tlb.h: Re-generate.
1813
1814 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1815
1816         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1817         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1818         sha256*): Drop Disp<N>.
1819
1820 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1821
1822         * i386-dis.c (EbndS, bnd_swap_mode): New.
1823         (prefix_table): Use EbndS.
1824         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1825         * i386-opc.tbl (bndmov): Move misplaced Load.
1826         * i386-tlb.h: Re-generate.
1827
1828 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1829
1830         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1831         templates allowing memory operands and folded ones for register
1832         only flavors.
1833         * i386-tlb.h: Re-generate.
1834
1835 2018-03-22  Jan Beulich  <jbeulich@suse.com>
1836
1837         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1838         256-bit templates. Drop redundant leftover Disp<N>.
1839         * i386-tlb.h: Re-generate.
1840
1841 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
1842
1843         * riscv-opc.c (riscv_insn_types): New.
1844
1845 2018-03-13  Nick Clifton  <nickc@redhat.com>
1846
1847         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1848
1849 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1850
1851         * i386-opc.tbl: Add Optimize to clr.
1852         * i386-tbl.h: Regenerated.
1853
1854 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
1855
1856         * i386-gen.c (opcode_modifiers): Remove OldGcc.
1857         * i386-opc.h (OldGcc): Removed.
1858         (i386_opcode_modifier): Remove oldgcc.
1859         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1860         instructions for old (<= 2.8.1) versions of gcc.
1861         * i386-tbl.h: Regenerated.
1862
1863 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1864
1865         * i386-opc.h (EVEXDYN): New.
1866         * i386-opc.tbl: Fold various AVX512VL templates.
1867         * i386-tlb.h: Re-generate.
1868
1869 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1870
1871         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1872         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1873         vpexpandd, vpexpandq): Fold AFX512VF templates.
1874         * i386-tlb.h: Re-generate.
1875
1876 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1877
1878         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1879         Fold 128- and 256-bit VEX-encoded templates.
1880         * i386-tlb.h: Re-generate.
1881
1882 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1883
1884         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1885         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1886         vpexpandd, vpexpandq): Fold AVX512F templates.
1887         * i386-tlb.h: Re-generate.
1888
1889 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1890
1891         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1892         64-bit templates. Drop Disp<N>.
1893         * i386-tlb.h: Re-generate.
1894
1895 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1896
1897         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1898         and 256-bit templates.
1899         * i386-tlb.h: Re-generate.
1900
1901 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1902
1903         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1904         * i386-tlb.h: Re-generate.
1905
1906 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1907
1908         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1909         Drop NoAVX.
1910         * i386-tlb.h: Re-generate.
1911
1912 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1913
1914         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1915         * i386-tlb.h: Re-generate.
1916
1917 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1918
1919         * i386-gen.c (opcode_modifiers): Delete FloatD.
1920         * i386-opc.h (FloatD): Delete.
1921         (struct i386_opcode_modifier): Delete floatd.
1922         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1923         FloatD by D.
1924         * i386-tlb.h: Re-generate.
1925
1926 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1927
1928         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1929
1930 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1931
1932         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1933         * i386-tlb.h: Re-generate.
1934
1935 2018-03-08  Jan Beulich  <jbeulich@suse.com>
1936
1937         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1938         forms.
1939         * i386-tlb.h: Re-generate.
1940
1941 2018-03-07  Alan Modra  <amodra@gmail.com>
1942
1943         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1944         bfd_arch_rs6000.
1945         * disassemble.h (print_insn_rs6000): Delete.
1946         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1947         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1948         (print_insn_rs6000): Delete.
1949
1950 2018-03-03  Alan Modra  <amodra@gmail.com>
1951
1952         * sysdep.h (opcodes_error_handler): Define.
1953         (_bfd_error_handler): Declare.
1954         * Makefile.am: Remove stray #.
1955         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
1956         EDIT" comment.
1957         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1958         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1959         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1960         opcodes_error_handler to print errors.  Standardize error messages.
1961         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1962         and include opintl.h.
1963         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1964         * i386-gen.c: Standardize error messages.
1965         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1966         * Makefile.in: Regenerate.
1967         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1968         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1969         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1970         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1971         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1972         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1973         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1974         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1975         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1976         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1977         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1978         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1979         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1980
1981 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
1982
1983         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1984         vpsub[bwdq] instructions.
1985         * i386-tbl.h: Regenerated.
1986
1987 2018-03-01  Alan Modra  <amodra@gmail.com>
1988
1989         * configure.ac (ALL_LINGUAS): Sort.
1990         * configure: Regenerate.
1991
1992 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1993
1994         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1995         macro by assignements.
1996
1997 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
1998
1999         PR gas/22871
2000         * i386-gen.c (opcode_modifiers): Add Optimize.
2001         * i386-opc.h (Optimize): New enum.
2002         (i386_opcode_modifier): Add optimize.
2003         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
2004         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2005         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2006         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2007         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2008         vpxord and vpxorq.
2009         * i386-tbl.h: Regenerated.
2010
2011 2018-02-26  Alan Modra  <amodra@gmail.com>
2012
2013         * crx-dis.c (getregliststring): Allocate a large enough buffer
2014         to silence false positive gcc8 warning.
2015
2016 2018-02-22  Shea Levy <shea@shealevy.com>
2017
2018         * disassemble.c (ARCH_riscv): Define if ARCH_all.
2019
2020 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
2021
2022         * i386-opc.tbl: Add {rex},
2023         * i386-tbl.h: Regenerated.
2024
2025 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
2026
2027         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2028         (mips16_opcodes): Replace `M' with `m' for "restore".
2029
2030 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2031
2032         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2033
2034 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
2035
2036         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2037         variable to `function_index'.
2038
2039 2018-02-13  Nick Clifton  <nickc@redhat.com>
2040
2041         PR 22823
2042         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2043         about truncation of printing.
2044
2045 2018-02-12  Henry Wong <henry@stuffedcow.net>
2046
2047         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2048
2049 2018-02-05  Nick Clifton  <nickc@redhat.com>
2050
2051         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2052
2053 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2054
2055         * i386-dis.c (enum): Add pconfig.
2056         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2057         (cpu_flags): Add CpuPCONFIG.
2058         * i386-opc.h (enum): Add CpuPCONFIG.
2059         (i386_cpu_flags): Add cpupconfig.
2060         * i386-opc.tbl: Add PCONFIG instruction.
2061         * i386-init.h: Regenerate.
2062         * i386-tbl.h: Likewise.
2063
2064 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2065
2066         * i386-dis.c (enum): Add PREFIX_0F09.
2067         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2068         (cpu_flags): Add CpuWBNOINVD.
2069         * i386-opc.h (enum): Add CpuWBNOINVD.
2070         (i386_cpu_flags): Add cpuwbnoinvd.
2071         * i386-opc.tbl: Add WBNOINVD instruction.
2072         * i386-init.h: Regenerate.
2073         * i386-tbl.h: Likewise.
2074
2075 2018-01-17  Jim Wilson  <jimw@sifive.com>
2076
2077         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2078
2079 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2080
2081         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2082         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2083         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2084         (cpu_flags): Add CpuIBT, CpuSHSTK.
2085         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2086         (i386_cpu_flags): Add cpuibt, cpushstk.
2087         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2088         * i386-init.h: Regenerate.
2089         * i386-tbl.h: Likewise.
2090
2091 2018-01-16  Nick Clifton  <nickc@redhat.com>
2092
2093         * po/pt_BR.po: Updated Brazilian Portugese translation.
2094         * po/de.po: Updated German translation.
2095
2096 2018-01-15  Jim Wilson  <jimw@sifive.com>
2097
2098         * riscv-opc.c (match_c_nop): New.
2099         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2100
2101 2018-01-15  Nick Clifton  <nickc@redhat.com>
2102
2103         * po/uk.po: Updated Ukranian translation.
2104
2105 2018-01-13  Nick Clifton  <nickc@redhat.com>
2106
2107         * po/opcodes.pot: Regenerated.
2108
2109 2018-01-13  Nick Clifton  <nickc@redhat.com>
2110
2111         * configure: Regenerate.
2112
2113 2018-01-13  Nick Clifton  <nickc@redhat.com>
2114
2115         2.30 branch created.
2116
2117 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
2118
2119         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2120         * i386-tbl.h: Regenerate.
2121
2122 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2123
2124         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2125         * i386-tbl.h: Re-generate.
2126
2127 2018-01-10  Jan Beulich  <jbeulich@suse.com>
2128
2129         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2130         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2131         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2132         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2133         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2134         Disp8MemShift of AVX512VL forms.
2135         * i386-tbl.h: Re-generate.
2136
2137 2018-01-09  Jim Wilson  <jimw@sifive.com>
2138
2139         * riscv-dis.c (maybe_print_address): If base_reg is zero,
2140         then the hi_addr value is zero.
2141
2142 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2143
2144         * arm-dis.c (arm_opcodes): Add csdb.
2145         (thumb32_opcodes): Add csdb.
2146
2147 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
2148
2149         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2150         * aarch64-asm-2.c: Regenerate.
2151         * aarch64-dis-2.c: Regenerate.
2152         * aarch64-opc-2.c: Regenerate.
2153
2154 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
2155
2156         PR gas/22681
2157         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2158         Remove AVX512 vmovd with 64-bit operands.
2159         * i386-tbl.h: Regenerated.
2160
2161 2018-01-05  Jim Wilson  <jimw@sifive.com>
2162
2163         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2164         jalr.
2165
2166 2018-01-03  Alan Modra  <amodra@gmail.com>
2167
2168         Update year range in copyright notice of all files.
2169
2170 2018-01-02  Jan Beulich  <jbeulich@suse.com>
2171
2172         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2173         and OPERAND_TYPE_REGZMM entries.
2174
2175 For older changes see ChangeLog-2017
2176 \f
2177 Copyright (C) 2018 Free Software Foundation, Inc.
2178
2179 Copying and distribution of this file, with or without modification,
2180 are permitted in any medium without royalty provided the copyright
2181 notice and this notice are preserved.
2182
2183 Local Variables:
2184 mode: change-log
2185 left-margin: 8
2186 fill-column: 74
2187 version-control: never
2188 End: