opcodes/ChangeLog

   1 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
   2
   3         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
   4         * frv-asm.c: Rebuilt.
   5         * frv-desc.c: Rebuilt.
   6         * frv-desc.h: Rebuilt.
   7         * frv-dis.c: Rebuilt.
   8         * frv-ibld.c: Rebuilt.
   9         * frv-opc.c: Rebuilt.
  10         * frv-opc.h: Rebuilt.
  11
  12 2005-01-24  Andrew Cagney  <cagney@gnu.org>
  13
  14         * configure: Regenerate, ../gettext.m4 was updated.
  15
  16 2005-01-21  Fred Fish  <fnf@specifixinc.com>
  17
  18         * mips-opc.c:  Change INSN_ALIAS to INSN2_ALIAS.
  19         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
  20         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
  21         * mips-dis.c: Ditto.
  22
  23 2005-01-20  Alan Modra  <amodra@bigpond.net.au>
  24
  25         * ppc-opc.c (powerpc_opcodes): Add optional 'l' arg to tlbiel.
  26
  27 2005-01-19  Fred Fish  <fnf@specifixinc.com>
  28
  29         * mips-dis.c (no_aliases): New disassembly option flag.
  30         (set_default_mips_dis_options): Init no_aliases to zero.
  31         (parse_mips_dis_option): Handle no-aliases option.
  32         (print_insn_mips): Ignore table entries that are aliases
  33         if no_aliases is set.
  34         (print_insn_mips16): Ditto.
  35         * mips-opc.c (mips_builtin_opcodes): Add initializer column for
  36         new pinfo2 member and add INSN_ALIAS initializers as needed.  Also
  37         move WR_MACC and RD_MACC initializers from pinfo to pinfo2.
  38         * mips16-opc.c (mips16_opcodes): Ditto.
  39
  40 2005-01-17  Andrew Stubbs  <andrew.stubbs@st.com>
  41
  42         * sh-opc.h (arch_sh2a_or_sh3e,arch_sh2a_or_sh4): Correct definition.
  43         (inheritance diagram): Add missing edge.
  44         (arch_sh1_up): Rename arch_sh_up to match external name to make life
  45         easier for the testsuite.
  46         (arch_sh4_nofp_up): Likewise, rename arch_sh4_nofpu_up.
  47         (arch_sh4a_nofp_up): Likewise, rename arch_sh4a_nofpu_up.
  48         (arch_sh2a_nofpu_or_sh4_nommu_nofpu_up): Add missing
  49         arch_sh2a_or_sh4_up child.
  50         (sh_table): Do renaming as above.
  51         Correct comment for ldc.l for gas testsuite to read.
  52         Remove rogue mul.l from sh1 (duplicate of the one for sh2).
  53         Correct comments for movy.w and movy.l for gas testsuite to read.
  54         Correct comments for fmov.d and fmov.s for gas testsuite to read.
  55
  56 2005-01-12  H.J. Lu  <hongjiu.lu@intel.com>
  57
  58         * i386-dis.c (OP_E): Don't ignore scale in SIB for 64 bit mode.
  59
  60 2005-01-12  H.J. Lu  <hongjiu.lu@intel.com>
  61
  62         * i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB.
  63
  64 2005-01-10  Andreas Schwab  <schwab@suse.de>
  65
  66         * disassemble.c (disassemble_init_for_target) <case
  67         bfd_arch_ia64>: Set skip_zeroes to 16.
  68         <case bfd_arch_tic4x>: Set skip_zeroes to 32.
  69
  70 2004-12-23  Tomer Levi  <Tomer.Levi@nsc.com>
  71
  72         * crx-opc.c: Mark 'bcop' instruction as RELAXABLE.
  73
  74 2004-12-14  Svein E. Seldal  <Svein.Seldal@solidas.com>
  75
  76         * avr-dis.c: Prettyprint. Added printing of symbol names in all
  77         memory references. Convert avr_operand() to C90 formatting.
  78
  79 2004-12-05  Tomer Levi  <Tomer.Levi@nsc.com>
  80
  81         * crx-dis.c (print_arg): Use 'info->print_address_func' for address printing.
  82
  83 2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
  84
  85         * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
  86         (no_op_insn): Initialize array with instructions that have no
  87         operands.
  88         * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
  89
  90 2004-11-29  Richard Earnshaw  <rearnsha@arm.com>
  91
  92         * arm-dis.c: Correct top-level comment.
  93
  94 2004-11-27  Richard Earnshaw  <rearnsha@arm.com>
  95
  96         * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
  97         architecuture defining the insn.
  98         (arm_opcodes, thumb_opcodes): Delete.  Move to ...
  99         * arm-dis.c (arm_opcodes, thumb_opcodes): Here.  Add architecutre
 100         field.
 101         Also include opcode/arm.h.
 102         * Makefile.am (arm-dis.lo): Update dependency list.
 103         * Makefile.in: Regenerate.
 104
 105 2004-11-22  Ravi Ramaseshan  <ravi.ramaseshan@codito.com>
 106
 107         * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
 108         reflect the change to the short immediate syntax.
 109
 110 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 111
 112         * or32-opc.c (debug): Warning fix.
 113         * po/POTFILES.in: Regenerate.
 114
 115         * maxq-dis.c: Formatting.
 116         (print_insn): Warning fix.
 117
 118 2004-11-17  Daniel Jacobowitz  <dan@codesourcery.com>
 119
 120         * arm-dis.c (WORD_ADDRESS): Define.
 121         (print_insn): Use it.  Correct big-endian end-of-section handling.
 122
 123 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 124             Vineet Sharma      <vineets@noida.hcltech.com>
 125
 126         * maxq-dis.c: New file.
 127         * disassemble.c (ARCH_maxq): Define.
 128         (disassembler): Add 'print_insn_maxq_little' for handling maxq
 129         instructions..
 130         * configure.in: Add case for bfd_maxq_arch.
 131         * configure: Regenerate.
 132         * Makefile.am: Add support for maxq-dis.c
 133         * Makefile.in: Regenerate.
 134         * aclocal.m4: Regenerate.
 135
 136 2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 137
 138         * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
 139         mode.
 140         * crx-dis.c: Likewise.
 141
 142 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 143
 144         Generally, handle CRISv32.
 145         * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
 146         (struct cris_disasm_data): New type.
 147         (format_reg, format_hex, cris_constraint, print_flags)
 148         (get_opcode_entry): Add struct cris_disasm_data * parameter.  All
 149         callers changed.
 150         (format_sup_reg, print_insn_crisv32_with_register_prefix)
 151         (print_insn_crisv32_without_register_prefix)
 152         (print_insn_crisv10_v32_with_register_prefix)
 153         (print_insn_crisv10_v32_without_register_prefix)
 154         (cris_parse_disassembler_options): New functions.
 155         (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
 156         parameter.  All callers changed.
 157         (get_opcode_entry): Call malloc, not xmalloc.  Return NULL on
 158         failure.
 159         (cris_constraint) <case 'Y', 'U'>: New cases.
 160         (bytes_to_skip): Handle 'Y' and 'N' as 's'.  Skip size is 4 bytes
 161         for constraint 'n'.
 162         (print_with_operands) <case 'Y'>: New case.
 163         (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
 164         <case 'N', 'Y', 'Q'>: New cases.
 165         (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
 166         (print_insn_cris_with_register_prefix)
 167         (print_insn_cris_without_register_prefix): Call
 168         cris_parse_disassembler_options.
 169         * cris-opc.c (cris_spec_regs): Mention that this table isn't used
 170         for CRISv32 and the size of immediate operands.  New v32-only
 171         entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
 172         spc.  Add v32-only 4-byte entries for p2, p3, p5 and p6.  Change
 173         ccr, ibr, irp to be v0..v10.  Change bar, dccr to be v8..v10.
 174         Change brp to be v3..v10.
 175         (cris_support_regs): New vector.
 176         (cris_opcodes): Update head comment.  New format characters '[',
 177         ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
 178         Add new opcodes for v32 and adjust existing opcodes to accommodate
 179         differences to earlier variants.
 180         (cris_cond15s): New vector.
 181
 182 2004-11-04 Jan Beulich <jbeulich@novell.com>
 183
 184         * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
 185         (indirEb): Remove.
 186         (Mp): Use f_mode rather than none at all.
 187         (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
 188         replaces what previously was x_mode; x_mode now means 128-bit SSE
 189         operands.
 190         (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
 191         mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
 192         pinsrw's second operand is Edqw.
 193         (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
 194         operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
 195         fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
 196         mode when an operand size override is present or always suffixing.
 197         More instructions will need to be added to this group.
 198         (putop): Handle new macro chars 'C' (short/long suffix selector),
 199         'I' (Intel mode override for following macro char), and 'J' (for
 200         adding the 'l' prefix to far branches in AT&T mode). When an
 201         alternative was specified in the template, honor macro character when
 202         specified for Intel mode.
 203         (OP_E): Handle new *_mode values. Correct pointer specifications for
 204         memory operands. Consolidate output of index register.
 205         (OP_G): Handle new *_mode values.
 206         (OP_I): Handle const_1_mode.
 207         (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
 208         respective opcode prefix bits have been consumed.
 209         (OP_EM, OP_EX): Provide some default handling for generating pointer
 210         specifications.
 211
 212 2004-10-28  Tomer Levi  <Tomer.Levi@nsc.com>
 213
 214         * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
 215         COP_INST macro.
 216
 217 2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 218
 219         * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
 220         (getregliststring): Support HI/LO and user registers.
 221         * crx-opc.c (crx_instruction): Update data structure according to the
 222         rearrangement done in CRX opcode header file.
 223         (crx_regtab):  Likewise.
 224         (crx_optab):  Likewise.
 225         (crx_instruction): Reorder load/stor instructions, remove unsupported
 226         formats.
 227         support new Co-Processor instruction 'cpi'.
 228
 229 2004-10-27  Nick Clifton  <nickc@redhat.com>
 230
 231         * opcodes/iq2000-asm.c: Regenerate.
 232         * opcodes/iq2000-desc.c: Regenerate.
 233         * opcodes/iq2000-desc.h: Regenerate.
 234         * opcodes/iq2000-dis.c: Regenerate.
 235         * opcodes/iq2000-ibld.c: Regenerate.
 236         * opcodes/iq2000-opc.c: Regenerate.
 237         * opcodes/iq2000-opc.h: Regenerate.
 238
 239 2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 240
 241         * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
 242         us4, us5 (respectively).
 243         Remove unsupported 'popa' instruction.
 244         Reverse operands order in store co-processor instructions.
 245
 246 2004-10-15  Alan Modra  <amodra@bigpond.net.au>
 247
 248         * Makefile.am: Run "make dep-am"
 249         * Makefile.in: Regenerate.
 250
 251 2004-10-12  Bob Wilson  <bob.wilson@acm.org>
 252
 253         * xtensa-dis.c: Use ISO C90 formatting.
 254
 255 2004-10-09  Alan Modra  <amodra@bigpond.net.au>
 256
 257         * ppc-opc.c: Revert 2004-09-09 change.
 258
 259 2004-10-07  Bob Wilson  <bob.wilson@acm.org>
 260
 261         * xtensa-dis.c (state_names): Delete.
 262         (fetch_data): Use xtensa_isa_maxlength.
 263         (print_xtensa_operand): Replace operand parameter with opcode/operand
 264         pair.  Remove print_sr_name parameter.  Use new xtensa-isa.h functions.
 265         (print_insn_xtensa): Use new xtensa-isa.h functions.  Handle multislot
 266         instruction bundles.  Use xmalloc instead of malloc.
 267
 268 2004-10-07  David Gibson  <david@gibson.dropbear.id.au>
 269
 270         * ppc-opc.c: Replace literal "0"s with NULLs in pointer
 271         initializers.
 272
 273 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 274
 275         * crx-opc.c (crx_instruction): Support Co-processor insns.
 276         * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
 277         (getregliststring): Change function to use the above enum.
 278         (print_arg): Handle CO-Processor insns.
 279         (crx_cinvs): Add 'b' option to invalidate the branch-target
 280         cache.
 281
 282 2004-10-06  Aldy Hernandez  <aldyh@redhat.com>
 283
 284         * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
 285         efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
 286         efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
 287         efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
 288         efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
 289
 290 2004-10-01  Bill Farmer  <Bill@the-farmers.freeserve.co.uk>
 291
 292         * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
 293         rather than add it.
 294
 295 2004-09-30  Paul Brook  <paul@codesourcery.com>
 296
 297         * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
 298         * arm-opc.h: Document %e.  Add ARMv6ZK instructions.
 299
 300 2004-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 301
 302         * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
 303         (CONFIG_STATUS_DEPENDENCIES): New.
 304         (Makefile): Removed.
 305         (config.status): Likewise.
 306         * Makefile.in: Regenerated.
 307
 308 2004-09-17  Alan Modra  <amodra@bigpond.net.au>
 309
 310         * Makefile.am: Run "make dep-am".
 311         * Makefile.in: Regenerate.
 312         * aclocal.m4: Regenerate.
 313         * configure: Regenerate.
 314         * po/POTFILES.in: Regenerate.
 315         * po/opcodes.pot: Regenerate.
 316
 317 2004-09-11  Andreas Schwab  <schwab@suse.de>
 318
 319         * configure: Rebuild.
 320
 321 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 322
 323         * ppc-opc.c (L): Make this field not optional.
 324
 325 2004-09-03  Tomer Levi  <Tomer.Levi@nsc.com>
 326
 327         * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
 328         Fix parameter to 'm[t|f]csr' insns.
 329
 330 2004-08-30  Nathanael Nerode  <neroden@gcc.gnu.org>
 331
 332         * configure.in: Autoupdate to autoconf 2.59.
 333         * aclocal.m4: Rebuild with aclocal 1.4p6.
 334         * configure: Rebuild with autoconf 2.59.
 335         * Makefile.in: Rebuild with automake 1.4p6 (picking up
 336         bfd changes for autoconf 2.59 on the way).
 337         * config.in: Rebuild with autoheader 2.59.
 338
 339 2004-08-27  Richard Sandiford  <rsandifo@redhat.com>
 340
 341         * frv-desc.[ch], frv-opc.[ch]: Regenerated.
 342
 343 2004-07-30  Michal Ludvig  <mludvig@suse.cz>
 344
 345         * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
 346         (GRPPADLCK2): New define.
 347         (twobyte_has_modrm): True for 0xA6.
 348         (grps): GRPPADLCK2 for opcode 0xA6.
 349
 350 2004-07-29  Alexandre Oliva  <aoliva@redhat.com>
 351
 352         Introduce SH2a support.
 353         * sh-opc.h (arch_sh2a_base): Renumber.
 354         (arch_sh2a_nofpu_base): Remove.
 355         (arch_sh_base_mask): Adjust.
 356         (arch_opann_mask): New.
 357         (arch_sh2a, arch_sh2a_nofpu): Adjust.
 358         (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
 359         (sh_table): Adjust whitespace.
 360         2004-02-24  Corinna Vinschen  <vinschen@redhat.com>
 361         * sh-opc.h (arch_sh2a_nofpu_up): New.  Use instead of arch_sh2a_up in
 362         instruction list throughout.
 363         (arch_sh2a_up): Redefine to include fpu instruction set.  Use instead
 364         of arch_sh2a in instruction list throughout.
 365         (arch_sh2e_up): Accomodate above changes.
 366         (arch_sh2_up): Ditto.
 367         2004-02-20  Corinna Vinschen  <vinschen@redhat.com>
 368         * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
 369         2004-02-18  Corinna Vinschen  <vinschen@redhat.com>
 370         * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
 371         * sh-opc.h (arch_sh2a_nofpu): New.
 372         (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
 373         (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
 374         instruction.
 375         2004-01-20  DJ Delorie  <dj@redhat.com>
 376         * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
 377         2003-12-29  DJ Delorie  <dj@redhat.com>
 378         * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
 379         sh_opcode_info, sh_table): Add sh2a support.
 380         (arch_op32): New, to tag 32-bit opcodes.
 381         * sh-dis.c (print_insn_sh): Support sh2a opcodes.
 382         2003-12-02  Michael Snyder  <msnyder@redhat.com>
 383         * sh-opc.h (arch_sh2a): Add.
 384         * sh-dis.c (arch_sh2a): Handle.
 385         * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
 386
 387 2004-07-27  Tomer Levi  <Tomer.Levi@nsc.com>
 388
 389         * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
 390
 391 2004-07-22  Nick Clifton  <nickc@redhat.com>
 392
 393         PR/280
 394         * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
 395         insns - this is done by objdump itself.
 396         * h8500-dis.c (print_insn_h8500): Likewise.
 397
 398 2004-07-21  Jan Beulich <jbeulich@novell.com>
 399
 400         * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
 401         regardless of address size prefix in effect.
 402         (ptr_reg): Size or address registers does not depend on rex64, but
 403         on the presence of an address size override.
 404         (OP_MMX): Use rex.x only for xmm registers.
 405         (OP_EM): Use rex.z only for xmm registers.
 406
 407 2004-07-20  Maciej W. Rozycki  <macro@linux-mips.org>
 408
 409         * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
 410         move/branch operations to the bottom so that VR5400 multimedia
 411         instructions take precedence in disassembly.
 412
 413 2004-07-20  Maciej W. Rozycki  <macro@linux-mips.org>
 414
 415         * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
 416         ISA-specific "break" encoding.
 417
 418 2004-07-13  Elvis Chiang  <elvisfb@gmail.com>
 419
 420         * arm-opc.h: Fix typo in comment.
 421
 422 2004-07-11  Andreas Schwab  <schwab@suse.de>
 423
 424         * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
 425
 426 2004-07-09  Andreas Schwab  <schwab@suse.de>
 427
 428         * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
 429
 430 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 431
 432         * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
 433         (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
 434         (crx-dis.lo): New target.
 435         (crx-opc.lo): Likewise.
 436         * Makefile.in: Regenerate.
 437         * configure.in: Handle bfd_crx_arch.
 438         * configure: Regenerate.
 439         * crx-dis.c: New file.
 440         * crx-opc.c: New file.
 441         * disassemble.c (ARCH_crx): Define.
 442         (disassembler): Handle ARCH_crx.
 443
 444 2004-06-29  James E Wilson  <wilson@specifixinc.com>
 445
 446         * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
 447         * ia64-asmtab.c: Regnerate.
 448
 449 2004-06-28  Alan Modra  <amodra@bigpond.net.au>
 450
 451         * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
 452         (extract_fxm): Don't test dialect.
 453         (XFXFXM_MASK): Include the power4 bit.
 454         (XFXM): Add p4 param.
 455         (powerpc_opcodes): Add mfocrf and mtocrf.  Adjust mtcr.
 456
 457 2004-06-27  Alexandre Oliva  <aoliva@redhat.com>
 458
 459         2003-07-21  Richard Sandiford  <rsandifo@redhat.com>
 460         * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
 461
 462 2004-06-26  Alan Modra  <amodra@bigpond.net.au>
 463
 464         * ppc-opc.c (BH, XLBH_MASK): Define.
 465         (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
 466
 467 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 468
 469         * i386-dis.c (x_mode): Comment.
 470         (two_source_ops): File scope.
 471         (float_mem): Correct fisttpll and fistpll.
 472         (float_mem_mode): New table.
 473         (dofloat): Use it.
 474         (OP_E): Correct intel mode PTR output.
 475         (ptr_reg): Use open_char and close_char.
 476         (PNI_Fixup): Handle possible suffix on sidt.  Use op1out etc. for
 477         operands.  Set two_source_ops.
 478
 479 2004-06-15  Alan Modra  <amodra@bigpond.net.au>
 480
 481         * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
 482         instead of _raw_size.
 483
 484 2004-06-08  Jakub Jelinek  <jakub@redhat.com>
 485
 486         * ia64-gen.c (in_iclass): Handle more postinc st
 487         and ld variants.
 488         * ia64-asmtab.c: Rebuilt.
 489
 490 2004-06-01  Martin Schwidefsky  <schwidefsky@de.ibm.com>
 491
 492         * s390-opc.txt: Correct architecture mask for some opcodes.
 493         lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
 494         in the esa mode as well.
 495
 496 2004-05-28  Andrew Stubbs <andrew.stubbs@superh.com>
 497
 498         * sh-dis.c (target_arch): Make unsigned.
 499         (print_insn_sh): Replace (most of) switch with a call to
 500         sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
 501         * sh-opc.h: Redefine architecture flags values.
 502         Add sh3-nommu architecture.
 503         Reorganise <arch>_up macros so they make more visual sense.
 504         (SH_MERGE_ARCH_SET): Define new macro.
 505         (SH_VALID_BASE_ARCH_SET): Likewise.
 506         (SH_VALID_MMU_ARCH_SET): Likewise.
 507         (SH_VALID_CO_ARCH_SET): Likewise.
 508         (SH_VALID_ARCH_SET): Likewise.
 509         (SH_MERGE_ARCH_SET_VALID): Likewise.
 510         (SH_ARCH_SET_HAS_FPU): Likewise.
 511         (SH_ARCH_SET_HAS_DSP): Likewise.
 512         (SH_ARCH_UNKNOWN_ARCH): Likewise.
 513         (sh_get_arch_from_bfd_mach): Add prototype.
 514         (sh_get_arch_up_from_bfd_mach): Likewise.
 515         (sh_get_bfd_mach_from_arch_set): Likewise.
 516         (sh_merge_bfd_arc): Likewise.
 517
 518 2004-05-24  Peter Barada  <peter@the-baradas.com>
 519
 520         * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
 521         into new match_insn_m68k function.  Loop over canidate
 522         matches and select first that completely matches.
 523         * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
 524         * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
 525         to verify addressing for MAC/EMAC.
 526         * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
 527         reigster halves since 'fpu' and 'spl' look misleading.
 528         * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
 529         * m68k-opc.c: Rearragne mac/emac cases to use longest for
 530         first, tighten up match masks.
 531         * m68k-opc.c: Add 'size' field to struct m68k_opcode.  Produce
 532         'size' from special case code in print_insn_m68k to
 533         determine decode size of insns.
 534
 535 2004-05-19  Alan Modra  <amodra@bigpond.net.au>
 536
 537         * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
 538         well as when -mpower4.
 539
 540 2004-05-13  Nick Clifton  <nickc@redhat.com>
 541
 542         * po/fr.po: Updated French translation.
 543
 544 2004-05-05  Peter Barada  <peter@the-baradas.com>
 545
 546         * m68k-dis.c(print_insn_m68k): Add new chips, use core
 547         variants in arch_mask.  Only set m68881/68851 for 68k chips.
 548         * m68k-op.c: Switch from ColdFire chips to core variants.
 549
 550 2004-05-05  Alan Modra  <amodra@bigpond.net.au>
 551
 552         PR 147.
 553         * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
 554
 555 2004-04-29  Ben Elliston  <bje@au.ibm.com>
 556
 557         * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
 558         (powerpc_opcodes): Add "dbczl" instruction for PPC970.
 559
 560 2004-04-22  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
 561
 562         * sh-dis.c (print_insn_sh): Print the value in constant pool
 563         as a symbol if it looks like a symbol.
 564
 565 2004-04-22  Peter Barada <peter@the-baradas.com>
 566
 567         * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
 568         appropriate ColdFire architectures.
 569         (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
 570         mask addressing.
 571         Add EMAC instructions, fix MAC instructions. Remove
 572         macmw/macml/msacmw/msacml instructions since mask addressing now
 573         supported.
 574
 575 2004-04-20  Jakub Jelinek  <jakub@redhat.com>
 576
 577         * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
 578         (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
 579         suffix.  Use fmov*x macros, create all 3 fpsize variants in one
 580         macro.  Adjust all users.
 581
 582 2004-04-15  Anil Paranjpe  <anilp1@kpitcummins.com>
 583
 584         * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
 585         separately.
 586
 587 2004-03-30  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
 588
 589         * m32r-asm.c: Regenerate.
 590
 591 2004-03-29  Stan Shebs  <shebs@apple.com>
 592
 593         * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
 594         used.
 595
 596 2004-03-19  Alan Modra  <amodra@bigpond.net.au>
 597
 598         * aclocal.m4: Regenerate.
 599         * config.in: Regenerate.
 600         * configure: Regenerate.
 601         * po/POTFILES.in: Regenerate.
 602         * po/opcodes.pot: Regenerate.
 603
 604 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 605
 606         * ppc-dis.c (print_insn_powerpc): Don't print tabs.  Handle
 607         PPC_OPERANDS_GPR_0.
 608         * ppc-opc.c (RA0): Define.
 609         (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
 610         (RAOPT): Rename from RAO.  Update all uses.
 611         (powerpc_opcodes): Use RA0 as appropriate.
 612
 613 2004-03-15  Aldy Hernandez  <aldyh@redhat.com>
 614
 615         * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
 616
 617 2004-03-15  Alan Modra  <amodra@bigpond.net.au>
 618
 619         * sparc-dis.c (print_insn_sparc): Update getword prototype.
 620
 621 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 622
 623         * i386-dis.c (GRPPLOCK): Delete.
 624         (grps): Delete GRPPLOCK entry.
 625
 626 2004-03-12  Alan Modra  <amodra@bigpond.net.au>
 627
 628         * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
 629         (M, Mp): Use OP_M.
 630         (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
 631         (GRPPADLCK): Define.
 632         (dis386): Use NOP_Fixup on "nop".
 633         (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
 634         (twobyte_has_modrm): Set for 0xa7.
 635         (padlock_table): Delete.  Move to..
 636         (grps): ..here, using OP_0f07.  Use OP_Ofae on lfence, mfence
 637         and clflush.
 638         (print_insn): Revert PADLOCK_SPECIAL code.
 639         (OP_E): Delete sfence, lfence, mfence checks.
 640
 641 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 642
 643         * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
 644         (INVLPG_Fixup): New function.
 645         (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
 646
 647 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 648
 649         * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
 650         (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
 651         (padlock_table): New struct with PadLock instructions.
 652         (print_insn): Handle PADLOCK_SPECIAL.
 653
 654 2004-03-12  Alan Modra  <amodra@bigpond.net.au>
 655
 656         * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
 657         (OP_E): Twiddle clflush to sfence here.
 658
 659 2004-03-08  Nick Clifton  <nickc@redhat.com>
 660
 661         * po/de.po: Updated German translation.
 662
 663 2003-03-03  Andrew Stubbs  <andrew.stubbs@superh.com>
 664
 665         * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
 666         nofpu mode.  Add BFD type bfd_mach_sh4_nommu_nofpu.
 667         * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
 668         accordingly.
 669
 670 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 671
 672         * frv-asm.c: Regenerate.
 673         * frv-desc.c: Regenerate.
 674         * frv-desc.h: Regenerate.
 675         * frv-dis.c: Regenerate.
 676         * frv-ibld.c: Regenerate.
 677         * frv-opc.c: Regenerate.
 678         * frv-opc.h: Regenerate.
 679
 680 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 681
 682         * frv-desc.c, frv-opc.c: Regenerate.
 683
 684 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 685
 686         * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
 687
 688 2004-02-26  Andrew Stubbs  <andrew.stubbs@superh.com>
 689
 690         * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
 691         Also correct mistake in the comment.
 692
 693 2004-02-26  Andrew Stubbs <andrew.stubbs@superh.com>
 694
 695         * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
 696         ensure that double registers have even numbers.
 697         Add REG_N_B01 for nn01 (binary 01) nibble to ensure
 698         that reserved instruction 0xfffd does not decode the same
 699         as 0xfdfd (ftrv).
 700         * sh-opc.h: Add REG_N_D nibble type and use it whereever
 701         REG_N refers to a double register.
 702         Add REG_N_B01 nibble type and use it instead of REG_NM
 703         in ftrv.
 704         Adjust the bit patterns in a few comments.
 705
 706 2004-02-25  Aldy Hernandez  <aldyh@redhat.com>
 707
 708         * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
 709
 710 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 711
 712         * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
 713
 714 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 715
 716         * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
 717
 718 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 719
 720         * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
 721         mtivor32, mtivor33, mtivor34.
 722
 723 2004-02-19  Aldy Hernandez  <aldyh@redhat.com>
 724
 725         * ppc-opc.c (powerpc_opcodes): Add mfmcar.
 726
 727 2004-02-10  Petko Manolov  <petkan@nucleusys.com>
 728
 729         * arm-opc.h Maverick accumulator register opcode fixes.
 730
 731 2004-02-13  Ben Elliston  <bje@wasabisystems.com>
 732
 733         * m32r-dis.c: Regenerate.
 734
 735 2004-01-27  Michael Snyder  <msnyder@redhat.com>
 736
 737         * sh-opc.h (sh_table): "fsrra", not "fssra".
 738
 739 2004-01-23  Andrew Over <andrew.over@cs.anu.edu.au>
 740
 741         * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
 742         contraints.
 743
 744 2004-01-19  Andrew Over  <andrew.over@cs.anu.edu.au>
 745
 746         * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
 747
 748 2004-01-19  Alan Modra  <amodra@bigpond.net.au>
 749
 750         * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
 751         1.  Don't print scale factor on AT&T mode when index missing.
 752
 753 2004-01-16  Alexandre Oliva  <aoliva@redhat.com>
 754
 755         * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
 756         when loaded into XR registers.
 757
 758 2004-01-14  Richard Sandiford  <rsandifo@redhat.com>
 759
 760         * frv-desc.h: Regenerate.
 761         * frv-desc.c: Regenerate.
 762         * frv-opc.c: Regenerate.
 763
 764 2004-01-13  Michael Snyder  <msnyder@redhat.com>
 765
 766         * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
 767
 768 2004-01-09  Paul Brook  <paul@codesourcery.com>
 769
 770         * arm-opc.h (arm_opcodes): Move generic mcrr after known
 771         specific opcodes.
 772
 773 2004-01-07  Daniel Jacobowitz  <drow@mvista.com>
 774
 775         * Makefile.am (libopcodes_la_DEPENDENCIES)
 776         (libopcodes_la_LIBADD): Revert 2003-05-17 change.  Add explanatory
 777         comment about the problem.
 778         * Makefile.in: Regenerate.
 779
 780 2004-01-06  Alexandre Oliva  <aoliva@redhat.com>
 781
 782         2003-12-19  Alexandre Oliva  <aoliva@redhat.com>
 783         * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
 784         cut&paste errors in shifting/truncating numerical operands.
 785         2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
 786         * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
 787         (parse_uslo16): Likewise.
 788         (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
 789         (parse_d12): Parse gotoff12 and gotofffuncdesc12.
 790         (parse_s12): Likewise.
 791         2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
 792         * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
 793         (parse_uslo16): Likewise.
 794         (parse_uhi16): Parse gothi and gotfuncdeschi.
 795         (parse_d12): Parse got12 and gotfuncdesc12.
 796         (parse_s12): Likewise.
 797
 798 2004-01-02  Albert Bartoszko  <albar@nt.kegel.com.pl>
 799
 800         * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
 801         instruction which looks similar to an 'rla' instruction.
 802
 803 For older changes see ChangeLog-0203
 804 \f
 805 Local Variables:
 806 mode: change-log
 807 left-margin: 8
 808 fill-column: 74
 809 version-control: never
 810 End: