opcodes/ChangeLog

   1 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
   2
   3         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
   4         and MPY class instructions.
   5         (parse_option): Add nps400 option.
   6         (print_arc_disassembler_options): Add nps400 info.
   7
   8 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
   9
  10         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
  11         (bspop): Likewise.
  12         (modapp): Likewise.
  13         * arc-opc.c (RAD_CHK): Add.
  14         * arc-tbl.h: Regenerate.
  15
  16 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
  17
  18         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
  19         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
  20
  21 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
  22
  23         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
  24         instructions as UNPREDICTABLE.
  25
  26 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
  27
  28         * bpf-desc.c: Regenerated.
  29
  30 2019-07-17  Jan Beulich  <jbeulich@suse.com>
  31
  32         * i386-gen.c (static_assert): Define.
  33         (main): Use it.
  34         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
  35         (Opcode_Modifier_Num): ... this.
  36         (Mem): Delete.
  37
  38 2019-07-16  Jan Beulich  <jbeulich@suse.com>
  39
  40         * i386-gen.c (operand_types): Move RegMem ...
  41         (opcode_modifiers): ... here.
  42         * i386-opc.h (RegMem): Move to opcode modifer enum.
  43         (union i386_operand_type): Move regmem field ...
  44         (struct i386_opcode_modifier): ... here.
  45         * i386-opc.tbl (RegMem): Define.
  46         (mov, movq): Move RegMem on segment, control, debug, and test
  47         register flavors.
  48         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
  49         to non-SSE2AVX flavor.
  50         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
  51         Move RegMem on register only flavors. Drop IgnoreSize from
  52         legacy encoding flavors.
  53         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
  54         flavors.
  55         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
  56         register only flavors.
  57         (vmovd): Move RegMem and drop IgnoreSize on register only
  58         flavor. Change opcode and operand order to store form.
  59         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
  60
  61 2019-07-16  Jan Beulich  <jbeulich@suse.com>
  62
  63         * i386-gen.c (operand_type_init, operand_types): Replace SReg
  64         entries.
  65         * i386-opc.h (SReg2, SReg3): Replace by ...
  66         (SReg): ... this.
  67         (union i386_operand_type): Replace sreg fields.
  68         * i386-opc.tbl (mov, ): Use SReg.
  69         (push, pop): Likewies. Drop i386 and x86-64 specific segment
  70         register flavors.
  71         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
  72         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
  73
  74 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
  75
  76         * bpf-desc.c: Regenerate.
  77         * bpf-opc.c: Likewise.
  78         * bpf-opc.h: Likewise.
  79
  80 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
  81
  82         * bpf-desc.c: Regenerate.
  83         * bpf-opc.c: Likewise.
  84
  85 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
  86
  87         * arm-dis.c (print_insn_coprocessor): Rename index to
  88         index_operand.
  89
  90 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
  91
  92         * riscv-opc.c (riscv_insn_types): Add r4 type.
  93
  94         * riscv-opc.c (riscv_insn_types): Add b and j type.
  95
  96         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
  97         format for sb type and correct s type.
  98
  99 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 100
 101         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 102         SVE FMOV alias of FCPY.
 103
 104 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 105
 106         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 107         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 108
 109 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 110
 111         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 112         registers in an instruction prefixed by MOVPRFX.
 113
 114 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 115
 116         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 117         sve_size_13 icode to account for variant behaviour of
 118         pmull{t,b}.
 119         * aarch64-dis-2.c: Regenerate.
 120         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 121         sve_size_13 icode to account for variant behaviour of
 122         pmull{t,b}.
 123         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 124         (OP_SVE_VVV_Q_D): Add new qualifier.
 125         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 126         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 127         AES and those not.
 128
 129 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 130
 131         * opcodes/i386-gen.c (operand_type_init): Remove
 132         OPERAND_TYPE_VEC_IMM4 entry.
 133         (operand_types): Remove Vec_Imm4.
 134         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 135         (union i386_operand_type): Remove vec_imm4.
 136         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 137         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 138
 139 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 140
 141         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 142         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 143         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 144         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 145         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 146         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 147         * i386-tbl.h: Re-generate.
 148
 149 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 150
 151         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 152         register operands.
 153         * i386-tbl.h: Re-generate.
 154
 155 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 156
 157         * i386-opc.tbl (C): New.
 158         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 159         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 160         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 161         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 162         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 163         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 164         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 165         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 166         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 167         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 168         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 169         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 170         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 171         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 172         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 173         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 174         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 175         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 176         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 177         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 178         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 179         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 180         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 181         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 182         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 183         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 184         flavors.
 185         * i386-tbl.h: Re-generate.
 186
 187 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 188
 189         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 190         register operands.
 191         * i386-tbl.h: Re-generate.
 192
 193 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 194
 195         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 196         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 197         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 198         * i386-tbl.h: Re-generate.
 199
 200 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 201
 202         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 203         Disp8MemShift from register only templates.
 204         * i386-tbl.h: Re-generate.
 205
 206 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 207
 208         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 209         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 210         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 211         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 212         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 213         EVEX_W_0F11_P_3_M_1): Delete.
 214         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 215         EVEX_W_0F11_P_3): New.
 216         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 217         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 218         MOD_EVEX_0F11_PREFIX_3 table entries.
 219         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 220         PREFIX_EVEX_0F11 table entries.
 221         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 222         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 223         EVEX_W_0F11_P_3_M_{0,1} table entries.
 224
 225 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 226
 227         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 228         Delete.
 229
 230 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 231
 232         PR binutils/24719
 233         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 234         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 235         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 236         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 237         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 238         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 239         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 240         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 241         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 242         PREFIX_EVEX_0F38C6_REG_6 entries.
 243         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 244         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 245         EVEX_W_0F38C7_R_6_P_2 entries.
 246         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 247         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 248         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 249         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 250         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 251         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 252         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 253
 254 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 255
 256         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 257         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 258         VEX_LEN_0F2D_P_3): Delete.
 259         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 260         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 261         (prefix_table): ... here.
 262
 263 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 264
 265         * i386-dis.c (Iq): Delete.
 266         (Id): New.
 267         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 268         TBM insns.
 269         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 270         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 271         (OP_E_memory): Also honor needindex when deciding whether an
 272         address size prefix needs printing.
 273         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 274
 275 2019-06-26  Jim Wilson  <jimw@sifive.com>
 276
 277         PR binutils/24739
 278         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 279         Set info->display_endian to info->endian_code.
 280
 281 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 282
 283         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 284         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 285         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 286         OPERAND_TYPE_ACC64 entries.
 287         * i386-init.h: Re-generate.
 288
 289 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 290
 291         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 292         Delete.
 293         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 294         of dqa_mode.
 295         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 296         entries here.
 297         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 298         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 299
 300 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 301
 302         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 303         variables.
 304
 305 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 306
 307         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 308         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 309         movnti.
 310         * i386-opc.tbl (movnti): Add IgnoreSize.
 311         * i386-tbl.h: Re-generate.
 312
 313 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 314
 315         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 316         * i386-tbl.h: Re-generate.
 317
 318 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 319
 320         * i386-dis-evex.h: Break into ...
 321         * i386-dis-evex-len.h: New file.
 322         * i386-dis-evex-mod.h: Likewise.
 323         * i386-dis-evex-prefix.h: Likewise.
 324         * i386-dis-evex-reg.h: Likewise.
 325         * i386-dis-evex-w.h: Likewise.
 326         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 327         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 328         i386-dis-evex-mod.h.
 329
 330 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 331
 332         PR binutils/24700
 333         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 334         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 335         EVEX_W_0F385B_P_2.
 336         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 337         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 338         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 339         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 340         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 341         EVEX_LEN_0F385B_P_2_W_1.
 342         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 343         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 344         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 345         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 346         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 347         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 348         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 349         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 350         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 351         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 352
 353 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 354
 355         PR binutils/24691
 356         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 357         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 358         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 359         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 360         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 361         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 362         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 363         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 364         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 365         EVEX_LEN_0F3A43_P_2_W_1.
 366         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 367         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 368         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 369         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 370         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 371         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 372         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 373         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 374         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 375         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 376         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 377         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 378
 379 2019-06-14  Nick Clifton  <nickc@redhat.com>
 380
 381         * po/fr.po; Updated French translation.
 382
 383 2019-06-13  Stafford Horne  <shorne@gmail.com>
 384
 385         * or1k-asm.c: Regenerated.
 386         * or1k-desc.c: Regenerated.
 387         * or1k-desc.h: Regenerated.
 388         * or1k-dis.c: Regenerated.
 389         * or1k-ibld.c: Regenerated.
 390         * or1k-opc.c: Regenerated.
 391         * or1k-opc.h: Regenerated.
 392         * or1k-opinst.c: Regenerated.
 393
 394 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 395
 396         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 397
 398 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 399
 400         PR binutils/24633
 401         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 402         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 403         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 404         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 405         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 406         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 407         EVEX_LEN_0F3A1B_P_2_W_1.
 408         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 409         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 410         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 411         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 412         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 413         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 414         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 415         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 416
 417 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 418
 419         PR binutils/24626
 420         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 421         EVEX.vvvv when disassembling VEX and EVEX instructions.
 422         (OP_VEX): Set vex.register_specifier to 0 after readding
 423         vex.register_specifier.
 424         (OP_Vex_2src_1): Likewise.
 425         (OP_Vex_2src_2): Likewise.
 426         (OP_LWP_E): Likewise.
 427         (OP_EX_Vex): Don't check vex.register_specifier.
 428         (OP_XMM_Vex): Likewise.
 429
 430 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 431             Lili Cui  <lili.cui@intel.com>
 432
 433         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 434         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 435         instructions.
 436         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 437         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 438         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 439         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 440         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 441         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 442         * i386-init.h: Regenerated.
 443         * i386-tbl.h: Likewise.
 444
 445 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 446             Lili Cui  <lili.cui@intel.com>
 447
 448         * doc/c-i386.texi: Document enqcmd.
 449         * testsuite/gas/i386/enqcmd-intel.d: New file.
 450         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 451         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 452         * testsuite/gas/i386/enqcmd.d: Likewise.
 453         * testsuite/gas/i386/enqcmd.s: Likewise.
 454         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 455         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 456         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 457         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 458         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 459         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 460         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 461         and x86-64-enqcmd.
 462
 463 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 464
 465         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 466
 467 2019-06-03  Alan Modra  <amodra@gmail.com>
 468
 469         * ppc-dis.c (prefix_opcd_indices): Correct size.
 470
 471 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 472
 473         PR gas/24625
 474         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 475         Disp8ShiftVL.
 476         * i386-tbl.h: Regenerated.
 477
 478 2019-05-24  Alan Modra  <amodra@gmail.com>
 479
 480         * po/POTFILES.in: Regenerate.
 481
 482 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 483             Alan Modra  <amodra@gmail.com>
 484
 485         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 486         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 487         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 488         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 489         XTOP>): Define and add entries.
 490         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 491         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 492         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 493         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 494
 495 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 496             Alan Modra  <amodra@gmail.com>
 497
 498         * ppc-dis.c (ppc_opts): Add "future" entry.
 499         (PREFIX_OPCD_SEGS): Define.
 500         (prefix_opcd_indices): New array.
 501         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 502         (lookup_prefix): New function.
 503         (print_insn_powerpc): Handle 64-bit prefix instructions.
 504         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 505         (PMRR, POWERXX): Define.
 506         (prefix_opcodes): New instruction table.
 507         (prefix_num_opcodes): New constant.
 508
 509 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 510
 511         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 512         * configure: Regenerated.
 513         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 514         and cpu/bpf.opc.
 515         (HFILES): Add bpf-desc.h and bpf-opc.h.
 516         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 517         bpf-ibld.c and bpf-opc.c.
 518         (BPF_DEPS): Define.
 519         * Makefile.in: Regenerated.
 520         * disassemble.c (ARCH_bpf): Define.
 521         (disassembler): Add case for bfd_arch_bpf.
 522         (disassemble_init_for_target): Likewise.
 523         (enum epbf_isa_attr): Define.
 524         * disassemble.h: extern print_insn_bpf.
 525         * bpf-asm.c: Generated.
 526         * bpf-opc.h: Likewise.
 527         * bpf-opc.c: Likewise.
 528         * bpf-ibld.c: Likewise.
 529         * bpf-dis.c: Likewise.
 530         * bpf-desc.h: Likewise.
 531         * bpf-desc.c: Likewise.
 532
 533 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 534
 535         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 536         and VMSR with the new operands.
 537
 538 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 539
 540         * arm-dis.c (enum mve_instructions): New enum
 541         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 542         and cneg.
 543         (mve_opcodes): New instructions as above.
 544         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 545         csneg and csel.
 546         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 547
 548 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 549
 550         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 551         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 552         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 553         uqshl, urshrl and urshr.
 554         (is_mve_okay_in_it): Add new instructions to TRUE list.
 555         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 556         (print_insn_mve): Updated to accept new %j,
 557         %<bitfield>m and %<bitfield>n patterns.
 558
 559 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 560
 561         * mips-opc.c (mips_builtin_opcodes): Change source register
 562         constraint for DAUI.
 563
 564 2019-05-20  Nick Clifton  <nickc@redhat.com>
 565
 566         * po/fr.po: Updated French translation.
 567
 568 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 569             Michael Collison <michael.collison@arm.com>
 570
 571         * arm-dis.c (thumb32_opcodes): Add new instructions.
 572         (enum mve_instructions): Likewise.
 573         (enum mve_undefined): Add new reasons.
 574         (is_mve_encoding_conflict): Handle new instructions.
 575         (is_mve_undefined): Likewise.
 576         (is_mve_unpredictable): Likewise.
 577         (print_mve_undefined): Likewise.
 578         (print_mve_size): Likewise.
 579
 580 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 581             Michael Collison <michael.collison@arm.com>
 582
 583         * arm-dis.c (thumb32_opcodes): Add new instructions.
 584         (enum mve_instructions): Likewise.
 585         (is_mve_encoding_conflict): Handle new instructions.
 586         (is_mve_undefined): Likewise.
 587         (is_mve_unpredictable): Likewise.
 588         (print_mve_size): Likewise.
 589
 590 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 591             Michael Collison <michael.collison@arm.com>
 592
 593         * arm-dis.c (thumb32_opcodes): Add new instructions.
 594         (enum mve_instructions): Likewise.
 595         (is_mve_encoding_conflict): Likewise.
 596         (is_mve_unpredictable): Likewise.
 597         (print_mve_size): Likewise.
 598
 599 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 600             Michael Collison <michael.collison@arm.com>
 601
 602         * arm-dis.c (thumb32_opcodes): Add new instructions.
 603         (enum mve_instructions): Likewise.
 604         (is_mve_encoding_conflict): Handle new instructions.
 605         (is_mve_undefined): Likewise.
 606         (is_mve_unpredictable): Likewise.
 607         (print_mve_size): Likewise.
 608
 609 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 610             Michael Collison <michael.collison@arm.com>
 611
 612         * arm-dis.c (thumb32_opcodes): Add new instructions.
 613         (enum mve_instructions): Likewise.
 614         (is_mve_encoding_conflict): Handle new instructions.
 615         (is_mve_undefined): Likewise.
 616         (is_mve_unpredictable): Likewise.
 617         (print_mve_size): Likewise.
 618         (print_insn_mve): Likewise.
 619
 620 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 621             Michael Collison <michael.collison@arm.com>
 622
 623         * arm-dis.c (thumb32_opcodes): Add new instructions.
 624         (print_insn_thumb32): Handle new instructions.
 625
 626 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 627             Michael Collison <michael.collison@arm.com>
 628
 629         * arm-dis.c (enum mve_instructions): Add new instructions.
 630         (enum mve_undefined): Add new reasons.
 631         (is_mve_encoding_conflict): Handle new instructions.
 632         (is_mve_undefined): Likewise.
 633         (is_mve_unpredictable): Likewise.
 634         (print_mve_undefined): Likewise.
 635         (print_mve_size): Likewise.
 636         (print_mve_shift_n): Likewise.
 637         (print_insn_mve): Likewise.
 638
 639 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 640             Michael Collison <michael.collison@arm.com>
 641
 642         * arm-dis.c (enum mve_instructions): Add new instructions.
 643         (is_mve_encoding_conflict): Handle new instructions.
 644         (is_mve_unpredictable): Likewise.
 645         (print_mve_rotate): Likewise.
 646         (print_mve_size): Likewise.
 647         (print_insn_mve): Likewise.
 648
 649 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 650             Michael Collison <michael.collison@arm.com>
 651
 652         * arm-dis.c (enum mve_instructions): Add new instructions.
 653         (is_mve_encoding_conflict): Handle new instructions.
 654         (is_mve_unpredictable): Likewise.
 655         (print_mve_size): Likewise.
 656         (print_insn_mve): Likewise.
 657
 658 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 659             Michael Collison <michael.collison@arm.com>
 660
 661         * arm-dis.c (enum mve_instructions): Add new instructions.
 662         (enum mve_undefined): Add new reasons.
 663         (is_mve_encoding_conflict): Handle new instructions.
 664         (is_mve_undefined): Likewise.
 665         (is_mve_unpredictable): Likewise.
 666         (print_mve_undefined): Likewise.
 667         (print_mve_size): Likewise.
 668         (print_insn_mve): Likewise.
 669
 670 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 671             Michael Collison <michael.collison@arm.com>
 672
 673         * arm-dis.c (enum mve_instructions): Add new instructions.
 674         (is_mve_encoding_conflict): Handle new instructions.
 675         (is_mve_undefined): Likewise.
 676         (is_mve_unpredictable): Likewise.
 677         (print_mve_size): Likewise.
 678         (print_insn_mve): Likewise.
 679
 680 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 681             Michael Collison <michael.collison@arm.com>
 682
 683         * arm-dis.c (enum mve_instructions): Add new instructions.
 684         (enum mve_unpredictable): Add new reasons.
 685         (enum mve_undefined): Likewise.
 686         (is_mve_okay_in_it): Handle new isntructions.
 687         (is_mve_encoding_conflict): Likewise.
 688         (is_mve_undefined): Likewise.
 689         (is_mve_unpredictable): Likewise.
 690         (print_mve_vmov_index): Likewise.
 691         (print_simd_imm8): Likewise.
 692         (print_mve_undefined): Likewise.
 693         (print_mve_unpredictable): Likewise.
 694         (print_mve_size): Likewise.
 695         (print_insn_mve): Likewise.
 696
 697 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 698             Michael Collison <michael.collison@arm.com>
 699
 700         * arm-dis.c (enum mve_instructions): Add new instructions.
 701         (enum mve_unpredictable): Add new reasons.
 702         (enum mve_undefined): Likewise.
 703         (is_mve_encoding_conflict): Handle new instructions.
 704         (is_mve_undefined): Likewise.
 705         (is_mve_unpredictable): Likewise.
 706         (print_mve_undefined): Likewise.
 707         (print_mve_unpredictable): Likewise.
 708         (print_mve_rounding_mode): Likewise.
 709         (print_mve_vcvt_size): Likewise.
 710         (print_mve_size): Likewise.
 711         (print_insn_mve): Likewise.
 712
 713 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 714             Michael Collison <michael.collison@arm.com>
 715
 716         * arm-dis.c (enum mve_instructions): Add new instructions.
 717         (enum mve_unpredictable): Add new reasons.
 718         (enum mve_undefined): Likewise.
 719         (is_mve_undefined): Handle new instructions.
 720         (is_mve_unpredictable): Likewise.
 721         (print_mve_undefined): Likewise.
 722         (print_mve_unpredictable): Likewise.
 723         (print_mve_size): Likewise.
 724         (print_insn_mve): Likewise.
 725
 726 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 727             Michael Collison <michael.collison@arm.com>
 728
 729         * arm-dis.c (enum mve_instructions): Add new instructions.
 730         (enum mve_undefined): Add new reasons.
 731         (insns): Add new instructions.
 732         (is_mve_encoding_conflict):
 733         (print_mve_vld_str_addr): New print function.
 734         (is_mve_undefined): Handle new instructions.
 735         (is_mve_unpredictable): Likewise.
 736         (print_mve_undefined): Likewise.
 737         (print_mve_size): Likewise.
 738         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 739         (print_insn_mve):  Handle new operands.
 740
 741 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 742             Michael Collison <michael.collison@arm.com>
 743
 744         * arm-dis.c (enum mve_instructions): Add new instructions.
 745         (enum mve_unpredictable): Add new reasons.
 746         (is_mve_encoding_conflict): Handle new instructions.
 747         (is_mve_unpredictable): Likewise.
 748         (mve_opcodes): Add new instructions.
 749         (print_mve_unpredictable): Handle new reasons.
 750         (print_mve_register_blocks): New print function.
 751         (print_mve_size): Handle new instructions.
 752         (print_insn_mve): Likewise.
 753
 754 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 755             Michael Collison <michael.collison@arm.com>
 756
 757         * arm-dis.c (enum mve_instructions): Add new instructions.
 758         (enum mve_unpredictable): Add new reasons.
 759         (enum mve_undefined): Likewise.
 760         (is_mve_encoding_conflict): Handle new instructions.
 761         (is_mve_undefined): Likewise.
 762         (is_mve_unpredictable): Likewise.
 763         (coprocessor_opcodes): Move NEON VDUP from here...
 764         (neon_opcodes): ... to here.
 765         (mve_opcodes): Add new instructions.
 766         (print_mve_undefined):  Handle new reasons.
 767         (print_mve_unpredictable): Likewise.
 768         (print_mve_size): Handle new instructions.
 769         (print_insn_neon): Handle vdup.
 770         (print_insn_mve): Handle new operands.
 771
 772 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 773             Michael Collison <michael.collison@arm.com>
 774
 775         * arm-dis.c (enum mve_instructions): Add new instructions.
 776         (enum mve_unpredictable): Add new values.
 777         (mve_opcodes): Add new instructions.
 778         (vec_condnames): New array with vector conditions.
 779         (mve_predicatenames): New array with predicate suffixes.
 780         (mve_vec_sizename): New array with vector sizes.
 781         (enum vpt_pred_state): New enum with vector predication states.
 782         (struct vpt_block): New struct type for vpt blocks.
 783         (vpt_block_state): Global struct to keep track of state.
 784         (mve_extract_pred_mask): New helper function.
 785         (num_instructions_vpt_block): Likewise.
 786         (mark_outside_vpt_block): Likewise.
 787         (mark_inside_vpt_block): Likewise.
 788         (invert_next_predicate_state): Likewise.
 789         (update_next_predicate_state): Likewise.
 790         (update_vpt_block_state): Likewise.
 791         (is_vpt_instruction): Likewise.
 792         (is_mve_encoding_conflict): Add entries for new instructions.
 793         (is_mve_unpredictable): Likewise.
 794         (print_mve_unpredictable): Handle new cases.
 795         (print_instruction_predicate): Likewise.
 796         (print_mve_size): New function.
 797         (print_vec_condition): New function.
 798         (print_insn_mve): Handle vpt blocks and new print operands.
 799
 800 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 801
 802         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 803         8, 14 and 15 for Armv8.1-M Mainline.
 804
 805 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 806             Michael Collison <michael.collison@arm.com>
 807
 808         * arm-dis.c (enum mve_instructions): New enum.
 809         (enum mve_unpredictable): Likewise.
 810         (enum mve_undefined): Likewise.
 811         (struct mopcode32): New struct.
 812         (is_mve_okay_in_it): New function.
 813         (is_mve_architecture): Likewise.
 814         (arm_decode_field): Likewise.
 815         (arm_decode_field_multiple): Likewise.
 816         (is_mve_encoding_conflict): Likewise.
 817         (is_mve_undefined): Likewise.
 818         (is_mve_unpredictable): Likewise.
 819         (print_mve_undefined): Likewise.
 820         (print_mve_unpredictable): Likewise.
 821         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 822         (print_insn_mve): New function.
 823         (print_insn_thumb32): Handle MVE architecture.
 824         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 825
 826 2019-05-10  Nick Clifton  <nickc@redhat.com>
 827
 828         PR 24538
 829         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 830         end of the table prematurely.
 831
 832 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 833
 834         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 835         macros for R6.
 836
 837 2019-05-11  Alan Modra  <amodra@gmail.com>
 838
 839         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 840         when -Mraw is in effect.
 841
 842 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 843
 844         * aarch64-dis-2.c: Regenerate.
 845         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 846         (OP_SVE_BBB): New variant set.
 847         (OP_SVE_DDDD): New variant set.
 848         (OP_SVE_HHH): New variant set.
 849         (OP_SVE_HHHU): New variant set.
 850         (OP_SVE_SSS): New variant set.
 851         (OP_SVE_SSSU): New variant set.
 852         (OP_SVE_SHH): New variant set.
 853         (OP_SVE_SBBU): New variant set.
 854         (OP_SVE_DSS): New variant set.
 855         (OP_SVE_DHHU): New variant set.
 856         (OP_SVE_VMV_HSD_BHS): New variant set.
 857         (OP_SVE_VVU_HSD_BHS): New variant set.
 858         (OP_SVE_VVVU_SD_BH): New variant set.
 859         (OP_SVE_VVVU_BHSD): New variant set.
 860         (OP_SVE_VVV_QHD_DBS): New variant set.
 861         (OP_SVE_VVV_HSD_BHS): New variant set.
 862         (OP_SVE_VVV_HSD_BHS2): New variant set.
 863         (OP_SVE_VVV_BHS_HSD): New variant set.
 864         (OP_SVE_VV_BHS_HSD): New variant set.
 865         (OP_SVE_VVV_SD): New variant set.
 866         (OP_SVE_VVU_BHS_HSD): New variant set.
 867         (OP_SVE_VZVV_SD): New variant set.
 868         (OP_SVE_VZVV_BH): New variant set.
 869         (OP_SVE_VZV_SD): New variant set.
 870         (aarch64_opcode_table): Add sve2 instructions.
 871
 872 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 873
 874         * aarch64-asm-2.c: Regenerated.
 875         * aarch64-dis-2.c: Regenerated.
 876         * aarch64-opc-2.c: Regenerated.
 877         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 878         for SVE_SHLIMM_UNPRED_22.
 879         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 880         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 881         operand.
 882
 883 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 884
 885         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 886         sve_size_tsz_bhs iclass encode.
 887         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 888         sve_size_tsz_bhs iclass decode.
 889
 890 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 891
 892         * aarch64-asm-2.c: Regenerated.
 893         * aarch64-dis-2.c: Regenerated.
 894         * aarch64-opc-2.c: Regenerated.
 895         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 896         for SVE_Zm4_11_INDEX.
 897         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 898         (fields): Handle SVE_i2h field.
 899         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 900         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 901
 902 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 903
 904         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 905         sve_shift_tsz_bhsd iclass encode.
 906         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 907         sve_shift_tsz_bhsd iclass decode.
 908
 909 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 910
 911         * aarch64-asm-2.c: Regenerated.
 912         * aarch64-dis-2.c: Regenerated.
 913         * aarch64-opc-2.c: Regenerated.
 914         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 915         (aarch64_encode_variant_using_iclass): Handle
 916         sve_shift_tsz_hsd iclass encode.
 917         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 918         sve_shift_tsz_hsd iclass decode.
 919         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 920         for SVE_SHRIMM_UNPRED_22.
 921         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 922         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 923         operand.
 924
 925 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 926
 927         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 928         sve_size_013 iclass encode.
 929         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 930         sve_size_013 iclass decode.
 931
 932 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 933
 934         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 935         sve_size_bh iclass encode.
 936         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 937         sve_size_bh iclass decode.
 938
 939 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 940
 941         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 942         sve_size_sd2 iclass encode.
 943         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 944         sve_size_sd2 iclass decode.
 945         * aarch64-opc.c (fields): Handle SVE_sz2 field.
 946         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
 947
 948 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 949
 950         * aarch64-asm-2.c: Regenerated.
 951         * aarch64-dis-2.c: Regenerated.
 952         * aarch64-opc-2.c: Regenerated.
 953         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 954         for SVE_ADDR_ZX.
 955         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
 956         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
 957
 958 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 959
 960         * aarch64-asm-2.c: Regenerated.
 961         * aarch64-dis-2.c: Regenerated.
 962         * aarch64-opc-2.c: Regenerated.
 963         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 964         for SVE_Zm3_11_INDEX.
 965         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
 966         (fields): Handle SVE_i3l and SVE_i3h2 fields.
 967         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
 968         fields.
 969         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
 970
 971 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 972
 973         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 974         sve_size_hsd2 iclass encode.
 975         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 976         sve_size_hsd2 iclass decode.
 977         * aarch64-opc.c (fields): Handle SVE_size field.
 978         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
 979
 980 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 981
 982         * aarch64-asm-2.c: Regenerated.
 983         * aarch64-dis-2.c: Regenerated.
 984         * aarch64-opc-2.c: Regenerated.
 985         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 986         for SVE_IMM_ROT3.
 987         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
 988         (fields): Handle SVE_rot3 field.
 989         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
 990         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
 991
 992 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 993
 994         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
 995         instructions.
 996
 997 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 998
 999         * aarch64-tbl.h
1000         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1001         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1002         aarch64_feature_sve2bitperm): New feature sets.
1003         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1004         for feature set addresses.
1005         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1006         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1007
1008 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1009             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1010
1011         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1012         argument and set ASE_EVA_R6 appropriately.
1013         (set_default_mips_dis_options): Pass ISA to above.
1014         (parse_mips_dis_option): Likewise.
1015         * mips-opc.c (EVAR6): New macro.
1016         (mips_builtin_opcodes): Add llwpe, scwpe.
1017
1018 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1019
1020         * aarch64-asm-2.c: Regenerated.
1021         * aarch64-dis-2.c: Regenerated.
1022         * aarch64-opc-2.c: Regenerated.
1023         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1024         AARCH64_OPND_TME_UIMM16.
1025         (aarch64_print_operand): Likewise.
1026         * aarch64-tbl.h (QL_IMM_NIL): New.
1027         (TME): New.
1028         (_TME_INSN): New.
1029         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1030
1031 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1032
1033         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1034
1035 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1036             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1037
1038         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1039
1040 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1041
1042         * s12z-opc.h: Add extern "C" bracketing to help
1043         users who wish to use this interface in c++ code.
1044
1045 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1046
1047         * s12z-opc.c (bm_decode): Handle bit map operations with the
1048         "reserved0" mode.
1049
1050 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1051
1052         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1053         specifier.  Add entries for VLDR and VSTR of system registers.
1054         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1055         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1056         of %J and %K format specifier.
1057
1058 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1059
1060         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1061         Add new entries for VSCCLRM instruction.
1062         (print_insn_coprocessor): Handle new %C format control code.
1063
1064 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1065
1066         * arm-dis.c (enum isa): New enum.
1067         (struct sopcode32): New structure.
1068         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1069         set isa field of all current entries to ANY.
1070         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1071         Only match an entry if its isa field allows the current mode.
1072
1073 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1074
1075         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1076         CLRM.
1077         (print_insn_thumb32): Add logic to print %n CLRM register list.
1078
1079 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1080
1081         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1082         and %Q patterns.
1083
1084 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1085
1086         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1087         (print_insn_thumb32): Edit the switch case for %Z.
1088
1089 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1090
1091         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1092
1093 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1094
1095         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1096
1097 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1098
1099         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1100
1101 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1102
1103         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1104         Arm register with r13 and r15 unpredictable.
1105         (thumb32_opcodes): New instructions for bfx and bflx.
1106
1107 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1108
1109         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1110
1111 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1112
1113         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1114
1115 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1116
1117         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1118
1119 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1120
1121         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1122
1123 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1124
1125         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1126         "optr". ("operator" is a reserved word in c++).
1127
1128 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1129
1130         * aarch64-opc.c (aarch64_print_operand): Add case for
1131         AARCH64_OPND_Rt_SP.
1132         (verify_constraints): Likewise.
1133         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1134         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1135         to accept Rt|SP as first operand.
1136         (AARCH64_OPERANDS): Add new Rt_SP.
1137         * aarch64-asm-2.c: Regenerated.
1138         * aarch64-dis-2.c: Regenerated.
1139         * aarch64-opc-2.c: Regenerated.
1140
1141 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1142
1143         * aarch64-asm-2.c: Regenerated.
1144         * aarch64-dis-2.c: Likewise.
1145         * aarch64-opc-2.c: Likewise.
1146         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1147
1148 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1149
1150         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1151
1152 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1153
1154         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1155         * i386-init.h: Regenerated.
1156
1157 2019-04-07  Alan Modra  <amodra@gmail.com>
1158
1159         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1160         op_separator to control printing of spaces, comma and parens
1161         rather than need_comma, need_paren and spaces vars.
1162
1163 2019-04-07  Alan Modra  <amodra@gmail.com>
1164
1165         PR 24421
1166         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1167         (print_insn_neon, print_insn_arm): Likewise.
1168
1169 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1170
1171         * i386-dis-evex.h (evex_table): Updated to support BF16
1172         instructions.
1173         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1174         and EVEX_W_0F3872_P_3.
1175         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1176         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1177         * i386-opc.h (enum): Add CpuAVX512_BF16.
1178         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1179         * i386-opc.tbl: Add AVX512 BF16 instructions.
1180         * i386-init.h: Regenerated.
1181         * i386-tbl.h: Likewise.
1182
1183 2019-04-05  Alan Modra  <amodra@gmail.com>
1184
1185         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1186         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1187         to favour printing of "-" branch hint when using the "y" bit.
1188         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1189
1190 2019-04-05  Alan Modra  <amodra@gmail.com>
1191
1192         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1193         opcode until first operand is output.
1194
1195 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1196
1197         PR gas/24349
1198         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1199         (valid_bo_post_v2): Add support for 'at' branch hints.
1200         (insert_bo): Only error on branch on ctr.
1201         (get_bo_hint_mask): New function.
1202         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1203         for inserting 'at' branch hints.
1204         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1205         for extracting 'at' branch hints.
1206         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1207         (BOE): Delete operand.
1208         (BOM, BOP): New operands.
1209         (RM): Update value.
1210         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1211         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1212         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1213         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1214         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1215         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1216         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1217         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1218         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1219         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1220         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1221         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1222         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1223         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1224         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1225         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1226         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1227         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1228         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1229         bttarl+>: New extended mnemonics.
1230
1231 2019-03-28  Alan Modra  <amodra@gmail.com>
1232
1233         PR 24390
1234         * ppc-opc.c (BTF): Define.
1235         (powerpc_opcodes): Use for mtfsb*.
1236         * ppc-dis.c (print_insn_powerpc): Print fields with both
1237         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1238
1239 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1240
1241         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1242         (mapping_symbol_for_insn): Implement new algorithm.
1243         (print_insn): Remove duplicate code.
1244
1245 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1246
1247         * aarch64-dis.c (print_insn_aarch64):
1248         Implement override.
1249
1250 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1251
1252         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1253         order.
1254
1255 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1256
1257         * aarch64-dis.c (last_stop_offset): New.
1258         (print_insn_aarch64): Use stop_offset.
1259
1260 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1261
1262         PR gas/24359
1263         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1264         CPU_ANY_AVX2_FLAGS.
1265         * i386-init.h: Regenerated.
1266
1267 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1268
1269         PR gas/24348
1270         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1271         vmovdqu16, vmovdqu32 and vmovdqu64.
1272         * i386-tbl.h: Regenerated.
1273
1274 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1275
1276         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1277         from vstrszb, vstrszh, and vstrszf.
1278
1279 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1280
1281         * s390-opc.txt: Add instruction descriptions.
1282
1283 2019-02-08  Jim Wilson  <jimw@sifive.com>
1284
1285         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1286         <bne>: Likewise.
1287
1288 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1289
1290         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1291
1292 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1293
1294         PR binutils/23212
1295         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1296         * aarch64-opc.c (verify_elem_sd): New.
1297         (fields): Add FLD_sz entr.
1298         * aarch64-tbl.h (_SIMD_INSN): New.
1299         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1300         fmulx scalar and vector by element isns.
1301
1302 2019-02-07  Nick Clifton  <nickc@redhat.com>
1303
1304         * po/sv.po: Updated Swedish translation.
1305
1306 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1307
1308         * s390-mkopc.c (main): Accept arch13 as cpu string.
1309         * s390-opc.c: Add new instruction formats and instruction opcode
1310         masks.
1311         * s390-opc.txt: Add new arch13 instructions.
1312
1313 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1314
1315         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1316         (aarch64_opcode): Change encoding for stg, stzg
1317         st2g and st2zg.
1318         * aarch64-asm-2.c: Regenerated.
1319         * aarch64-dis-2.c: Regenerated.
1320         * aarch64-opc-2.c: Regenerated.
1321
1322 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1323
1324         * aarch64-asm-2.c: Regenerated.
1325         * aarch64-dis-2.c: Likewise.
1326         * aarch64-opc-2.c: Likewise.
1327         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1328
1329 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1330             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1331
1332         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1333         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1334         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1335         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1336         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1337         case for ldstgv_indexed.
1338         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1339         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1340         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1341         * aarch64-asm-2.c: Regenerated.
1342         * aarch64-dis-2.c: Regenerated.
1343         * aarch64-opc-2.c: Regenerated.
1344
1345 2019-01-23  Nick Clifton  <nickc@redhat.com>
1346
1347         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1348
1349 2019-01-21  Nick Clifton  <nickc@redhat.com>
1350
1351         * po/de.po: Updated German translation.
1352         * po/uk.po: Updated Ukranian translation.
1353
1354 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1355         * mips-dis.c (mips_arch_choices): Fix typo in
1356         gs464, gs464e and gs264e descriptors.
1357
1358 2019-01-19  Nick Clifton  <nickc@redhat.com>
1359
1360         * configure: Regenerate.
1361         * po/opcodes.pot: Regenerate.
1362
1363 2018-06-24  Nick Clifton  <nickc@redhat.com>
1364
1365         2.32 branch created.
1366
1367 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1368
1369         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1370         if it is null.
1371         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1372         zero.
1373
1374 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1375
1376         * configure: Regenerate.
1377
1378 2019-01-07  Alan Modra  <amodra@gmail.com>
1379
1380         * configure: Regenerate.
1381         * po/POTFILES.in: Regenerate.
1382
1383 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1384
1385         * s12z-opc.c: New file.
1386         * s12z-opc.h: New file.
1387         * s12z-dis.c: Removed all code not directly related to display
1388         of instructions.  Used the interface provided by the new files
1389         instead.
1390         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1391         * Makefile.in: Regenerate.
1392         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1393         * configure: Regenerate.
1394
1395 2019-01-01  Alan Modra  <amodra@gmail.com>
1396
1397         Update year range in copyright notice of all files.
1398
1399 For older changes see ChangeLog-2018
1400 \f
1401 Copyright (C) 2019 Free Software Foundation, Inc.
1402
1403 Copying and distribution of this file, with or without modification,
1404 are permitted in any medium without royalty provided the copyright
1405 notice and this notice are preserved.
1406
1407 Local Variables:
1408 mode: change-log
1409 left-margin: 8
1410 fill-column: 74
1411 version-control: never
1412 End: