opcodes/ChangeLog

   1 2021-05-06  Stafford Horne  <shorne@gmail.com>
   2
   3         PR 21464
   4         * or1k-asm.c: Regenerate.
   5
   6 2021-05-01  Max Filippov  <jcmvbkbc@gmail.com>
   7
   8         * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
   9         info->insn_info_valid.
  10
  11 2021-04-26  Jan Beulich  <jbeulich@suse.com>
  12
  13         * i386-opc.tbl (lea): Add Optimize.
  14         * opcodes/i386-tbl.h: Re-generate.
  15
  16 2020-04-23  Max Filippov  <jcmvbkbc@gmail.com>
  17
  18         * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
  19         of l32r fetch and display referenced literal value.
  20
  21 2021-04-23  Max Filippov  <jcmvbkbc@gmail.com>
  22
  23         * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
  24         to 4 for literal disassembly.
  25
  26 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  27
  28         * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
  29         for TLBI instruction.
  30
  31 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  32
  33         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
  34         DC instruction.
  35
  36 2021-04-19  Jan Beulich  <jbeulich@suse.com>
  37
  38         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
  39         "qualifier".
  40         (convert_mov_to_movewide): Add initializer for "value".
  41
  42 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  43
  44         * aarch64-opc.c: Add RME system registers.
  45
  46 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
  47
  48         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
  49         "addi d,CV,z" to "c.mv d,CV".
  50
  51 2021-04-12  Alan Modra  <amodra@gmail.com>
  52
  53         * configure.ac (--enable-checking): Add support.
  54         * config.in: Regenerate.
  55         * configure: Regenerate.
  56
  57 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
  58
  59         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
  60         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
  61
  62 2021-04-09  Alan Modra  <amodra@gmail.com>
  63
  64         * ppc-dis.c (struct dis_private): Add "special".
  65         (POWERPC_DIALECT): Delete.  Replace uses with..
  66         (private_data): ..this.  New inline function.
  67         (disassemble_init_powerpc): Init "special" names.
  68         (skip_optional_operands): Add is_pcrel arg, set when detecting R
  69         field of prefix instructions.
  70         (bsearch_reloc, print_got_plt): New functions.
  71         (print_insn_powerpc): For pcrel instructions, print target address
  72         and symbol if known, and decode plt and got loads too.
  73
  74 2021-04-08  Alan Modra  <amodra@gmail.com>
  75
  76         PR 27684
  77         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
  78
  79 2021-04-08  Alan Modra  <amodra@gmail.com>
  80
  81         PR 27676
  82         * ppc-opc.c (DCBT_EO): Move earlier.
  83         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
  84         (powerpc_operands): Add THCT and THDS entries.
  85         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
  86
  87 2021-04-06  Alan Modra  <amodra@gmail.com>
  88
  89         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
  90         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
  91         symbol_at_address_func.
  92
  93 2021-04-05  Alan Modra  <amodra@gmail.com>
  94
  95         * configure.ac: Don't check for limits.h, string.h, strings.h or
  96         stdlib.h.
  97         (AC_ISC_POSIX): Don't invoke.
  98         * sysdep.h: Include stdlib.h and string.h unconditionally.
  99         * i386-opc.h: Include limits.h unconditionally.
 100         * wasm32-dis.c: Likewise.
 101         * cgen-opc.c: Don't include alloca-conf.h.
 102         * config.in: Regenerate.
 103         * configure: Regenerate.
 104
 105 2021-04-01  Martin Liska  <mliska@suse.cz>
 106
 107         * arm-dis.c (strneq): Remove strneq and use startswith.
 108         * cr16-dis.c (print_insn_cr16): Likewise.
 109         * score-dis.c (streq): Likewise.
 110         (strneq): Likewise.
 111         * score7-dis.c (strneq): Likewise.
 112
 113 2021-04-01  Alan Modra  <amodra@gmail.com>
 114
 115         PR 27675
 116         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
 117
 118 2021-03-31  Alan Modra  <amodra@gmail.com>
 119
 120         * sysdep.h (POISON_BFD_BOOLEAN): Define.
 121         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
 122         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
 123         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
 124         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
 125         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
 126         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
 127         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
 128         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
 129         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 130         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 131         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 132         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 133         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 134         and TRUE with true throughout.
 135
 136 2021-03-31  Alan Modra  <amodra@gmail.com>
 137
 138         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 139         * aarch64-dis.h: Likewise.
 140         * aarch64-opc.c: Likewise.
 141         * avr-dis.c: Likewise.
 142         * csky-dis.c: Likewise.
 143         * nds32-asm.c: Likewise.
 144         * nds32-dis.c: Likewise.
 145         * nfp-dis.c: Likewise.
 146         * riscv-dis.c: Likewise.
 147         * s12z-dis.c: Likewise.
 148         * wasm32-dis.c: Likewise.
 149
 150 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 151
 152         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 153         (i386_seg_prefixes): New.
 154         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 155         (i386_seg_prefixes): Declare.
 156
 157 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 158
 159         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 160
 161 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 162
 163         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 164         * i386-reg.tbl (st): Move down.
 165         (st(0)): Delete. Extend comment.
 166         * i386-tbl.h: Re-generate.
 167
 168 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 169
 170         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 171         (cmpsd): Move next to cmps.
 172         (movsd): Move next to movs.
 173         (cmpxchg16b): Move to separate section.
 174         (fisttp, fisttpll): Likewise.
 175         (monitor, mwait): Likewise.
 176         * i386-tbl.h: Re-generate.
 177
 178 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 179
 180         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 181         (vpsadbw): Add C.
 182         * i386-tbl.h: Re-generate.
 183
 184 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 185
 186         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 187         pclmul, gfni): New templates. Use them wherever possible. Move
 188         SSE4.1 pextrw into respective section.
 189         * i386-tbl.h: Re-generate.
 190
 191 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 192
 193         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 194         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 195         "length".
 196         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 197         Convert all of their uses to representation in opcode.
 198
 199 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 200
 201         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 202         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 203         value of None. Shrink operands to 3 bits.
 204
 205 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 206
 207         * i386-gen.c (process_i386_opcode_modifier): New parameter
 208         "space".
 209         (output_i386_opcode): New local variable "space". Adjust
 210         process_i386_opcode_modifier() invocation.
 211         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 212         invocation.
 213         * i386-tbl.h: Re-generate.
 214
 215 2021-03-29  Alan Modra  <amodra@gmail.com>
 216
 217         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 218         (fp_qualifier_p, get_data_pattern): Likewise.
 219         (aarch64_get_operand_modifier_from_value): Likewise.
 220         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 221         (operand_variant_qualifier_p): Likewise.
 222         (qualifier_value_in_range_constraint_p): Likewise.
 223         (aarch64_get_qualifier_esize): Likewise.
 224         (aarch64_get_qualifier_nelem): Likewise.
 225         (aarch64_get_qualifier_standard_value): Likewise.
 226         (get_lower_bound, get_upper_bound): Likewise.
 227         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 228         (aarch64_print_operand): Likewise.
 229         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 230         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 231         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 232         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 233         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 234         (print_insn_tic6x): Likewise.
 235
 236 2021-03-29  Alan Modra  <amodra@gmail.com>
 237
 238         * arc-dis.c (extract_operand_value): Correct NULL cast.
 239         * frv-opc.h: Regenerate.
 240
 241 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 242
 243         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 244         MMX form.
 245         * i386-tbl.h: Re-generate.
 246
 247 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 248
 249         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 250         immediate in br.n instruction.
 251
 252 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 253
 254         * i386-dis.c (XMGatherD, VexGatherD): New.
 255         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 256         (print_insn): Check masking for S/G insns.
 257         (OP_E_memory): New local variable check_gather. Extend mandatory
 258         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 259         Extend check for disallowed 16-bit addressing.
 260         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 261         if()s to switch(). Check register conflicts for (VEX-encoded)
 262         gathers. Drop no longer reachable cases.
 263         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 264         vgatherdp*.
 265
 266 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 267
 268         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 269         zeroing-masking without masking.
 270
 271 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 272
 273         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 274         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 275         single-operand forms as deprecated.
 276         * i386-tbl.h: Re-generate.
 277
 278 2021-03-25  Alan Modra  <amodra@gmail.com>
 279
 280         PR 27647
 281         * ppc-opc.c (XLOCB_MASK): Delete.
 282         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 283         XLBH_MASK.
 284         (powerpc_opcodes): Accept a BH field on all extended forms of
 285         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 286
 287 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 288
 289         * i386-gen.c (output_i386_opcode): Drop processing of
 290         opcode_length. Calculate length from base_opcode. Adjust prefix
 291         encoding determination.
 292         (process_i386_opcodes): Drop output of fake opcode_length.
 293         * i386-opc.h (struct insn_template): Drop opcode_length field.
 294         * i386-opc.tbl: Drop opcode length field from all templates.
 295         * i386-tbl.h: Re-generate.
 296
 297 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 298
 299         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 300         parameter "prefix". Drop local variable "regular_encoding".
 301         Record prefix setting / check for consistency.
 302         (output_i386_opcode): Parse opcode_length and base_opcode
 303         earlier. Derive prefix encoding. Drop no longer applicable
 304         consistency checking. Adjust process_i386_opcode_modifier()
 305         invocation.
 306         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 307         invocation.
 308         * i386-tbl.h: Re-generate.
 309
 310 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 311
 312         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 313         check.
 314         * i386-opc.h (Prefix_*): Move #define-s.
 315         * i386-opc.tbl: Move pseudo prefix enumerator values to
 316         extension opcode field. Introduce pseudopfx template.
 317         * i386-tbl.h: Re-generate.
 318
 319 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 320
 321         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 322         comment.
 323         * i386-tbl.h: Re-generate.
 324
 325 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 326
 327         * i386-opc.h (struct insn_template): Move cpu_flags field past
 328         opcode_modifier one.
 329         * i386-tbl.h: Re-generate.
 330
 331 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 332
 333         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 334         * i386-opc.h (OpcodeSpace): New enumerator.
 335         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 336         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 337         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 338         (struct i386_opcode_modifier): New field opcodespace. Shrink
 339         opcodeprefix field.
 340         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 341         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 342         OpcodePrefix uses.
 343         * i386-tbl.h: Re-generate.
 344
 345 2021-03-22  Martin Liska  <mliska@suse.cz>
 346
 347         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 348         * arc-dis.c (parse_option): Likewise.
 349         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 350         * cris-dis.c (print_with_operands): Likewise.
 351         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 352         * i386-dis.c (print_insn): Likewise.
 353         * ia64-gen.c (fetch_insn_class): Likewise.
 354         (parse_resource_users): Likewise.
 355         (in_iclass): Likewise.
 356         (lookup_specifier): Likewise.
 357         (insert_opcode_dependencies): Likewise.
 358         * mips-dis.c (parse_mips_ase_option): Likewise.
 359         (parse_mips_dis_option): Likewise.
 360         * s390-dis.c (disassemble_init_s390): Likewise.
 361         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 362
 363 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 364
 365         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 366
 367 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 368
 369         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 370         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 371
 372 2021-03-12  Alan Modra  <amodra@gmail.com>
 373
 374         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 375
 376 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 377
 378         * i386-dis.c (OP_XMM): Re-order checks.
 379
 380 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 381
 382         * i386-dis.c (putop): Drop need_vex check when also checking
 383         vex.evex.
 384         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 385         checking vex.b.
 386
 387 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 388
 389         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 390         checks. Move case label past broadcast check.
 391
 392 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 393
 394         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 395         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 396         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 397         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 398         EVEX_W_0F38C7_M_0_L_2): Delete.
 399         (REG_EVEX_0F38C7_M_0_L_2): New.
 400         (intel_operand_size): Handle VEX and EVEX the same for
 401         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 402         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 403         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 404         vex_vsib_q_w_d_mode uses.
 405         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 406         0F38A1, and 0F38A3 entries.
 407         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 408         entry.
 409         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 410         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 411         0F38A3 entries.
 412
 413 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 414
 415         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 416         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 417         MOD_VEX_0FXOP_09_12): Rename to ...
 418         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 419         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 420         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 421         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 422         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 423         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 424         (reg_table): Adjust comments.
 425         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 426         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 427         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 428         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 429         (vex_len_table): Adjust opcode 0A_12 entry.
 430         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 431         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 432         (rm_table): Move hreset entry.
 433
 434 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 435
 436         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 437         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 438         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 439         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 440         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 441         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 442         (get_valid_dis386): Also handle 512-bit vector length when
 443         vectoring into vex_len_table[].
 444         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 445         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 446         entries.
 447         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 448         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 449         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 450         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 451         entries.
 452
 453 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 454
 455         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 456         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 457         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 458         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 459         entries.
 460         * i386-dis-evex-len.h (evex_len_table): Likewise.
 461         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 462
 463 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 464
 465         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 466         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 467         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 468         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 469         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 470         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 471         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 472         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 473         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 474         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 475         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 476         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 477         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 478         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 479         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 480         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 481         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 482         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 483         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 484         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 485         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 486         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 487         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 488         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 489         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 490         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 491         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 492         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 493         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 494         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 495         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 496         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 497         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 498         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 499         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 500         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 501         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 502         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 503         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 504         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 505         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 506         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 507         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 508         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 509         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 510         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 511         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 512         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 513         EVEX_W_0F3A43_L_n): New.
 514         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 515         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 516         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 517         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 518         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 519         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 520         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 521         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 522         0F385B, 0F38C6, and 0F38C7 entries.
 523         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 524         0F38C6 and 0F38C7.
 525         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 526         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 527         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 528         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 529
 530 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 531
 532         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 533         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 534         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 535         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 536         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 537         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 538         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 539         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 540         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 541         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 542         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 543         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 544         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 545         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 546         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 547         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 548         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 549         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 550         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 551         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 552         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 553         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 554         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 555         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 556         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 557         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 558         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 559         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 560         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 561         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 562         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 563         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 564         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 565         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 566         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 567         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 568         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 569         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 570         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 571         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 572         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 573         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 574         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 575         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 576         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 577         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 578         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 579         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 580         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 581         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 582         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 583         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 584         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 585         VEX_W_0F99_P_2_LEN_0): Delete.
 586         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 587         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 588         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 589         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 590         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 591         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 592         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 593         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 594         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 595         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 596         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 597         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 598         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 599         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 600         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 601         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 602         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 603         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 604         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 605         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 606         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 607         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 608         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 609         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 610         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 611         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 612         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 613         (prefix_table): No longer link to vex_len_table[] for opcodes
 614         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 615         0F92, 0F93, 0F98, and 0F99.
 616         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 617         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 618         0F98, and 0F99.
 619         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 620         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 621         0F98, and 0F99.
 622         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 623         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 624         0F98, and 0F99.
 625         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 626         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 627         0F98, and 0F99.
 628
 629 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 630
 631         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 632         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 633         REG_VEX_0F73_M_0 respectively.
 634         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 635         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 636         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 637         MOD_VEX_0F73_REG_7): Delete.
 638         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 639         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 640         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 641         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 642         PREFIX_VEX_0F3AF0_L_0 respectively.
 643         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 644         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 645         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 646         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 647         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 648         VEX_LEN_0F38F7): New.
 649         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 650         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 651         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 652         0F38F3.
 653         (prefix_table): No longer link to vex_len_table[] for opcodes
 654         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 655         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 656         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 657         0F38F6, 0F38F7, and 0F3AF0.
 658         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 659         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 660         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 661         0F73.
 662
 663 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 664
 665         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 666         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 667         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 668         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 669         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 670         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 671         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 672         73.
 673         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 674         0F72, and 0F73.
 675         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 676         0F73.
 677
 678 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 679
 680         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 681         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 682         (reg_table): Don't link to mod_table[] where not needed. Add
 683         PREFIX_IGNORED to nop entries.
 684         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 685         (mod_table): Add nop entries next to prefetch ones. Drop
 686         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 687         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 688         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 689         PREFIX_OPCODE from endbr* entries.
 690         (get_valid_dis386): Also consider entry's name when zapping
 691         vindex.
 692         (print_insn): Handle PREFIX_IGNORED.
 693
 694 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 695
 696         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 697         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 698         element.
 699         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 700         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 701         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 702         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 703         (struct i386_opcode_modifier): Delete notrackprefixok,
 704         islockable, hleprefixok, and repprefixok fields. Add prefixok
 705         field.
 706         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 707         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 708         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 709         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 710         Replace HLEPrefixOk.
 711         * opcodes/i386-tbl.h: Re-generate.
 712
 713 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 714
 715         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 716         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 717         64-bit form.
 718         * opcodes/i386-tbl.h: Re-generate.
 719
 720 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 721
 722         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 723         for {} instead of {0}. Don't look for '0'.
 724         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 725         size specifiers.
 726
 727 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 728
 729         PR 27158
 730         * riscv-dis.c (print_insn_args): Updated encoding macros.
 731         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 732         (match_c_addi16sp): Updated encoding macros.
 733         (match_c_lui): Likewise.
 734         (match_c_lui_with_hint): Likewise.
 735         (match_c_addi4spn): Likewise.
 736         (match_c_slli): Likewise.
 737         (match_slli_as_c_slli): Likewise.
 738         (match_c_slli64): Likewise.
 739         (match_srxi_as_c_srxi): Likewise.
 740         (riscv_insn_types): Added .insn css/cl/cs.
 741
 742 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 743
 744         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 745         (default_priv_spec): Updated type to riscv_spec_class.
 746         (parse_riscv_dis_option): Updated.
 747         * riscv-opc.c: Moved stuff and make the file tidy.
 748
 749 2021-02-17  Alan Modra  <amodra@gmail.com>
 750
 751         * wasm32-dis.c: Include limits.h.
 752         (CHAR_BIT): Provide backup define.
 753         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 754         Correct signed overflow checking.
 755
 756 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 757
 758         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 759         * i386-tbl.h: Re-generate.
 760
 761 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 762
 763         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 764         Oword.
 765         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 766
 767 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 768
 769         * s390-mkopc.c (main): Accept arch14 as cpu string.
 770         * s390-opc.txt: Add new arch14 instructions.
 771
 772 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 773
 774         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 775         favour of LIBINTL.
 776         * configure: Regenerated.
 777
 778 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 779
 780         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 781         * tic54x-opc.c (regs): Rename to ...
 782         (tic54x_regs): ... this.
 783         (mmregs): Rename to ...
 784         (tic54x_mmregs): ... this.
 785         (condition_codes): Rename to ...
 786         (tic54x_condition_codes): ... this.
 787         (cc2_codes): Rename to ...
 788         (tic54x_cc2_codes): ... this.
 789         (cc3_codes): Rename to ...
 790         (tic54x_cc3_codes): ... this.
 791         (status_bits): Rename to ...
 792         (tic54x_status_bits): ... this.
 793         (misc_symbols): Rename to ...
 794         (tic54x_misc_symbols): ... this.
 795
 796 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
 797
 798         * riscv-opc.c (MASK_RVB_IMM): Removed.
 799         (riscv_opcodes): Removed zb* instructions.
 800         (riscv_ext_version_table): Removed versions for zb*.
 801
 802 2021-01-26  Alan Modra  <amodra@gmail.com>
 803
 804         * i386-gen.c (parse_template): Ensure entire template_instance
 805         is initialised.
 806
 807 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 808
 809         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
 810         (riscv_fpr_names_abi): Likewise.
 811         (riscv_opcodes): Likewise.
 812         (riscv_insn_types): Likewise.
 813
 814 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 815
 816         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 817
 818 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 819
 820         * riscv-dis.c: Comments tidy and improvement.
 821         * riscv-opc.c: Likewise.
 822
 823 2021-01-13  Alan Modra  <amodra@gmail.com>
 824
 825         * Makefile.in: Regenerate.
 826
 827 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 828
 829         PR binutils/26792
 830         * configure.ac: Use GNU_MAKE_JOBSERVER.
 831         * aclocal.m4: Regenerated.
 832         * configure: Likewise.
 833
 834 2021-01-12  Nick Clifton  <nickc@redhat.com>
 835
 836         * po/sr.po: Updated Serbian translation.
 837
 838 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
 839
 840         PR ld/27173
 841         * configure: Regenerated.
 842
 843 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 844
 845         * aarch64-asm-2.c: Regenerate.
 846         * aarch64-dis-2.c: Likewise.
 847         * aarch64-opc-2.c: Likewise.
 848         * aarch64-opc.c (aarch64_print_operand):
 849         Delete handling of AARCH64_OPND_CSRE_CSR.
 850         * aarch64-tbl.h (aarch64_feature_csre): Delete.
 851         (CSRE): Likewise.
 852         (_CSRE_INSN): Likewise.
 853         (aarch64_opcode_table): Delete csr.
 854
 855 2021-01-11  Nick Clifton  <nickc@redhat.com>
 856
 857         * po/de.po: Updated German translation.
 858         * po/fr.po: Updated French translation.
 859         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 860         * po/sv.po: Updated Swedish translation.
 861         * po/uk.po: Updated Ukranian translation.
 862
 863 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
 864
 865         * configure: Regenerated.
 866
 867 2021-01-09  Nick Clifton  <nickc@redhat.com>
 868
 869         * configure: Regenerate.
 870         * po/opcodes.pot: Regenerate.
 871
 872 2021-01-09  Nick Clifton  <nickc@redhat.com>
 873
 874         * 2.36 release branch crated.
 875
 876 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
 877
 878         * ppc-opc.c (insert_dw, (extract_dw): New functions.
 879         (DW, (XRC_MASK): Define.
 880         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
 881
 882 2021-01-09  Alan Modra  <amodra@gmail.com>
 883
 884         * configure: Regenerate.
 885
 886 2021-01-08  Nick Clifton  <nickc@redhat.com>
 887
 888         * po/sv.po: Updated Swedish translation.
 889
 890 2021-01-08  Nick Clifton  <nickc@redhat.com>
 891
 892         PR 27129
 893         * aarch64-dis.c (determine_disassembling_preference): Move call to
 894         aarch64_match_operands_constraint outside of the assertion.
 895         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
 896         Replace with a return of FALSE.
 897
 898         PR 27139
 899         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
 900         core system register.
 901
 902 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
 903
 904         * configure: Regenerate.
 905
 906 2021-01-07  Nick Clifton  <nickc@redhat.com>
 907
 908         * po/fr.po: Updated French translation.
 909
 910 2021-01-07  Fredrik Noring  <noring@nocrew.org>
 911
 912         * m68k-opc.c (chkl): Change minimum architecture requirement to
 913         m68020.
 914
 915 2021-01-07  Philipp Tomsich  <prt@gnu.org>
 916
 917         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
 918
 919 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
 920             Jim Wilson  <jimw@sifive.com>
 921             Andrew Waterman  <andrew@sifive.com>
 922             Maxim Blinov  <maxim.blinov@embecosm.com>
 923             Kito Cheng  <kito.cheng@sifive.com>
 924             Nelson Chu  <nelson.chu@sifive.com>
 925
 926         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
 927         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
 928
 929 2021-01-01  Alan Modra  <amodra@gmail.com>
 930
 931         Update year range in copyright notice of all files.
 932
 933 For older changes see ChangeLog-2020
 934 \f
 935 Copyright (C) 2021 Free Software Foundation, Inc.
 936
 937 Copying and distribution of this file, with or without modification,
 938 are permitted in any medium without royalty provided the copyright
 939 notice and this notice are preserved.
 940
 941 Local Variables:
 942 mode: change-log
 943 left-margin: 8
 944 fill-column: 74
 945 version-control: never
 946 End: