opcodes/ChangeLog

   1 2021-04-23  Max Filippov  <jcmvbkbc@gmail.com>
   2
   3         * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
   4         to 4 for literal disassembly.
   5
   6 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
   7
   8         * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
   9         for TLBI instruction.
  10
  11 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  12
  13         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
  14         DC instruction.
  15
  16 2021-04-19  Jan Beulich  <jbeulich@suse.com>
  17
  18         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
  19         "qualifier".
  20         (convert_mov_to_movewide): Add initializer for "value".
  21
  22 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  23
  24         * aarch64-opc.c: Add RME system registers.
  25
  26 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
  27
  28         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
  29         "addi d,CV,z" to "c.mv d,CV".
  30
  31 2021-04-12  Alan Modra  <amodra@gmail.com>
  32
  33         * configure.ac (--enable-checking): Add support.
  34         * config.in: Regenerate.
  35         * configure: Regenerate.
  36
  37 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
  38
  39         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
  40         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
  41
  42 2021-04-09  Alan Modra  <amodra@gmail.com>
  43
  44         * ppc-dis.c (struct dis_private): Add "special".
  45         (POWERPC_DIALECT): Delete.  Replace uses with..
  46         (private_data): ..this.  New inline function.
  47         (disassemble_init_powerpc): Init "special" names.
  48         (skip_optional_operands): Add is_pcrel arg, set when detecting R
  49         field of prefix instructions.
  50         (bsearch_reloc, print_got_plt): New functions.
  51         (print_insn_powerpc): For pcrel instructions, print target address
  52         and symbol if known, and decode plt and got loads too.
  53
  54 2021-04-08  Alan Modra  <amodra@gmail.com>
  55
  56         PR 27684
  57         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
  58
  59 2021-04-08  Alan Modra  <amodra@gmail.com>
  60
  61         PR 27676
  62         * ppc-opc.c (DCBT_EO): Move earlier.
  63         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
  64         (powerpc_operands): Add THCT and THDS entries.
  65         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
  66
  67 2021-04-06  Alan Modra  <amodra@gmail.com>
  68
  69         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
  70         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
  71         symbol_at_address_func.
  72
  73 2021-04-05  Alan Modra  <amodra@gmail.com>
  74
  75         * configure.ac: Don't check for limits.h, string.h, strings.h or
  76         stdlib.h.
  77         (AC_ISC_POSIX): Don't invoke.
  78         * sysdep.h: Include stdlib.h and string.h unconditionally.
  79         * i386-opc.h: Include limits.h unconditionally.
  80         * wasm32-dis.c: Likewise.
  81         * cgen-opc.c: Don't include alloca-conf.h.
  82         * config.in: Regenerate.
  83         * configure: Regenerate.
  84
  85 2021-04-01  Martin Liska  <mliska@suse.cz>
  86
  87         * arm-dis.c (strneq): Remove strneq and use startswith.
  88         * cr16-dis.c (print_insn_cr16): Likewise.
  89         * score-dis.c (streq): Likewise.
  90         (strneq): Likewise.
  91         * score7-dis.c (strneq): Likewise.
  92
  93 2021-04-01  Alan Modra  <amodra@gmail.com>
  94
  95         PR 27675
  96         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
  97
  98 2021-03-31  Alan Modra  <amodra@gmail.com>
  99
 100         * sysdep.h (POISON_BFD_BOOLEAN): Define.
 101         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
 102         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
 103         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
 104         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
 105         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
 106         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
 107         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
 108         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
 109         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 110         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 111         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 112         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 113         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 114         and TRUE with true throughout.
 115
 116 2021-03-31  Alan Modra  <amodra@gmail.com>
 117
 118         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 119         * aarch64-dis.h: Likewise.
 120         * aarch64-opc.c: Likewise.
 121         * avr-dis.c: Likewise.
 122         * csky-dis.c: Likewise.
 123         * nds32-asm.c: Likewise.
 124         * nds32-dis.c: Likewise.
 125         * nfp-dis.c: Likewise.
 126         * riscv-dis.c: Likewise.
 127         * s12z-dis.c: Likewise.
 128         * wasm32-dis.c: Likewise.
 129
 130 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 131
 132         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 133         (i386_seg_prefixes): New.
 134         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 135         (i386_seg_prefixes): Declare.
 136
 137 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 138
 139         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 140
 141 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 142
 143         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 144         * i386-reg.tbl (st): Move down.
 145         (st(0)): Delete. Extend comment.
 146         * i386-tbl.h: Re-generate.
 147
 148 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 149
 150         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 151         (cmpsd): Move next to cmps.
 152         (movsd): Move next to movs.
 153         (cmpxchg16b): Move to separate section.
 154         (fisttp, fisttpll): Likewise.
 155         (monitor, mwait): Likewise.
 156         * i386-tbl.h: Re-generate.
 157
 158 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 159
 160         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 161         (vpsadbw): Add C.
 162         * i386-tbl.h: Re-generate.
 163
 164 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 165
 166         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 167         pclmul, gfni): New templates. Use them wherever possible. Move
 168         SSE4.1 pextrw into respective section.
 169         * i386-tbl.h: Re-generate.
 170
 171 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 172
 173         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 174         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 175         "length".
 176         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 177         Convert all of their uses to representation in opcode.
 178
 179 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 180
 181         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 182         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 183         value of None. Shrink operands to 3 bits.
 184
 185 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 186
 187         * i386-gen.c (process_i386_opcode_modifier): New parameter
 188         "space".
 189         (output_i386_opcode): New local variable "space". Adjust
 190         process_i386_opcode_modifier() invocation.
 191         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 192         invocation.
 193         * i386-tbl.h: Re-generate.
 194
 195 2021-03-29  Alan Modra  <amodra@gmail.com>
 196
 197         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 198         (fp_qualifier_p, get_data_pattern): Likewise.
 199         (aarch64_get_operand_modifier_from_value): Likewise.
 200         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 201         (operand_variant_qualifier_p): Likewise.
 202         (qualifier_value_in_range_constraint_p): Likewise.
 203         (aarch64_get_qualifier_esize): Likewise.
 204         (aarch64_get_qualifier_nelem): Likewise.
 205         (aarch64_get_qualifier_standard_value): Likewise.
 206         (get_lower_bound, get_upper_bound): Likewise.
 207         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 208         (aarch64_print_operand): Likewise.
 209         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 210         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 211         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 212         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 213         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 214         (print_insn_tic6x): Likewise.
 215
 216 2021-03-29  Alan Modra  <amodra@gmail.com>
 217
 218         * arc-dis.c (extract_operand_value): Correct NULL cast.
 219         * frv-opc.h: Regenerate.
 220
 221 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 222
 223         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 224         MMX form.
 225         * i386-tbl.h: Re-generate.
 226
 227 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 228
 229         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 230         immediate in br.n instruction.
 231
 232 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 233
 234         * i386-dis.c (XMGatherD, VexGatherD): New.
 235         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 236         (print_insn): Check masking for S/G insns.
 237         (OP_E_memory): New local variable check_gather. Extend mandatory
 238         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 239         Extend check for disallowed 16-bit addressing.
 240         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 241         if()s to switch(). Check register conflicts for (VEX-encoded)
 242         gathers. Drop no longer reachable cases.
 243         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 244         vgatherdp*.
 245
 246 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 247
 248         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 249         zeroing-masking without masking.
 250
 251 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 252
 253         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 254         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 255         single-operand forms as deprecated.
 256         * i386-tbl.h: Re-generate.
 257
 258 2021-03-25  Alan Modra  <amodra@gmail.com>
 259
 260         PR 27647
 261         * ppc-opc.c (XLOCB_MASK): Delete.
 262         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 263         XLBH_MASK.
 264         (powerpc_opcodes): Accept a BH field on all extended forms of
 265         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 266
 267 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 268
 269         * i386-gen.c (output_i386_opcode): Drop processing of
 270         opcode_length. Calculate length from base_opcode. Adjust prefix
 271         encoding determination.
 272         (process_i386_opcodes): Drop output of fake opcode_length.
 273         * i386-opc.h (struct insn_template): Drop opcode_length field.
 274         * i386-opc.tbl: Drop opcode length field from all templates.
 275         * i386-tbl.h: Re-generate.
 276
 277 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 278
 279         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 280         parameter "prefix". Drop local variable "regular_encoding".
 281         Record prefix setting / check for consistency.
 282         (output_i386_opcode): Parse opcode_length and base_opcode
 283         earlier. Derive prefix encoding. Drop no longer applicable
 284         consistency checking. Adjust process_i386_opcode_modifier()
 285         invocation.
 286         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 287         invocation.
 288         * i386-tbl.h: Re-generate.
 289
 290 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 291
 292         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 293         check.
 294         * i386-opc.h (Prefix_*): Move #define-s.
 295         * i386-opc.tbl: Move pseudo prefix enumerator values to
 296         extension opcode field. Introduce pseudopfx template.
 297         * i386-tbl.h: Re-generate.
 298
 299 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 300
 301         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 302         comment.
 303         * i386-tbl.h: Re-generate.
 304
 305 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 306
 307         * i386-opc.h (struct insn_template): Move cpu_flags field past
 308         opcode_modifier one.
 309         * i386-tbl.h: Re-generate.
 310
 311 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 312
 313         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 314         * i386-opc.h (OpcodeSpace): New enumerator.
 315         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 316         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 317         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 318         (struct i386_opcode_modifier): New field opcodespace. Shrink
 319         opcodeprefix field.
 320         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 321         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 322         OpcodePrefix uses.
 323         * i386-tbl.h: Re-generate.
 324
 325 2021-03-22  Martin Liska  <mliska@suse.cz>
 326
 327         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 328         * arc-dis.c (parse_option): Likewise.
 329         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 330         * cris-dis.c (print_with_operands): Likewise.
 331         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 332         * i386-dis.c (print_insn): Likewise.
 333         * ia64-gen.c (fetch_insn_class): Likewise.
 334         (parse_resource_users): Likewise.
 335         (in_iclass): Likewise.
 336         (lookup_specifier): Likewise.
 337         (insert_opcode_dependencies): Likewise.
 338         * mips-dis.c (parse_mips_ase_option): Likewise.
 339         (parse_mips_dis_option): Likewise.
 340         * s390-dis.c (disassemble_init_s390): Likewise.
 341         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 342
 343 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 344
 345         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 346
 347 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 348
 349         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 350         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 351
 352 2021-03-12  Alan Modra  <amodra@gmail.com>
 353
 354         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 355
 356 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 357
 358         * i386-dis.c (OP_XMM): Re-order checks.
 359
 360 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 361
 362         * i386-dis.c (putop): Drop need_vex check when also checking
 363         vex.evex.
 364         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 365         checking vex.b.
 366
 367 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 368
 369         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 370         checks. Move case label past broadcast check.
 371
 372 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 373
 374         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 375         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 376         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 377         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 378         EVEX_W_0F38C7_M_0_L_2): Delete.
 379         (REG_EVEX_0F38C7_M_0_L_2): New.
 380         (intel_operand_size): Handle VEX and EVEX the same for
 381         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 382         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 383         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 384         vex_vsib_q_w_d_mode uses.
 385         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 386         0F38A1, and 0F38A3 entries.
 387         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 388         entry.
 389         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 390         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 391         0F38A3 entries.
 392
 393 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 394
 395         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 396         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 397         MOD_VEX_0FXOP_09_12): Rename to ...
 398         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 399         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 400         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 401         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 402         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 403         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 404         (reg_table): Adjust comments.
 405         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 406         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 407         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 408         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 409         (vex_len_table): Adjust opcode 0A_12 entry.
 410         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 411         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 412         (rm_table): Move hreset entry.
 413
 414 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 415
 416         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 417         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 418         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 419         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 420         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 421         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 422         (get_valid_dis386): Also handle 512-bit vector length when
 423         vectoring into vex_len_table[].
 424         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 425         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 426         entries.
 427         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 428         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 429         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 430         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 431         entries.
 432
 433 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 434
 435         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 436         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 437         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 438         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 439         entries.
 440         * i386-dis-evex-len.h (evex_len_table): Likewise.
 441         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 442
 443 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 444
 445         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 446         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 447         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 448         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 449         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 450         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 451         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 452         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 453         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 454         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 455         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 456         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 457         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 458         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 459         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 460         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 461         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 462         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 463         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 464         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 465         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 466         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 467         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 468         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 469         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 470         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 471         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 472         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 473         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 474         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 475         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 476         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 477         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 478         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 479         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 480         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 481         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 482         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 483         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 484         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 485         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 486         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 487         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 488         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 489         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 490         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 491         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 492         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 493         EVEX_W_0F3A43_L_n): New.
 494         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 495         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 496         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 497         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 498         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 499         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 500         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 501         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 502         0F385B, 0F38C6, and 0F38C7 entries.
 503         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 504         0F38C6 and 0F38C7.
 505         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 506         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 507         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 508         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 509
 510 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 511
 512         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 513         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 514         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 515         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 516         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 517         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 518         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 519         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 520         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 521         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 522         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 523         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 524         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 525         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 526         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 527         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 528         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 529         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 530         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 531         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 532         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 533         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 534         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 535         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 536         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 537         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 538         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 539         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 540         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 541         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 542         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 543         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 544         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 545         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 546         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 547         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 548         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 549         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 550         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 551         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 552         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 553         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 554         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 555         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 556         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 557         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 558         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 559         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 560         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 561         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 562         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 563         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 564         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 565         VEX_W_0F99_P_2_LEN_0): Delete.
 566         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 567         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 568         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 569         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 570         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 571         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 572         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 573         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 574         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 575         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 576         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 577         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 578         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 579         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 580         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 581         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 582         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 583         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 584         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 585         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 586         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 587         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 588         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 589         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 590         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 591         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 592         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 593         (prefix_table): No longer link to vex_len_table[] for opcodes
 594         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 595         0F92, 0F93, 0F98, and 0F99.
 596         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 597         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 598         0F98, and 0F99.
 599         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 600         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 601         0F98, and 0F99.
 602         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 603         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 604         0F98, and 0F99.
 605         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 606         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 607         0F98, and 0F99.
 608
 609 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 610
 611         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 612         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 613         REG_VEX_0F73_M_0 respectively.
 614         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 615         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 616         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 617         MOD_VEX_0F73_REG_7): Delete.
 618         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 619         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 620         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 621         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 622         PREFIX_VEX_0F3AF0_L_0 respectively.
 623         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 624         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 625         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 626         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 627         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 628         VEX_LEN_0F38F7): New.
 629         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 630         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 631         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 632         0F38F3.
 633         (prefix_table): No longer link to vex_len_table[] for opcodes
 634         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 635         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 636         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 637         0F38F6, 0F38F7, and 0F3AF0.
 638         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 639         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 640         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 641         0F73.
 642
 643 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 644
 645         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 646         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 647         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 648         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 649         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 650         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 651         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 652         73.
 653         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 654         0F72, and 0F73.
 655         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 656         0F73.
 657
 658 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 659
 660         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 661         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 662         (reg_table): Don't link to mod_table[] where not needed. Add
 663         PREFIX_IGNORED to nop entries.
 664         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 665         (mod_table): Add nop entries next to prefetch ones. Drop
 666         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 667         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 668         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 669         PREFIX_OPCODE from endbr* entries.
 670         (get_valid_dis386): Also consider entry's name when zapping
 671         vindex.
 672         (print_insn): Handle PREFIX_IGNORED.
 673
 674 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 675
 676         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 677         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 678         element.
 679         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 680         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 681         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 682         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 683         (struct i386_opcode_modifier): Delete notrackprefixok,
 684         islockable, hleprefixok, and repprefixok fields. Add prefixok
 685         field.
 686         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 687         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 688         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 689         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 690         Replace HLEPrefixOk.
 691         * opcodes/i386-tbl.h: Re-generate.
 692
 693 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 694
 695         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 696         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 697         64-bit form.
 698         * opcodes/i386-tbl.h: Re-generate.
 699
 700 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 701
 702         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 703         for {} instead of {0}. Don't look for '0'.
 704         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 705         size specifiers.
 706
 707 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 708
 709         PR 27158
 710         * riscv-dis.c (print_insn_args): Updated encoding macros.
 711         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 712         (match_c_addi16sp): Updated encoding macros.
 713         (match_c_lui): Likewise.
 714         (match_c_lui_with_hint): Likewise.
 715         (match_c_addi4spn): Likewise.
 716         (match_c_slli): Likewise.
 717         (match_slli_as_c_slli): Likewise.
 718         (match_c_slli64): Likewise.
 719         (match_srxi_as_c_srxi): Likewise.
 720         (riscv_insn_types): Added .insn css/cl/cs.
 721
 722 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 723
 724         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 725         (default_priv_spec): Updated type to riscv_spec_class.
 726         (parse_riscv_dis_option): Updated.
 727         * riscv-opc.c: Moved stuff and make the file tidy.
 728
 729 2021-02-17  Alan Modra  <amodra@gmail.com>
 730
 731         * wasm32-dis.c: Include limits.h.
 732         (CHAR_BIT): Provide backup define.
 733         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 734         Correct signed overflow checking.
 735
 736 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 737
 738         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 739         * i386-tbl.h: Re-generate.
 740
 741 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 742
 743         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 744         Oword.
 745         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 746
 747 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 748
 749         * s390-mkopc.c (main): Accept arch14 as cpu string.
 750         * s390-opc.txt: Add new arch14 instructions.
 751
 752 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 753
 754         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 755         favour of LIBINTL.
 756         * configure: Regenerated.
 757
 758 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 759
 760         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 761         * tic54x-opc.c (regs): Rename to ...
 762         (tic54x_regs): ... this.
 763         (mmregs): Rename to ...
 764         (tic54x_mmregs): ... this.
 765         (condition_codes): Rename to ...
 766         (tic54x_condition_codes): ... this.
 767         (cc2_codes): Rename to ...
 768         (tic54x_cc2_codes): ... this.
 769         (cc3_codes): Rename to ...
 770         (tic54x_cc3_codes): ... this.
 771         (status_bits): Rename to ...
 772         (tic54x_status_bits): ... this.
 773         (misc_symbols): Rename to ...
 774         (tic54x_misc_symbols): ... this.
 775
 776 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
 777
 778         * riscv-opc.c (MASK_RVB_IMM): Removed.
 779         (riscv_opcodes): Removed zb* instructions.
 780         (riscv_ext_version_table): Removed versions for zb*.
 781
 782 2021-01-26  Alan Modra  <amodra@gmail.com>
 783
 784         * i386-gen.c (parse_template): Ensure entire template_instance
 785         is initialised.
 786
 787 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 788
 789         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
 790         (riscv_fpr_names_abi): Likewise.
 791         (riscv_opcodes): Likewise.
 792         (riscv_insn_types): Likewise.
 793
 794 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 795
 796         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 797
 798 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 799
 800         * riscv-dis.c: Comments tidy and improvement.
 801         * riscv-opc.c: Likewise.
 802
 803 2021-01-13  Alan Modra  <amodra@gmail.com>
 804
 805         * Makefile.in: Regenerate.
 806
 807 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 808
 809         PR binutils/26792
 810         * configure.ac: Use GNU_MAKE_JOBSERVER.
 811         * aclocal.m4: Regenerated.
 812         * configure: Likewise.
 813
 814 2021-01-12  Nick Clifton  <nickc@redhat.com>
 815
 816         * po/sr.po: Updated Serbian translation.
 817
 818 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
 819
 820         PR ld/27173
 821         * configure: Regenerated.
 822
 823 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 824
 825         * aarch64-asm-2.c: Regenerate.
 826         * aarch64-dis-2.c: Likewise.
 827         * aarch64-opc-2.c: Likewise.
 828         * aarch64-opc.c (aarch64_print_operand):
 829         Delete handling of AARCH64_OPND_CSRE_CSR.
 830         * aarch64-tbl.h (aarch64_feature_csre): Delete.
 831         (CSRE): Likewise.
 832         (_CSRE_INSN): Likewise.
 833         (aarch64_opcode_table): Delete csr.
 834
 835 2021-01-11  Nick Clifton  <nickc@redhat.com>
 836
 837         * po/de.po: Updated German translation.
 838         * po/fr.po: Updated French translation.
 839         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 840         * po/sv.po: Updated Swedish translation.
 841         * po/uk.po: Updated Ukranian translation.
 842
 843 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
 844
 845         * configure: Regenerated.
 846
 847 2021-01-09  Nick Clifton  <nickc@redhat.com>
 848
 849         * configure: Regenerate.
 850         * po/opcodes.pot: Regenerate.
 851
 852 2021-01-09  Nick Clifton  <nickc@redhat.com>
 853
 854         * 2.36 release branch crated.
 855
 856 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
 857
 858         * ppc-opc.c (insert_dw, (extract_dw): New functions.
 859         (DW, (XRC_MASK): Define.
 860         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
 861
 862 2021-01-09  Alan Modra  <amodra@gmail.com>
 863
 864         * configure: Regenerate.
 865
 866 2021-01-08  Nick Clifton  <nickc@redhat.com>
 867
 868         * po/sv.po: Updated Swedish translation.
 869
 870 2021-01-08  Nick Clifton  <nickc@redhat.com>
 871
 872         PR 27129
 873         * aarch64-dis.c (determine_disassembling_preference): Move call to
 874         aarch64_match_operands_constraint outside of the assertion.
 875         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
 876         Replace with a return of FALSE.
 877
 878         PR 27139
 879         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
 880         core system register.
 881
 882 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
 883
 884         * configure: Regenerate.
 885
 886 2021-01-07  Nick Clifton  <nickc@redhat.com>
 887
 888         * po/fr.po: Updated French translation.
 889
 890 2021-01-07  Fredrik Noring  <noring@nocrew.org>
 891
 892         * m68k-opc.c (chkl): Change minimum architecture requirement to
 893         m68020.
 894
 895 2021-01-07  Philipp Tomsich  <prt@gnu.org>
 896
 897         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
 898
 899 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
 900             Jim Wilson  <jimw@sifive.com>
 901             Andrew Waterman  <andrew@sifive.com>
 902             Maxim Blinov  <maxim.blinov@embecosm.com>
 903             Kito Cheng  <kito.cheng@sifive.com>
 904             Nelson Chu  <nelson.chu@sifive.com>
 905
 906         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
 907         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
 908
 909 2021-01-01  Alan Modra  <amodra@gmail.com>
 910
 911         Update year range in copyright notice of all files.
 912
 913 For older changes see ChangeLog-2020
 914 \f
 915 Copyright (C) 2021 Free Software Foundation, Inc.
 916
 917 Copying and distribution of this file, with or without modification,
 918 are permitted in any medium without royalty provided the copyright
 919 notice and this notice are preserved.
 920
 921 Local Variables:
 922 mode: change-log
 923 left-margin: 8
 924 fill-column: 74
 925 version-control: never
 926 End: