opcodes/ChangeLog

   1 2015-11-20  Matthew Wahab  <matthew.wahab@arm.com>
   2
   3         * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
   4         sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
   5         tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
   6         amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
   7         cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
   8         cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
   9         cnthv_ctl_el2, cnthv_cval_el2.
  10         (aarch64_sys_reg_supported_p): Update for the new system
  11         registers.
  12
  13 2015-11-20  Nick Clifton  <nickc@redhat.com>
  14
  15         PR binutils/19224
  16         * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
  17
  18 2015-11-20  Nick Clifton  <nickc@redhat.com>
  19
  20         * po/zh_CN.po: Updated simplified Chinese translation.
  21
  22 2015-11-19  Matthew Wahab  <matthew.wahab@arm.com>
  23
  24         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
  25         of MSR PAN immediate operand.
  26
  27 2015-11-16  Nick Clifton  <nickc@redhat.com>
  28
  29         * rx-dis.c (condition_names): Replace always and never with
  30         invalid, since the always/never conditions can never be legal.
  31
  32 2015-11-13  Tristan Gingold  <gingold@adacore.com>
  33
  34         * configure: Regenerate.
  35
  36 2015-11-11  Alan Modra  <amodra@gmail.com>
  37             Peter Bergner <bergner@vnet.ibm.com>
  38
  39         * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
  40         Add PPC_OPCODE_VSX3 to the vsx entry.
  41         (powerpc_init_dialect): Set default dialect to power9.
  42         * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
  43         insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
  44         extract_l1 insert_xtq6, extract_xtq6): New static functions.
  45         (insert_esync): Test for illegal L operand value.
  46         (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
  47         XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
  48         XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
  49         XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
  50         PPCVSX3): New defines.
  51         (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
  52         fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
  53         <mcrxr>: Use XBFRARB_MASK.
  54         <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
  55         bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
  56         cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
  57         cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
  58         lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
  59         lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
  60         modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
  61         rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
  62         stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
  63         subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
  64         vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
  65         vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
  66         vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
  67         vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
  68         vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
  69         vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
  70         vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
  71         xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
  72         xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
  73         xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
  74         xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
  75         xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
  76         xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
  77         xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
  78         xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
  79         xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
  80         xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
  81         xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
  82         xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
  83         xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
  84         <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
  85         <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
  86
  87 2015-11-02  Nick Clifton  <nickc@redhat.com>
  88
  89         * rx-decode.opc (rx_decode_opcode): Decode extra NOP
  90         instructions.
  91         * rx-decode.c: Regenerate.
  92
  93 2015-11-02  Nick Clifton  <nickc@redhat.com>
  94
  95         * rx-decode.opc (rx_disp): If the displacement is zero, set the
  96         type to RX_Operand_Zero_Indirect.
  97         * rx-decode.c: Regenerate.
  98         * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
  99
 100 2015-10-28  Yao Qi  <yao.qi@linaro.org>
 101
 102         * aarch64-dis.c (aarch64_decode_insn): Add one argument
 103         noaliases_p.  Update comments.  Pass noaliases_p rather than
 104         no_aliases to aarch64_opcode_decode.
 105         (print_insn_aarch64_word): Pass no_aliases to
 106         aarch64_decode_insn.
 107
 108 2015-10-27  Vinay  <Vinay.G@kpit.com>
 109
 110         PR binutils/19159
 111         * rl78-decode.opc (MOV): Added offset to DE register in index
 112         addressing mode.
 113         * rl78-decode.c: Regenerate.
 114
 115 2015-10-27  Vinay Kumar  <vinay.g@kpit.com>
 116
 117         PR binutils/19158
 118         * rl78-decode.opc: Add 's' print operator to instructions that
 119         access system registers.
 120         * rl78-decode.c: Regenerate.
 121         * rl78-dis.c (print_insn_rl78_common): Decode all system
 122         registers.
 123
 124 2015-10-27  Vinay Kumar  <vinay.g@kpit.com>
 125
 126         PR binutils/19157
 127         * rl78-decode.opc: Add 'a' print operator to mov instructions
 128         using stack pointer plus index addressing.
 129         * rl78-decode.c: Regenerate.
 130
 131 2015-10-14  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 132
 133         * s390-opc.c: Fix comment.
 134         * s390-opc.txt: Change instruction type for troo, trot, trto, and
 135         trtt to RRF_U0RER since the second parameter does not need to be a
 136         register pair.
 137
 138 2015-10-08  Nick Clifton  <nickc@redhat.com>
 139
 140         * arc-dis.c (print_insn_arc): Initiallise insn array.
 141
 142 2015-10-07  Yao Qi  <yao.qi@linaro.org>
 143
 144         * aarch64-dis.c (aarch64_ext_sysins_op): Access field
 145         'name' rather than 'template'.
 146         * aarch64-opc.c (aarch64_print_operand): Likewise.
 147
 148 2015-10-07  Claudiu Zissulescu <claziss@synopsys.com>
 149
 150         * arc-dis.c: Revamped file for ARC support
 151         * arc-dis.h: Likewise.
 152         * arc-ext.c: Likewise.
 153         * arc-ext.h: Likewise.
 154         * arc-opc.c: Likewise.
 155         * arc-fxi.h: New file.
 156         * arc-regs.h: Likewise.
 157         * arc-tbl.h: Likewise.
 158
 159 2015-10-02  Yao Qi  <yao.qi@linaro.org>
 160
 161         * aarch64-dis.c (disas_aarch64_insn): Remove static.  Change
 162         argument insn type to aarch64_insn.  Rename to ...
 163         (aarch64_decode_insn): ... it.
 164         (print_insn_aarch64_word): Caller updated.
 165
 166 2015-10-02  Yao Qi  <yao.qi@linaro.org>
 167
 168         * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
 169         (print_insn_aarch64_word): Caller updated.
 170
 171 2015-09-29  Dominik Vogt  <vogt@linux.vnet.ibm.com>
 172
 173         * s390-mkopc.c (main): Parse htm and vx flag.
 174         * s390-opc.txt: Mark instructions from the hardware transactional
 175         memory and vector facilities with the "htm"/"vx" flag.
 176
 177 2015-09-28  Nick Clifton  <nickc@redhat.com>
 178
 179         * po/de.po: Updated German translation.
 180
 181 2015-09-28  Tom Rix  <tom@bumblecow.com>
 182
 183         * ppc-opc.c (PPC500): Mark some opcodes as invalid
 184
 185 2015-09-23  Nick Clifton  <nickc@redhat.com>
 186
 187         * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
 188         function.
 189         * tic30-dis.c (print_branch): Likewise.
 190         * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
 191         value before left shifting.
 192         * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
 193         * hppa-dis.c (print_insn_hppa): Likewise.
 194         * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
 195         array.
 196         * msp430-dis.c (msp430_singleoperand): Likewise.
 197         (msp430_doubleoperand): Likewise.
 198         (print_insn_msp430): Likewise.
 199         * nds32-asm.c (parse_operand): Likewise.
 200         * sh-opc.h (MASK): Likewise.
 201         * v850-dis.c (get_operand_value): Likewise.
 202
 203 2015-09-22  Nick Clifton  <nickc@redhat.com>
 204
 205         * rx-decode.opc (bwl): Use RX_Bad_Size.
 206         (sbwl): Likewise.
 207         (ubwl): Likewise.  Rename to ubw.
 208         (uBWL): Rename to uBW.
 209         Replace all references to uBWL with uBW.
 210         * rx-decode.c: Regenerate.
 211         * rx-dis.c (size_names): Add entry for RX_Bad_Size.
 212         (opsize_names): Likewise.
 213         (print_insn_rx): Detect and report RX_Bad_Size.
 214
 215 2015-09-22  Anton Blanchard  <anton@samba.org>
 216
 217         * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
 218
 219 2015-08-25  Jose E. Marchesi  <jose.marchesi@oracle.com>
 220
 221         * sparc-dis.c (print_insn_sparc): Handle the privileged register
 222         %pmcdper.
 223
 224 2015-08-24  Jan Stancek  <jstancek@redhat.com>
 225
 226         * i386-dis.c (print_insn): Fix decoding of three byte operands.
 227
 228 2015-08-21  Alexander Fomin  <alexander.fomin@intel.com>
 229
 230         PR binutils/18257
 231         * i386-dis.c: Use MOD_TABLE for most of mask instructions.
 232         (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
 233         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 234         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 235         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 236         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 237         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 238         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 239         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 240         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 241         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 242         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 243         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 244         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 245         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 246         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 247         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 248         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 249         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 250         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 251         MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
 252         MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
 253         MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
 254         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 255         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 256         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 257         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 258         MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 259         MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 260         MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 261         MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
 262         (vex_w_table): Replace terminals with MOD_TABLE entries for
 263         most of mask instructions.
 264
 265 2015-08-17  Alan Modra  <amodra@gmail.com>
 266
 267         * cgen.sh: Trim trailing space from cgen output.
 268         * ia64-gen.c (print_dependency_table): Don't generate trailing space.
 269         (print_dis_table): Likewise.
 270         * opc2c.c (dump_lines): Likewise.
 271         (orig_filename): Warning fix.
 272         * ia64-asmtab.c: Regenerate.
 273
 274 2015-08-13  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 275
 276         * arm-dis.c (print_insn_arm): Disassembling for all targets V6
 277         and higher with ARM instruction set will now mark the 26-bit
 278         versions of teq,tst,cmn and cmp as UNPREDICTABLE.
 279         (arm_opcodes): Fix for unpredictable nop being recognized as a
 280         teq.
 281
 282 2015-08-12  Simon Dardis  <simon.dardis@imgtec.com>
 283
 284         * micromips-opc.c (micromips_opcodes): Re-order table so that move
 285         based on 'or' is first.
 286         * mips-opc.c (mips_builtin_opcodes): Ditto.
 287
 288 2015-08-11  Nick Clifton  <nickc@redhat.com>
 289
 290         PR 18800
 291         * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
 292         instruction.
 293
 294 2015-08-10  Robert Suchanek  <robert.suchanek@imgtec.com>
 295
 296         * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
 297
 298 2015-08-07  Amit Pawar <Amit.Pawar@amd.com>
 299
 300         * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
 301         * i386-init.h: Regenerated.
 302
 303 2015-07-30  H.J. Lu  <hongjiu.lu@intel.com>
 304
 305         PR binutils/13571
 306         * i386-dis.c (MOD_0FC3): New.
 307         (PREFIX_0FC3): Renamed to ...
 308         (PREFIX_MOD_0_0FC3): This.
 309         (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
 310         (prefix_table): Replace Ma with Ev on movntiS.
 311         (mod_table): Add MOD_0FC3.
 312
 313 2015-07-27  H.J. Lu  <hongjiu.lu@intel.com>
 314
 315         * configure: Regenerated.
 316
 317 2015-07-23  Alan Modra  <amodra@gmail.com>
 318
 319         PR 18708
 320         * i386-dis.c (get64): Avoid signed integer overflow.
 321
 322 2015-07-22  Alexander Fomin  <alexander.fomin@intel.com>
 323
 324         PR binutils/18631
 325         * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
 326         "EXEvexHalfBcstXmmq" for the second operand.
 327         (EVEX_W_0F79_P_2): Likewise.
 328         (EVEX_W_0F7A_P_2): Likewise.
 329         (EVEX_W_0F7B_P_2): Likewise.
 330
 331 2015-07-16  Alessandro Marzocchi  <alessandro.marzocchi@gmail.com>
 332
 333         * arm-dis.c (print_insn_coprocessor): Added support for quarter
 334         float bitfield format.
 335         (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
 336         quarter float bitfield format.
 337
 338 2015-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 339
 340         * configure: Regenerated.
 341
 342 2015-07-03  Alan Modra  <amodra@gmail.com>
 343
 344         * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
 345         * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries.  Add
 346         PPC_OPCODE_7450 to 7450 entry.  Add PPC_OPCODE_750 to 750cl entry.
 347
 348 2015-07-01  Sandra Loosemore  <sandra@codesourcery.com>
 349             Cesar Philippidis  <cesar@codesourcery.com>
 350
 351         * nios2-dis.c (nios2_extract_opcode): New.
 352         (nios2_disassembler_state): New.
 353         (nios2_find_opcode_hash): Use mach parameter to select correct
 354         disassembler state.
 355         (nios2_print_insn_arg): Extend to support new R2 argument letters
 356         and formats.
 357         (print_insn_nios2): Check for 16-bit instruction at end of memory.
 358         * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
 359         (NIOS2_NUM_OPCODES): Rename to...
 360         (NIOS2_NUM_R1_OPCODES): This.
 361         (nios2_r2_opcodes): New.
 362         (NIOS2_NUM_R2_OPCODES): New.
 363         (nios2_num_r2_opcodes): New.
 364         (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
 365         (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
 366         (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
 367         (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
 368         (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
 369
 370 2015-06-30  Amit Pawar  <Amit.Pawar@amd.com>
 371
 372         * i386-dis.c (OP_Mwaitx): New.
 373         (rm_table): Add monitorx/mwaitx.
 374         * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
 375         and CPU_ZNVER1_FLAGS.  Add CPU_MWAITX_FLAGS.
 376         (operand_type_init): Add CpuMWAITX.
 377         * i386-opc.h (CpuMWAITX): New.
 378         (i386_cpu_flags): Add cpumwaitx.
 379         * i386-opc.tbl: Add monitorx and mwaitx.
 380         * i386-init.h: Regenerated.
 381         * i386-tbl.h: Likewise.
 382
 383 2015-06-22  Peter Bergner  <bergner@vnet.ibm.com>
 384
 385         * ppc-opc.c (insert_ls): Test for invalid LS operands.
 386         (insert_esync): New function.
 387         (LS, WC): Use insert_ls.
 388         (ESYNC): Use insert_esync.
 389
 390 2015-06-22  Nick Clifton  <nickc@redhat.com>
 391
 392         * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
 393         requested region lies beyond it.
 394         * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
 395         looking for 32-bit insns.
 396         * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
 397         data.
 398         * sh-dis.c (print_insn_sh): Likewise.
 399         * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
 400         blocks of instructions.
 401         * vax-dis.c (print_insn_vax): Check that the requested address
 402         does not clash with the stop_vma.
 403
 404 2015-06-19  Peter Bergner  <bergner@vnet.ibm.com>
 405
 406         * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
 407         * ppc-opc.c (FXM4): Add non-zero optional value.
 408         (TBR): Likewise.
 409         (SXL): Likewise.
 410         (insert_fxm): Handle new default operand value.
 411         (extract_fxm): Likewise.
 412         (insert_tbr): Likewise.
 413         (extract_tbr): Likewise.
 414
 415 2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
 416
 417         * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
 418
 419 2015-06-16  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 420
 421         * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
 422
 423 2015-06-12  Peter Bergner  <bergner@vnet.ibm.com>
 424
 425         * ppc-opc.c: Add comment accidentally removed by old commit.
 426         (MTMSRD_L): Delete.
 427
 428 2015-06-04  Peter Bergner  <bergner@vnet.ibm.com>
 429
 430         * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
 431
 432 2015-06-04  Nick Clifton  <nickc@redhat.com>
 433
 434         PR 18474
 435         * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
 436
 437 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 438
 439         * arm-dis.c (arm_opcodes): Add "setpan".
 440         (thumb_opcodes): Add "setpan".
 441
 442 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 443
 444         * arm-dis.c (select_arm_features): Rework to avoid used of redefined
 445         macros.
 446
 447 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 448
 449         * aarch64-tbl.h (aarch64_feature_rdma): New.
 450         (RDMA): New.
 451         (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
 452         * aarch64-asm-2.c: Regenerate.
 453         * aarch64-dis-2.c: Regenerate.
 454         * aarch64-opc-2.c: Regenerate.
 455
 456 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 457
 458         * aarch64-tbl.h (aarch64_feature_lor): New.
 459         (LOR): New.
 460         (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
 461         "stllrb", "stllrh".
 462         * aarch64-asm-2.c: Regenerate.
 463         * aarch64-dis-2.c: Regenerate.
 464         * aarch64-opc-2.c: Regenerate.
 465
 466 2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
 467
 468         * aarch64-opc.c (F_ARCHEXT): New.
 469         (aarch64_sys_regs): Add "pan".
 470         (aarch64_sys_reg_supported_p): New.
 471         (aarch64_pstatefields): Add "pan".
 472         (aarch64_pstatefield_supported_p): New.
 473
 474 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 475
 476         * i386-tbl.h: Regenerate.
 477
 478 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 479
 480         * i386-dis.c (print_insn): Swap rounding mode specifier and
 481         general purpose register in Intel mode.
 482
 483 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 484
 485         * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
 486         * i386-tbl.h: Regenerate.
 487
 488 2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>
 489
 490         * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
 491         * i386-init.h: Regenerated.
 492
 493 2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>
 494
 495         PR binutis/18386
 496         * i386-dis.c: Add comments for '@'.
 497         (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
 498         (enum x86_64_isa): New.
 499         (isa64): Likewise.
 500         (print_i386_disassembler_options): Add amd64 and intel64.
 501         (print_insn): Handle amd64 and intel64.
 502         (putop): Handle '@'.
 503         (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
 504         * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
 505         * i386-opc.h (AMD64): New.
 506         (CpuIntel64): Likewise.
 507         (i386_cpu_flags): Add cpuamd64 and cpuintel64.
 508         * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
 509         Mark direct call/jmp without Disp16|Disp32 as Intel64.
 510         * i386-init.h: Regenerated.
 511         * i386-tbl.h: Likewise.
 512
 513 2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>
 514
 515         * ppc-opc.c (IH) New define.
 516         (powerpc_opcodes) <wait>: Do not enable for POWER7.
 517         <tlbie>: Add RS operand for POWER7.
 518         <slbia>: Add IH operand for POWER6.
 519
 520 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 521
 522         * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
 523         direct branch.
 524         (jmp): Likewise.
 525         * i386-tbl.h: Regenerated.
 526
 527 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 528
 529         * configure.ac: Support bfd_iamcu_arch.
 530         * disassemble.c (disassembler): Support bfd_iamcu_arch.
 531         * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
 532         CPU_IAMCU_COMPAT_FLAGS.
 533         (cpu_flags): Add CpuIAMCU.
 534         * i386-opc.h (CpuIAMCU): New.
 535         (i386_cpu_flags): Add cpuiamcu.
 536         * configure: Regenerated.
 537         * i386-init.h: Likewise.
 538         * i386-tbl.h: Likewise.
 539
 540 2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>
 541
 542         PR binutis/18386
 543         * i386-dis.c (X86_64_E8): New.
 544         (X86_64_E9): Likewise.
 545         Update comments on 'T', 'U', 'V'.  Add comments for '^'.
 546         (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
 547         (x86_64_table): Add X86_64_E8 and X86_64_E9.
 548         (mod_table): Replace {T|} with ^ on Jcall/Jmp.
 549         (putop): Handle '^'.
 550         (OP_J): Ignore the operand size prefix in 64-bit.  Don't check
 551         REX_W.
 552
 553 2015-04-30  DJ Delorie  <dj@redhat.com>
 554
 555         * disassemble.c (disassembler): Choose suitable disassembler based
 556         on E_ABI.
 557         * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
 558         it to decode mul/div insns.
 559         * rl78-decode.c: Regenerate.
 560         * rl78-dis.c (print_insn_rl78): Rename to...
 561         (print_insn_rl78_common): ...this, take ISA parameter.
 562         (print_insn_rl78): New.
 563         (print_insn_rl78_g10): New.
 564         (print_insn_rl78_g13): New.
 565         (print_insn_rl78_g14): New.
 566         (rl78_get_disassembler): New.
 567
 568 2015-04-29  Nick Clifton  <nickc@redhat.com>
 569
 570         * po/fr.po: Updated French translation.
 571
 572 2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>
 573
 574         * ppc-opc.c (DCBT_EO): New define.
 575         (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
 576         <lharx>: Likewise.
 577         <stbcx.>: Likewise.
 578         <sthcx.>: Likewise.
 579         <waitrsv>: Do not enable for POWER7 and later.
 580         <waitimpl>: Likewise.
 581         <dcbt>: Default to the two operand form of the instruction for all
 582         "old" cpus.  For "new" cpus, use the operand ordering that matches
 583         whether the cpu is server or embedded.
 584         <dcbtst>: Likewise.
 585
 586 2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 587
 588         * s390-opc.c: New instruction type VV0UU2.
 589         * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
 590         and WFC.
 591
 592 2015-04-23  Jan Beulich  <jbeulich@suse.com>
 593
 594         * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
 595         * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
 596         vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
 597         (vfpclasspd, vfpclassps): Add %XZ.
 598
 599 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 600
 601         * i386-dis.c (PREFIX_UD_SHIFT): Removed.
 602         (PREFIX_UD_REPZ): Likewise.
 603         (PREFIX_UD_REPNZ): Likewise.
 604         (PREFIX_UD_DATA): Likewise.
 605         (PREFIX_UD_ADDR): Likewise.
 606         (PREFIX_UD_LOCK): Likewise.
 607
 608 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 609
 610         * i386-dis.c (prefix_requirement): Removed.
 611         (print_insn): Don't set prefix_requirement.  Check
 612         dp->prefix_requirement instead of prefix_requirement.
 613
 614 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 615
 616         PR binutils/17898
 617         * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
 618         (PREFIX_MOD_0_0FC7_REG_6): This.
 619         (PREFIX_MOD_3_0FC7_REG_6): New.
 620         (PREFIX_MOD_3_0FC7_REG_7): Likewise.
 621         (prefix_table): Replace PREFIX_0FC7_REG_6 with
 622         PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
 623         PREFIX_MOD_3_0FC7_REG_7.
 624         (mod_table): Replace PREFIX_0FC7_REG_6 with
 625         PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
 626         PREFIX_MOD_3_0FC7_REG_7.
 627
 628 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 629
 630         * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
 631         (PREFIX_MANDATORY_REPNZ): Likewise.
 632         (PREFIX_MANDATORY_DATA): Likewise.
 633         (PREFIX_MANDATORY_ADDR): Likewise.
 634         (PREFIX_MANDATORY_LOCK): Likewise.
 635         (PREFIX_MANDATORY): Likewise.
 636         (PREFIX_UD_SHIFT): Set to 8
 637         (PREFIX_UD_REPZ): Updated.
 638         (PREFIX_UD_REPNZ): Likewise.
 639         (PREFIX_UD_DATA): Likewise.
 640         (PREFIX_UD_ADDR): Likewise.
 641         (PREFIX_UD_LOCK): Likewise.
 642         (PREFIX_IGNORED_SHIFT): New.
 643         (PREFIX_IGNORED_REPZ): Likewise.
 644         (PREFIX_IGNORED_REPNZ): Likewise.
 645         (PREFIX_IGNORED_DATA): Likewise.
 646         (PREFIX_IGNORED_ADDR): Likewise.
 647         (PREFIX_IGNORED_LOCK): Likewise.
 648         (PREFIX_OPCODE): Likewise.
 649         (PREFIX_IGNORED): Likewise.
 650         (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
 651         (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 652         (three_byte_table): Likewise.
 653         (mod_table): Likewise.
 654         (mandatory_prefix): Renamed to ...
 655         (prefix_requirement): This.
 656         (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 657         Update PREFIX_90 entry.
 658         (get_valid_dis386): Check prefix_requirement to see if a prefix
 659         should be ignored.
 660         (print_insn): Replace mandatory_prefix with prefix_requirement.
 661
 662 2015-04-15  Renlin Li  <renlin.li@arm.com>
 663
 664         * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
 665         use it for ssat and ssat16.
 666         (print_insn_thumb32): Add handle case for 'D' control code.
 667
 668 2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
 669             H.J. Lu  <hongjiu.lu@intel.com>
 670
 671         * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
 672         * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
 673         PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
 674         PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
 675         PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
 676         (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
 677         Fill prefix_requirement field.
 678         (struct dis386): Add prefix_requirement field.
 679         (dis386): Fill prefix_requirement field.
 680         (dis386_twobyte): Ditto.
 681         (twobyte_has_mandatory_prefix_: Remove.
 682         (reg_table): Fill prefix_requirement field.
 683         (prefix_table): Ditto.
 684         (x86_64_table): Ditto.
 685         (three_byte_table): Ditto.
 686         (xop_table): Ditto.
 687         (vex_table): Ditto.
 688         (vex_len_table): Ditto.
 689         (vex_w_table): Ditto.
 690         (mod_table): Ditto.
 691         (bad_opcode): Ditto.
 692         (print_insn): Use prefix_requirement.
 693         (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
 694         FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
 695         (float_reg): Ditto.
 696
 697 2015-03-30  Mike Frysinger  <vapier@gentoo.org>
 698
 699         * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
 700
 701 2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 702
 703         * Makefile.in: Regenerated.
 704
 705 2015-03-25  Anton Blanchard  <anton@samba.org>
 706
 707         * ppc-dis.c (disassemble_init_powerpc): Only initialise
 708         powerpc_opcd_indices and vle_opcd_indices once.
 709
 710 2015-03-25  Anton Blanchard  <anton@samba.org>
 711
 712         * ppc-opc.c (powerpc_opcodes): Add slbfee.
 713
 714 2015-03-24  Terry Guo  <terry.guo@arm.com>
 715
 716         * arm-dis.c (opcode32): Updated to use new arm feature struct.
 717         (opcode16): Likewise.
 718         (coprocessor_opcodes): Replace bit with feature struct.
 719         (neon_opcodes): Likewise.
 720         (arm_opcodes): Likewise.
 721         (thumb_opcodes): Likewise.
 722         (thumb32_opcodes): Likewise.
 723         (print_insn_coprocessor): Likewise.
 724         (print_insn_arm): Likewise.
 725         (select_arm_features): Follow new feature struct.
 726
 727 2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
 728
 729         * i386-dis.c (rm_table): Add clzero.
 730         * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
 731         Add CPU_CLZERO_FLAGS.
 732         (cpu_flags): Add CpuCLZERO.
 733         * i386-opc.h: Add CpuCLZERO.
 734         * i386-opc.tbl: Add clzero.
 735         * i386-init.h: Re-generated.
 736         * i386-tbl.h: Re-generated.
 737
 738 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 739
 740         * mips-opc.c (decode_mips_operand): Fix constraint issues
 741         with u and y operands.
 742
 743 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 744
 745         * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
 746
 747 2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 748
 749         * s390-opc.c: Add new IBM z13 instructions.
 750         * s390-opc.txt: Likewise.
 751
 752 2015-03-10  Renlin Li  <renlin.li@arm.com>
 753
 754         * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
 755         stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
 756         related alias.
 757         * aarch64-asm-2.c: Regenerate.
 758         * aarch64-dis-2.c: Likewise.
 759         * aarch64-opc-2.c: Likewise.
 760
 761 2015-03-03  Jiong Wang  <jiong.wang@arm.com>
 762
 763         * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
 764
 765 2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>
 766
 767         * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
 768         arch_sh_up.
 769         (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
 770         arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
 771
 772 2015-02-23  Vinay  <Vinay.G@kpit.com>
 773
 774         * rl78-decode.opc (MOV): Added space between two operands for
 775         'mov' instruction in index addressing mode.
 776         * rl78-decode.c: Regenerate.
 777
 778 2015-02-19  Pedro Alves  <palves@redhat.com>
 779
 780         * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
 781
 782 2015-02-10  Pedro Alves  <palves@redhat.com>
 783             Tom Tromey  <tromey@redhat.com>
 784
 785         * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
 786         microblaze_and, microblaze_xor.
 787         * microblaze-opc.h (opcodes): Adjust.
 788
 789 2015-01-28  James Bowman  <james.bowman@ftdichip.com>
 790
 791         * Makefile.am: Add FT32 files.
 792         * configure.ac: Handle FT32.
 793         * disassemble.c (disassembler): Call print_insn_ft32.
 794         * ft32-dis.c: New file.
 795         * ft32-opc.c: New file.
 796         * Makefile.in: Regenerate.
 797         * configure: Regenerate.
 798         * po/POTFILES.in: Regenerate.
 799
 800 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
 801
 802         * nds32-asm.c (keyword_sr): Add new system registers.
 803
 804 2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 805
 806         * s390-dis.c (s390_extract_operand): Support vector register
 807         operands.
 808         (s390_print_insn_with_opcode): Support new operands types and add
 809         new handling of optional operands.
 810         * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
 811         and include opcode/s390.h instead.
 812         (struct op_struct): New field `flags'.
 813         (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
 814         (dumpTable): Dump flags.
 815         (main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
 816         string.
 817         * s390-opc.c: Add new operands types, instruction formats, and
 818         instruction masks.
 819         (s390_opformats): Add new formats for .insn.
 820         * s390-opc.txt: Add new instructions.
 821
 822 2015-01-01  Alan Modra  <amodra@gmail.com>
 823
 824         Update year range in copyright notice of all files.
 825
 826 For older changes see ChangeLog-2014
 827 \f
 828 Copyright (C) 2015 Free Software Foundation, Inc.
 829
 830 Copying and distribution of this file, with or without modification,
 831 are permitted in any medium without royalty provided the copyright
 832 notice and this notice are preserved.
 833
 834 Local Variables:
 835 mode: change-log
 836 left-margin: 8
 837 fill-column: 74
 838 version-control: never
 839 End: