opcodes/ChangeLog

   1 2020-05-11  Alan Modra  <amodra@gmail.com>
   2
   3         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
   4         (XTP, DQXP, DQXP_MASK): Define.
   5         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
   6         (prefix_opcodes): Add plxvp and pstxvp.
   7
   8 2020-05-11  Alan Modra  <amodra@gmail.com>
   9
  10         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
  11         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
  12         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
  13
  14 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
  15
  16         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
  17
  18 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
  19
  20         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
  21         (L1OPT): Define.
  22         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
  23
  24 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
  25
  26         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
  27
  28 2020-05-11  Alan Modra  <amodra@gmail.com>
  29
  30         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
  31
  32 2020-05-11  Alan Modra  <amodra@gmail.com>
  33
  34         * ppc-dis.c (ppc_opts): Add "power10" entry.
  35         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
  36         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
  37
  38 2020-05-11  Nick Clifton  <nickc@redhat.com>
  39
  40         * po/fr.po: Updated French translation.
  41
  42 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
  43
  44         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
  45         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
  46         (operand_general_constraint_met_p): validate
  47         AARCH64_OPND_UNDEFINED.
  48         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
  49         for FLD_imm16_2.
  50         * aarch64-asm-2.c: Regenerated.
  51         * aarch64-dis-2.c: Regenerated.
  52         * aarch64-opc-2.c: Regenerated.
  53
  54 2020-04-29  Nick Clifton  <nickc@redhat.com>
  55
  56         PR 22699
  57         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
  58         and SETRC insns.
  59
  60 2020-04-29  Nick Clifton  <nickc@redhat.com>
  61
  62         * po/sv.po: Updated Swedish translation.
  63
  64 2020-04-29  Nick Clifton  <nickc@redhat.com>
  65
  66         PR 22699
  67         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
  68         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
  69         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
  70         IMM0_8U case.
  71
  72 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
  73
  74         PR 25848
  75         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
  76         cmpi only on m68020up and cpu32.
  77
  78 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
  79
  80         * aarch64-asm.c (aarch64_ins_none): New.
  81         * aarch64-asm.h (ins_none): New declaration.
  82         * aarch64-dis.c (aarch64_ext_none): New.
  83         * aarch64-dis.h (ext_none): New declaration.
  84         * aarch64-opc.c (aarch64_print_operand): Update case for
  85         AARCH64_OPND_BARRIER_PSB.
  86         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
  87         (AARCH64_OPERANDS): Update inserter/extracter for
  88         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
  89         * aarch64-asm-2.c: Regenerated.
  90         * aarch64-dis-2.c: Regenerated.
  91         * aarch64-opc-2.c: Regenerated.
  92
  93 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
  94
  95         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
  96         (aarch64_feature_ras, RAS): Likewise.
  97         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
  98         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
  99         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
 100         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
 101         * aarch64-asm-2.c: Regenerated.
 102         * aarch64-dis-2.c: Regenerated.
 103         * aarch64-opc-2.c: Regenerated.
 104
 105 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
 106
 107         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
 108         (print_insn_neon): Support disassembly of conditional
 109         instructions.
 110
 111 2020-02-16  David Faust  <david.faust@oracle.com>
 112
 113         * bpf-desc.c: Regenerate.
 114         * bpf-desc.h: Likewise.
 115         * bpf-opc.c: Regenerate.
 116         * bpf-opc.h: Likewise.
 117
 118 2020-04-07  Lili Cui  <lili.cui@intel.com>
 119
 120         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
 121         (prefix_table): New instructions (see prefixes above).
 122         (rm_table): Likewise
 123         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
 124         CPU_ANY_TSXLDTRK_FLAGS.
 125         (cpu_flags): Add CpuTSXLDTRK.
 126         * i386-opc.h (enum): Add CpuTSXLDTRK.
 127         (i386_cpu_flags): Add cputsxldtrk.
 128         * i386-opc.tbl: Add XSUSPLDTRK insns.
 129         * i386-init.h: Regenerate.
 130         * i386-tbl.h: Likewise.
 131
 132 2020-04-02  Lili Cui  <lili.cui@intel.com>
 133
 134         * i386-dis.c (prefix_table): New instructions serialize.
 135         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
 136         CPU_ANY_SERIALIZE_FLAGS.
 137         (cpu_flags): Add CpuSERIALIZE.
 138         * i386-opc.h (enum): Add CpuSERIALIZE.
 139         (i386_cpu_flags): Add cpuserialize.
 140         * i386-opc.tbl: Add SERIALIZE insns.
 141         * i386-init.h: Regenerate.
 142         * i386-tbl.h: Likewise.
 143
 144 2020-03-26  Alan Modra  <amodra@gmail.com>
 145
 146         * disassemble.h (opcodes_assert): Declare.
 147         (OPCODES_ASSERT): Define.
 148         * disassemble.c: Don't include assert.h.  Include opintl.h.
 149         (opcodes_assert): New function.
 150         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 151         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 152         calculate maxlen.  Omit insn decoding when insn length exceeds
 153         maxlen.  Exit from nibble loop when looking for E, before
 154         accessing next data byte.  Move processing of E outside loop.
 155         Replace tests of maxlen in loop with assertions.
 156
 157 2020-03-26  Alan Modra  <amodra@gmail.com>
 158
 159         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 160
 161 2020-03-25  Alan Modra  <amodra@gmail.com>
 162
 163         * z80-dis.c (suffix): Init mybuf.
 164
 165 2020-03-22  Alan Modra  <amodra@gmail.com>
 166
 167         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 168         successflly read from section.
 169
 170 2020-03-22  Alan Modra  <amodra@gmail.com>
 171
 172         * arc-dis.c (find_format): Use ISO C string concatenation rather
 173         than line continuation within a string.  Don't access needs_limm
 174         before testing opcode != NULL.
 175
 176 2020-03-22  Alan Modra  <amodra@gmail.com>
 177
 178         * ns32k-dis.c (print_insn_arg): Update comment.
 179         (print_insn_ns32k): Reduce size of index_offset array, and
 180         initialize, passing -1 to print_insn_arg for args that are not
 181         an index.  Don't exit arg loop early.  Abort on bad arg number.
 182
 183 2020-03-22  Alan Modra  <amodra@gmail.com>
 184
 185         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 186         * s12z-opc.c: Formatting.
 187         (operands_f): Return an int.
 188         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 189         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 190         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 191         (exg_sex_discrim): Likewise.
 192         (create_immediate_operand, create_bitfield_operand),
 193         (create_register_operand_with_size, create_register_all_operand),
 194         (create_register_all16_operand, create_simple_memory_operand),
 195         (create_memory_operand, create_memory_auto_operand): Don't
 196         segfault on malloc failure.
 197         (z_ext24_decode): Return an int status, negative on fail, zero
 198         on success.
 199         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 200         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 201         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 202         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 203         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 204         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 205         (loop_primitive_decode, shift_decode, psh_pul_decode),
 206         (bit_field_decode): Similarly.
 207         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 208         to return value, update callers.
 209         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 210         Don't segfault on NULL operand.
 211         (decode_operation): Return OP_INVALID on first fail.
 212         (decode_s12z): Check all reads, returning -1 on fail.
 213
 214 2020-03-20  Alan Modra  <amodra@gmail.com>
 215
 216         * metag-dis.c (print_insn_metag): Don't ignore status from
 217         read_memory_func.
 218
 219 2020-03-20  Alan Modra  <amodra@gmail.com>
 220
 221         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 222         Initialize parts of buffer not written when handling a possible
 223         2-byte insn at end of section.  Don't attempt decoding of such
 224         an insn by the 4-byte machinery.
 225
 226 2020-03-20  Alan Modra  <amodra@gmail.com>
 227
 228         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 229         partially filled buffer.  Prevent lookup of 4-byte insns when
 230         only VLE 2-byte insns are possible due to section size.  Print
 231         ".word" rather than ".long" for 2-byte leftovers.
 232
 233 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 234
 235         PR 25641
 236         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 237
 238 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 239
 240         * i386-dis.c (X86_64_0D): Rename to ...
 241         (X86_64_0E): ... this.
 242
 243 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 244
 245         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 246         * Makefile.in: Regenerated.
 247
 248 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 249
 250         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 251         3-operand pseudos.
 252         * i386-tbl.h: Re-generate.
 253
 254 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 255
 256         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 257         vprot*, vpsha*, and vpshl*.
 258         * i386-tbl.h: Re-generate.
 259
 260 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 261
 262         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 263         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 264         * i386-tbl.h: Re-generate.
 265
 266 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 267
 268         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 269         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 270         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 271         * i386-tbl.h: Re-generate.
 272
 273 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 274
 275         * i386-gen.c (struct template_arg, struct template_instance,
 276         struct template_param, struct template, templates,
 277         parse_template, expand_templates): New.
 278         (process_i386_opcodes): Various local variables moved to
 279         expand_templates. Call parse_template and expand_templates.
 280         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 281         * i386-tbl.h: Re-generate.
 282
 283 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 284
 285         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 286         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 287         register and memory source templates. Replace VexW= by VexW*
 288         where applicable.
 289         * i386-tbl.h: Re-generate.
 290
 291 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 292
 293         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 294         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 295         * i386-tbl.h: Re-generate.
 296
 297 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 298
 299         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 300         * i386-tbl.h: Re-generate.
 301
 302 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 303
 304         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 305         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 306         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 307         VexW0 on SSE2AVX variants.
 308         (vmovq): Drop NoRex64 from XMM/XMM variants.
 309         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 310         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 311         applicable use VexW0.
 312         * i386-tbl.h: Re-generate.
 313
 314 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 315
 316         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 317         * i386-opc.h (Rex64): Delete.
 318         (struct i386_opcode_modifier): Remove rex64 field.
 319         * i386-opc.tbl (crc32): Drop Rex64.
 320         Replace Rex64 with Size64 everywhere else.
 321         * i386-tbl.h: Re-generate.
 322
 323 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 324
 325         * i386-dis.c (OP_E_memory): Exclude recording of used address
 326         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 327         addressed memory operands for MPX insns.
 328
 329 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 330
 331         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 332         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 333         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 334         (ptwrite): Split into non-64-bit and 64-bit forms.
 335         * i386-tbl.h: Re-generate.
 336
 337 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 338
 339         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 340         template.
 341         * i386-tbl.h: Re-generate.
 342
 343 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 344
 345         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 346         (prefix_table): Move vmmcall here. Add vmgexit.
 347         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 348         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 349         (cpu_flags): Add CpuSEV_ES entry.
 350         * i386-opc.h (CpuSEV_ES): New.
 351         (union i386_cpu_flags): Add cpusev_es field.
 352         * i386-opc.tbl (vmgexit): New.
 353         * i386-init.h, i386-tbl.h: Re-generate.
 354
 355 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 356
 357         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 358         with MnemonicSize.
 359         * i386-opc.h (IGNORESIZE): New.
 360         (DEFAULTSIZE): Likewise.
 361         (IgnoreSize): Removed.
 362         (DefaultSize): Likewise.
 363         (MnemonicSize): New.
 364         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 365         mnemonicsize.
 366         * i386-opc.tbl (IgnoreSize): New.
 367         (DefaultSize): Likewise.
 368         * i386-tbl.h: Regenerated.
 369
 370 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 371
 372         PR 25627
 373         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 374         instructions.
 375
 376 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 377
 378         PR gas/25622
 379         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 380         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 381         * i386-tbl.h: Regenerated.
 382
 383 2020-02-26  Alan Modra  <amodra@gmail.com>
 384
 385         * aarch64-asm.c: Indent labels correctly.
 386         * aarch64-dis.c: Likewise.
 387         * aarch64-gen.c: Likewise.
 388         * aarch64-opc.c: Likewise.
 389         * alpha-dis.c: Likewise.
 390         * i386-dis.c: Likewise.
 391         * nds32-asm.c: Likewise.
 392         * nfp-dis.c: Likewise.
 393         * visium-dis.c: Likewise.
 394
 395 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 396
 397         * arc-regs.h (int_vector_base): Make it available for all ARC
 398         CPUs.
 399
 400 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 401
 402         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 403         changed.
 404
 405 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 406
 407         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 408         c.mv/c.li if rs1 is zero.
 409
 410 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 411
 412         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 413         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 414         CPU_POPCNT_FLAGS.
 415         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 416         * i386-opc.h (CpuABM): Removed.
 417         (CpuPOPCNT): New.
 418         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 419         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 420         popcnt.  Remove CpuABM from lzcnt.
 421         * i386-init.h: Regenerated.
 422         * i386-tbl.h: Likewise.
 423
 424 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 425
 426         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 427         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 428         VexW1 instead of open-coding them.
 429         * i386-tbl.h: Re-generate.
 430
 431 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 432
 433         * i386-opc.tbl (AddrPrefixOpReg): Define.
 434         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 435         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 436         templates. Drop NoRex64.
 437         * i386-tbl.h: Re-generate.
 438
 439 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 440
 441         PR gas/6518
 442         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 443         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 444         into Intel syntax instance (with Unpsecified) and AT&T one
 445         (without).
 446         (vcvtneps2bf16): Likewise, along with folding the two so far
 447         separate ones.
 448         * i386-tbl.h: Re-generate.
 449
 450 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 451
 452         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 453         CPU_ANY_SSE4A_FLAGS.
 454
 455 2020-02-17  Alan Modra  <amodra@gmail.com>
 456
 457         * i386-gen.c (cpu_flag_init): Correct last change.
 458
 459 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 460
 461         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 462         CPU_ANY_SSE4_FLAGS.
 463
 464 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 465
 466         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 467         (movzx): Likewise.
 468
 469 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 470
 471         PR gas/25438
 472         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 473         destination for Cpu64-only variant.
 474         (movzx): Fold patterns.
 475         * i386-tbl.h: Re-generate.
 476
 477 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 478
 479         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 480         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 481         CPU_ANY_SSE4_FLAGS entry.
 482         * i386-init.h: Re-generate.
 483
 484 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 485
 486         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 487         with Unspecified, making the present one AT&T syntax only.
 488         * i386-tbl.h: Re-generate.
 489
 490 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 491
 492         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 493         * i386-tbl.h: Re-generate.
 494
 495 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 496
 497         PR gas/24546
 498         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 499         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 500         Amd64 and Intel64 templates.
 501         (call, jmp): Likewise for far indirect variants. Dro
 502         Unspecified.
 503         * i386-tbl.h: Re-generate.
 504
 505 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 506
 507         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 508         * i386-opc.h (ShortForm): Delete.
 509         (struct i386_opcode_modifier): Remove shortform field.
 510         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 511         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 512         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 513         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 514         Drop ShortForm.
 515         * i386-tbl.h: Re-generate.
 516
 517 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 518
 519         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 520         fucompi): Drop ShortForm from operand-less templates.
 521         * i386-tbl.h: Re-generate.
 522
 523 2020-02-11  Alan Modra  <amodra@gmail.com>
 524
 525         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 526         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 527         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 528         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 529         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 530
 531 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 532
 533         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 534         (cde_opcodes): Add VCX* instructions.
 535
 536 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 537             Matthew Malcomson  <matthew.malcomson@arm.com>
 538
 539         * arm-dis.c (struct cdeopcode32): New.
 540         (CDE_OPCODE): New macro.
 541         (cde_opcodes): New disassembly table.
 542         (regnames): New option to table.
 543         (cde_coprocs): New global variable.
 544         (print_insn_cde): New
 545         (print_insn_thumb32): Use print_insn_cde.
 546         (parse_arm_disassembler_options): Parse coprocN args.
 547
 548 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 549
 550         PR gas/25516
 551         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 552         with ISA64.
 553         * i386-opc.h (AMD64): Removed.
 554         (Intel64): Likewose.
 555         (AMD64): New.
 556         (INTEL64): Likewise.
 557         (INTEL64ONLY): Likewise.
 558         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 559         * i386-opc.tbl (Amd64): New.
 560         (Intel64): Likewise.
 561         (Intel64Only): Likewise.
 562         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 563         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 564         * i386-tbl.h: Regenerated.
 565
 566 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 567
 568         PR 25469
 569         * z80-dis.c: Add support for GBZ80 opcodes.
 570
 571 2020-02-04  Alan Modra  <amodra@gmail.com>
 572
 573         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 574
 575 2020-02-03  Alan Modra  <amodra@gmail.com>
 576
 577         * m32c-ibld.c: Regenerate.
 578
 579 2020-02-01  Alan Modra  <amodra@gmail.com>
 580
 581         * frv-ibld.c: Regenerate.
 582
 583 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 584
 585         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 586         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 587         (OP_E_memory): Replace xmm_mdq_mode case label by
 588         vex_scalar_w_dq_mode one.
 589         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 590
 591 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 592
 593         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 594         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 595         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 596         (intel_operand_size): Drop vex_w_dq_mode case label.
 597
 598 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 599
 600         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 601         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 602
 603 2020-01-30  Alan Modra  <amodra@gmail.com>
 604
 605         * m32c-ibld.c: Regenerate.
 606
 607 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 608
 609         * bpf-opc.c: Regenerate.
 610
 611 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 612
 613         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 614         (dis386): Use them to replace C2/C3 table entries.
 615         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 616         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 617         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 618         * i386-tbl.h: Re-generate.
 619
 620 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 621
 622         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 623         forms.
 624         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 625         DefaultSize.
 626         * i386-tbl.h: Re-generate.
 627
 628 2020-01-30  Alan Modra  <amodra@gmail.com>
 629
 630         * tic4x-dis.c (tic4x_dp): Make unsigned.
 631
 632 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 633             Jan Beulich  <jbeulich@suse.com>
 634
 635         PR binutils/25445
 636         * i386-dis.c (MOVSXD_Fixup): New function.
 637         (movsxd_mode): New enum.
 638         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 639         (intel_operand_size): Handle movsxd_mode.
 640         (OP_E_register): Likewise.
 641         (OP_G): Likewise.
 642         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 643         register on movsxd.  Add movsxd with 16-bit destination register
 644         for AMD64 and Intel64 ISAs.
 645         * i386-tbl.h: Regenerated.
 646
 647 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 648
 649         PR 25403
 650         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 651         * aarch64-asm-2.c: Regenerate
 652         * aarch64-dis-2.c: Likewise.
 653         * aarch64-opc-2.c: Likewise.
 654
 655 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 656
 657         * i386-opc.tbl (sysret): Drop DefaultSize.
 658         * i386-tbl.h: Re-generate.
 659
 660 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 661
 662         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 663         Dword.
 664         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 665         * i386-tbl.h: Re-generate.
 666
 667 2020-01-20  Nick Clifton  <nickc@redhat.com>
 668
 669         * po/de.po: Updated German translation.
 670         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 671         * po/uk.po: Updated Ukranian translation.
 672
 673 2020-01-20  Alan Modra  <amodra@gmail.com>
 674
 675         * hppa-dis.c (fput_const): Remove useless cast.
 676
 677 2020-01-20  Alan Modra  <amodra@gmail.com>
 678
 679         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 680
 681 2020-01-18  Nick Clifton  <nickc@redhat.com>
 682
 683         * configure: Regenerate.
 684         * po/opcodes.pot: Regenerate.
 685
 686 2020-01-18  Nick Clifton  <nickc@redhat.com>
 687
 688         Binutils 2.34 branch created.
 689
 690 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 691
 692         * opintl.h: Fix spelling error (seperate).
 693
 694 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 695
 696         * i386-opc.tbl: Add {vex} pseudo prefix.
 697         * i386-tbl.h: Regenerated.
 698
 699 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 700
 701         PR 25376
 702         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 703         (neon_opcodes): Likewise.
 704         (select_arm_features): Make sure we enable MVE bits when selecting
 705         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 706         any architecture.
 707
 708 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 709
 710         * i386-opc.tbl: Drop stale comment from XOP section.
 711
 712 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 713
 714         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 715         (extractps): Add VexWIG to SSE2AVX forms.
 716         * i386-tbl.h: Re-generate.
 717
 718 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 719
 720         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 721         Size64 from and use VexW1 on SSE2AVX forms.
 722         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 723         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 724         * i386-tbl.h: Re-generate.
 725
 726 2020-01-15  Alan Modra  <amodra@gmail.com>
 727
 728         * tic4x-dis.c (tic4x_version): Make unsigned long.
 729         (optab, optab_special, registernames): New file scope vars.
 730         (tic4x_print_register): Set up registernames rather than
 731         malloc'd registertable.
 732         (tic4x_disassemble): Delete optable and optable_special.  Use
 733         optab and optab_special instead.  Throw away old optab,
 734         optab_special and registernames when info->mach changes.
 735
 736 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 737
 738         PR 25377
 739         * z80-dis.c (suffix): Use .db instruction to generate double
 740         prefix.
 741
 742 2020-01-14  Alan Modra  <amodra@gmail.com>
 743
 744         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 745         values to unsigned before shifting.
 746
 747 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 748
 749         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 750         flow instructions.
 751         (print_insn_thumb16, print_insn_thumb32): Likewise.
 752         (print_insn): Initialize the insn info.
 753         * i386-dis.c (print_insn): Initialize the insn info fields, and
 754         detect jumps.
 755
 756 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 757
 758         * arc-opc.c (C_NE): Make it required.
 759
 760 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 761
 762         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 763         reserved register name.
 764
 765 2020-01-13  Alan Modra  <amodra@gmail.com>
 766
 767         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 768         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 769
 770 2020-01-13  Alan Modra  <amodra@gmail.com>
 771
 772         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 773         result of wasm_read_leb128 in a uint64_t and check that bits
 774         are not lost when copying to other locals.  Use uint32_t for
 775         most locals.  Use PRId64 when printing int64_t.
 776
 777 2020-01-13  Alan Modra  <amodra@gmail.com>
 778
 779         * score-dis.c: Formatting.
 780         * score7-dis.c: Formatting.
 781
 782 2020-01-13  Alan Modra  <amodra@gmail.com>
 783
 784         * score-dis.c (print_insn_score48): Use unsigned variables for
 785         unsigned values.  Don't left shift negative values.
 786         (print_insn_score32): Likewise.
 787         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 788
 789 2020-01-13  Alan Modra  <amodra@gmail.com>
 790
 791         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 792
 793 2020-01-13  Alan Modra  <amodra@gmail.com>
 794
 795         * fr30-ibld.c: Regenerate.
 796
 797 2020-01-13  Alan Modra  <amodra@gmail.com>
 798
 799         * xgate-dis.c (print_insn): Don't left shift signed value.
 800         (ripBits): Formatting, use 1u.
 801
 802 2020-01-10  Alan Modra  <amodra@gmail.com>
 803
 804         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 805         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 806
 807 2020-01-10  Alan Modra  <amodra@gmail.com>
 808
 809         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 810         and XRREG value earlier to avoid a shift with negative exponent.
 811         * m10200-dis.c (disassemble): Similarly.
 812
 813 2020-01-09  Nick Clifton  <nickc@redhat.com>
 814
 815         PR 25224
 816         * z80-dis.c (ld_ii_ii): Use correct cast.
 817
 818 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 819
 820         PR 25224
 821         * z80-dis.c (ld_ii_ii): Use character constant when checking
 822         opcode byte value.
 823
 824 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 825
 826         * i386-dis.c (SEP_Fixup): New.
 827         (SEP): Define.
 828         (dis386_twobyte): Use it for sysenter/sysexit.
 829         (enum x86_64_isa): Change amd64 enumerator to value 1.
 830         (OP_J): Compare isa64 against intel64 instead of amd64.
 831         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 832         forms.
 833         * i386-tbl.h: Re-generate.
 834
 835 2020-01-08  Alan Modra  <amodra@gmail.com>
 836
 837         * z8k-dis.c: Include libiberty.h
 838         (instr_data_s): Make max_fetched unsigned.
 839         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 840         Don't exceed byte_info bounds.
 841         (output_instr): Make num_bytes unsigned.
 842         (unpack_instr): Likewise for nibl_count and loop.
 843         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 844         idx unsigned.
 845         * z8k-opc.h: Regenerate.
 846
 847 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 848
 849         * arc-tbl.h (llock): Use 'LLOCK' as class.
 850         (llockd): Likewise.
 851         (scond): Use 'SCOND' as class.
 852         (scondd): Likewise.
 853         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 854         (scondd): Likewise.
 855
 856 2020-01-06  Alan Modra  <amodra@gmail.com>
 857
 858         * m32c-ibld.c: Regenerate.
 859
 860 2020-01-06  Alan Modra  <amodra@gmail.com>
 861
 862         PR 25344
 863         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 864         Peek at next byte to prevent recursion on repeated prefix bytes.
 865         Ensure uninitialised "mybuf" is not accessed.
 866         (print_insn_z80): Don't zero n_fetch and n_used here,..
 867         (print_insn_z80_buf): ..do it here instead.
 868
 869 2020-01-04  Alan Modra  <amodra@gmail.com>
 870
 871         * m32r-ibld.c: Regenerate.
 872
 873 2020-01-04  Alan Modra  <amodra@gmail.com>
 874
 875         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 876
 877 2020-01-04  Alan Modra  <amodra@gmail.com>
 878
 879         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 880
 881 2020-01-04  Alan Modra  <amodra@gmail.com>
 882
 883         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 884
 885 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 886
 887         * aarch64-tbl.h (aarch64_opcode_table): Use
 888         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 889
 890 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 891
 892         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 893         forms of SUDOT and USDOT.
 894
 895 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 896
 897         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 898         uzip{1,2}.
 899         * opcodes/aarch64-dis-2.c: Re-generate.
 900
 901 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 902
 903         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 904         FMMLA encoding.
 905         * opcodes/aarch64-dis-2.c: Re-generate.
 906
 907 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 908
 909         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 910
 911 2020-01-01  Alan Modra  <amodra@gmail.com>
 912
 913         Update year range in copyright notice of all files.
 914
 915 For older changes see ChangeLog-2019
 916 \f
 917 Copyright (C) 2020 Free Software Foundation, Inc.
 918
 919 Copying and distribution of this file, with or without modification,
 920 are permitted in any medium without royalty provided the copyright
 921 notice and this notice are preserved.
 922
 923 Local Variables:
 924 mode: change-log
 925 left-margin: 8
 926 fill-column: 74
 927 version-control: never
 928 End: