x86: infer operand count of templates
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
1 2021-03-03 Jan Beulich <jbeulich@suse.com>
2
3 * i386-gen.c (output_i386_opcode): Don't get operand count. Look
4 for {} instead of {0}. Don't look for '0'.
5 * i386-opc.tbl: Drop operand count field. Drop redundant operand
6 size specifiers.
7
8 2021-02-19 Nelson Chu <nelson.chu@sifive.com>
9
10 PR 27158
11 * riscv-dis.c (print_insn_args): Updated encoding macros.
12 * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
13 (match_c_addi16sp): Updated encoding macros.
14 (match_c_lui): Likewise.
15 (match_c_lui_with_hint): Likewise.
16 (match_c_addi4spn): Likewise.
17 (match_c_slli): Likewise.
18 (match_slli_as_c_slli): Likewise.
19 (match_c_slli64): Likewise.
20 (match_srxi_as_c_srxi): Likewise.
21 (riscv_insn_types): Added .insn css/cl/cs.
22
23 2021-02-18 Nelson Chu <nelson.chu@sifive.com>
24
25 * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
26 (default_priv_spec): Updated type to riscv_spec_class.
27 (parse_riscv_dis_option): Updated.
28 * riscv-opc.c: Moved stuff and make the file tidy.
29
30 2021-02-17 Alan Modra <amodra@gmail.com>
31
32 * wasm32-dis.c: Include limits.h.
33 (CHAR_BIT): Provide backup define.
34 (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
35 Correct signed overflow checking.
36
37 2021-02-16 Jan Beulich <jbeulich@suse.com>
38
39 * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
40 * i386-tbl.h: Re-generate.
41
42 2021-02-16 Jan Beulich <jbeulich@suse.com>
43
44 * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
45 Oword.
46 * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
47
48 2021-02-15 Andreas Krebbel <krebbel@linux.ibm.com>
49
50 * s390-mkopc.c (main): Accept arch14 as cpu string.
51 * s390-opc.txt: Add new arch14 instructions.
52
53 2021-02-04 Nick Alcock <nick.alcock@oracle.com>
54
55 * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
56 favour of LIBINTL.
57 * configure: Regenerated.
58
59 2021-02-08 Mike Frysinger <vapier@gentoo.org>
60
61 * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
62 * tic54x-opc.c (regs): Rename to ...
63 (tic54x_regs): ... this.
64 (mmregs): Rename to ...
65 (tic54x_mmregs): ... this.
66 (condition_codes): Rename to ...
67 (tic54x_condition_codes): ... this.
68 (cc2_codes): Rename to ...
69 (tic54x_cc2_codes): ... this.
70 (cc3_codes): Rename to ...
71 (tic54x_cc3_codes): ... this.
72 (status_bits): Rename to ...
73 (tic54x_status_bits): ... this.
74 (misc_symbols): Rename to ...
75 (tic54x_misc_symbols): ... this.
76
77 2021-02-04 Nelson Chu <nelson.chu@sifive.com>
78
79 * riscv-opc.c (MASK_RVB_IMM): Removed.
80 (riscv_opcodes): Removed zb* instructions.
81 (riscv_ext_version_table): Removed versions for zb*.
82
83 2021-01-26 Alan Modra <amodra@gmail.com>
84
85 * i386-gen.c (parse_template): Ensure entire template_instance
86 is initialised.
87
88 2021-01-15 Nelson Chu <nelson.chu@sifive.com>
89
90 * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
91 (riscv_fpr_names_abi): Likewise.
92 (riscv_opcodes): Likewise.
93 (riscv_insn_types): Likewise.
94
95 2021-01-15 Nelson Chu <nelson.chu@sifive.com>
96
97 * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
98
99 2021-01-15 Nelson Chu <nelson.chu@sifive.com>
100
101 * riscv-dis.c: Comments tidy and improvement.
102 * riscv-opc.c: Likewise.
103
104 2021-01-13 Alan Modra <amodra@gmail.com>
105
106 * Makefile.in: Regenerate.
107
108 2021-01-12 H.J. Lu <hongjiu.lu@intel.com>
109
110 PR binutils/26792
111 * configure.ac: Use GNU_MAKE_JOBSERVER.
112 * aclocal.m4: Regenerated.
113 * configure: Likewise.
114
115 2021-01-12 Nick Clifton <nickc@redhat.com>
116
117 * po/sr.po: Updated Serbian translation.
118
119 2021-01-11 H.J. Lu <hongjiu.lu@intel.com>
120
121 PR ld/27173
122 * configure: Regenerated.
123
124 2021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
125
126 * aarch64-asm-2.c: Regenerate.
127 * aarch64-dis-2.c: Likewise.
128 * aarch64-opc-2.c: Likewise.
129 * aarch64-opc.c (aarch64_print_operand):
130 Delete handling of AARCH64_OPND_CSRE_CSR.
131 * aarch64-tbl.h (aarch64_feature_csre): Delete.
132 (CSRE): Likewise.
133 (_CSRE_INSN): Likewise.
134 (aarch64_opcode_table): Delete csr.
135
136 2021-01-11 Nick Clifton <nickc@redhat.com>
137
138 * po/de.po: Updated German translation.
139 * po/fr.po: Updated French translation.
140 * po/pt_BR.po: Updated Brazilian Portuguese translation.
141 * po/sv.po: Updated Swedish translation.
142 * po/uk.po: Updated Ukranian translation.
143
144 2021-01-09 H.J. Lu <hongjiu.lu@intel.com>
145
146 * configure: Regenerated.
147
148 2021-01-09 Nick Clifton <nickc@redhat.com>
149
150 * configure: Regenerate.
151 * po/opcodes.pot: Regenerate.
152
153 2021-01-09 Nick Clifton <nickc@redhat.com>
154
155 * 2.36 release branch crated.
156
157 2021-01-08 Peter Bergner <bergner@linux.ibm.com>
158
159 * ppc-opc.c (insert_dw, (extract_dw): New functions.
160 (DW, (XRC_MASK): Define.
161 (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
162
163 2021-01-09 Alan Modra <amodra@gmail.com>
164
165 * configure: Regenerate.
166
167 2021-01-08 Nick Clifton <nickc@redhat.com>
168
169 * po/sv.po: Updated Swedish translation.
170
171 2021-01-08 Nick Clifton <nickc@redhat.com>
172
173 PR 27129
174 * aarch64-dis.c (determine_disassembling_preference): Move call to
175 aarch64_match_operands_constraint outside of the assertion.
176 * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
177 Replace with a return of FALSE.
178
179 PR 27139
180 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
181 core system register.
182
183 2021-01-07 Samuel Thibault <samuel.thibault@gnu.org>
184
185 * configure: Regenerate.
186
187 2021-01-07 Nick Clifton <nickc@redhat.com>
188
189 * po/fr.po: Updated French translation.
190
191 2021-01-07 Fredrik Noring <noring@nocrew.org>
192
193 * m68k-opc.c (chkl): Change minimum architecture requirement to
194 m68020.
195
196 2021-01-07 Philipp Tomsich <prt@gnu.org>
197
198 * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
199
200 2021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
201 Jim Wilson <jimw@sifive.com>
202 Andrew Waterman <andrew@sifive.com>
203 Maxim Blinov <maxim.blinov@embecosm.com>
204 Kito Cheng <kito.cheng@sifive.com>
205 Nelson Chu <nelson.chu@sifive.com>
206
207 * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
208 (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
209
210 2021-01-01 Alan Modra <amodra@gmail.com>
211
212 Update year range in copyright notice of all files.
213
214 For older changes see ChangeLog-2020
215 \f
216 Copyright (C) 2021 Free Software Foundation, Inc.
217
218 Copying and distribution of this file, with or without modification,
219 are permitted in any medium without royalty provided the copyright
220 notice and this notice are preserved.
221
222 Local Variables:
223 mode: change-log
224 left-margin: 8
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226 version-control: never
227 End:
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