opcodes/ChangeLog

   1 2019-06-26  Jim Wilson  <jimw@sifive.com>
   2
   3         PR binutils/24739
   4         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
   5         Set info->display_endian to info->endian_code.
   6
   7 2019-06-25  Jan Beulich  <jbeulich@suse.com>
   8
   9         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
  10         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
  11         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
  12         OPERAND_TYPE_ACC64 entries.
  13         * i386-init.h: Re-generate.
  14
  15 2019-06-25  Jan Beulich  <jbeulich@suse.com>
  16
  17         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
  18         Delete.
  19         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
  20         of dqa_mode.
  21         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
  22         entries here.
  23         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
  24         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
  25
  26 2019-06-25  Jan Beulich  <jbeulich@suse.com>
  27
  28         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
  29         variables.
  30
  31 2019-06-25  Jan Beulich  <jbeulich@suse.com>
  32
  33         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
  34         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
  35         movnti.
  36         * i386-opc.tbl (movnti): Add IgnoreSize.
  37         * i386-tbl.h: Re-generate.
  38
  39 2019-06-25  Jan Beulich  <jbeulich@suse.com>
  40
  41         * i386-opc.tbl (and): Mark Imm8S form for optimization.
  42         * i386-tbl.h: Re-generate.
  43
  44 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
  45
  46         * i386-dis-evex.h: Break into ...
  47         * i386-dis-evex-len.h: New file.
  48         * i386-dis-evex-mod.h: Likewise.
  49         * i386-dis-evex-prefix.h: Likewise.
  50         * i386-dis-evex-reg.h: Likewise.
  51         * i386-dis-evex-w.h: Likewise.
  52         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
  53         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
  54         i386-dis-evex-mod.h.
  55
  56 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
  57
  58         PR binutils/24700
  59         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
  60         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
  61         EVEX_W_0F385B_P_2.
  62         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
  63         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
  64         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
  65         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
  66         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
  67         EVEX_LEN_0F385B_P_2_W_1.
  68         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
  69         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
  70         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
  71         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
  72         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
  73         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
  74         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
  75         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
  76         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
  77         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
  78
  79 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
  80
  81         PR binutils/24691
  82         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
  83         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
  84         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
  85         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
  86         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
  87         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
  88         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
  89         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
  90         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
  91         EVEX_LEN_0F3A43_P_2_W_1.
  92         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
  93         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
  94         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
  95         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
  96         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
  97         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
  98         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
  99         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 100         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 101         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 102         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 103         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 104
 105 2019-06-14  Nick Clifton  <nickc@redhat.com>
 106
 107         * po/fr.po; Updated French translation.
 108
 109 2019-06-13  Stafford Horne  <shorne@gmail.com>
 110
 111         * or1k-asm.c: Regenerated.
 112         * or1k-desc.c: Regenerated.
 113         * or1k-desc.h: Regenerated.
 114         * or1k-dis.c: Regenerated.
 115         * or1k-ibld.c: Regenerated.
 116         * or1k-opc.c: Regenerated.
 117         * or1k-opc.h: Regenerated.
 118         * or1k-opinst.c: Regenerated.
 119
 120 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 121
 122         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 123
 124 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 125
 126         PR binutils/24633
 127         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 128         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 129         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 130         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 131         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 132         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 133         EVEX_LEN_0F3A1B_P_2_W_1.
 134         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 135         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 136         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 137         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 138         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 139         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 140         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 141         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 142
 143 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 144
 145         PR binutils/24626
 146         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 147         EVEX.vvvv when disassembling VEX and EVEX instructions.
 148         (OP_VEX): Set vex.register_specifier to 0 after readding
 149         vex.register_specifier.
 150         (OP_Vex_2src_1): Likewise.
 151         (OP_Vex_2src_2): Likewise.
 152         (OP_LWP_E): Likewise.
 153         (OP_EX_Vex): Don't check vex.register_specifier.
 154         (OP_XMM_Vex): Likewise.
 155
 156 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 157             Lili Cui  <lili.cui@intel.com>
 158
 159         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 160         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 161         instructions.
 162         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 163         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 164         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 165         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 166         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 167         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 168         * i386-init.h: Regenerated.
 169         * i386-tbl.h: Likewise.
 170
 171 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 172             Lili Cui  <lili.cui@intel.com>
 173
 174         * doc/c-i386.texi: Document enqcmd.
 175         * testsuite/gas/i386/enqcmd-intel.d: New file.
 176         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 177         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 178         * testsuite/gas/i386/enqcmd.d: Likewise.
 179         * testsuite/gas/i386/enqcmd.s: Likewise.
 180         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 181         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 182         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 183         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 184         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 185         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 186         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 187         and x86-64-enqcmd.
 188
 189 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 190
 191         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 192
 193 2019-06-03  Alan Modra  <amodra@gmail.com>
 194
 195         * ppc-dis.c (prefix_opcd_indices): Correct size.
 196
 197 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 198
 199         PR gas/24625
 200         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 201         Disp8ShiftVL.
 202         * i386-tbl.h: Regenerated.
 203
 204 2019-05-24  Alan Modra  <amodra@gmail.com>
 205
 206         * po/POTFILES.in: Regenerate.
 207
 208 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 209             Alan Modra  <amodra@gmail.com>
 210
 211         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 212         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 213         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 214         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 215         XTOP>): Define and add entries.
 216         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 217         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 218         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 219         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 220
 221 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 222             Alan Modra  <amodra@gmail.com>
 223
 224         * ppc-dis.c (ppc_opts): Add "future" entry.
 225         (PREFIX_OPCD_SEGS): Define.
 226         (prefix_opcd_indices): New array.
 227         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 228         (lookup_prefix): New function.
 229         (print_insn_powerpc): Handle 64-bit prefix instructions.
 230         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 231         (PMRR, POWERXX): Define.
 232         (prefix_opcodes): New instruction table.
 233         (prefix_num_opcodes): New constant.
 234
 235 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 236
 237         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 238         * configure: Regenerated.
 239         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 240         and cpu/bpf.opc.
 241         (HFILES): Add bpf-desc.h and bpf-opc.h.
 242         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 243         bpf-ibld.c and bpf-opc.c.
 244         (BPF_DEPS): Define.
 245         * Makefile.in: Regenerated.
 246         * disassemble.c (ARCH_bpf): Define.
 247         (disassembler): Add case for bfd_arch_bpf.
 248         (disassemble_init_for_target): Likewise.
 249         (enum epbf_isa_attr): Define.
 250         * disassemble.h: extern print_insn_bpf.
 251         * bpf-asm.c: Generated.
 252         * bpf-opc.h: Likewise.
 253         * bpf-opc.c: Likewise.
 254         * bpf-ibld.c: Likewise.
 255         * bpf-dis.c: Likewise.
 256         * bpf-desc.h: Likewise.
 257         * bpf-desc.c: Likewise.
 258
 259 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 260
 261         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 262         and VMSR with the new operands.
 263
 264 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 265
 266         * arm-dis.c (enum mve_instructions): New enum
 267         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 268         and cneg.
 269         (mve_opcodes): New instructions as above.
 270         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 271         csneg and csel.
 272         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 273
 274 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 275
 276         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 277         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 278         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 279         uqshl, urshrl and urshr.
 280         (is_mve_okay_in_it): Add new instructions to TRUE list.
 281         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 282         (print_insn_mve): Updated to accept new %j,
 283         %<bitfield>m and %<bitfield>n patterns.
 284
 285 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 286
 287         * mips-opc.c (mips_builtin_opcodes): Change source register
 288         constraint for DAUI.
 289
 290 2019-05-20  Nick Clifton  <nickc@redhat.com>
 291
 292         * po/fr.po: Updated French translation.
 293
 294 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 295             Michael Collison <michael.collison@arm.com>
 296
 297         * arm-dis.c (thumb32_opcodes): Add new instructions.
 298         (enum mve_instructions): Likewise.
 299         (enum mve_undefined): Add new reasons.
 300         (is_mve_encoding_conflict): Handle new instructions.
 301         (is_mve_undefined): Likewise.
 302         (is_mve_unpredictable): Likewise.
 303         (print_mve_undefined): Likewise.
 304         (print_mve_size): Likewise.
 305
 306 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 307             Michael Collison <michael.collison@arm.com>
 308
 309         * arm-dis.c (thumb32_opcodes): Add new instructions.
 310         (enum mve_instructions): Likewise.
 311         (is_mve_encoding_conflict): Handle new instructions.
 312         (is_mve_undefined): Likewise.
 313         (is_mve_unpredictable): Likewise.
 314         (print_mve_size): Likewise.
 315
 316 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 317             Michael Collison <michael.collison@arm.com>
 318
 319         * arm-dis.c (thumb32_opcodes): Add new instructions.
 320         (enum mve_instructions): Likewise.
 321         (is_mve_encoding_conflict): Likewise.
 322         (is_mve_unpredictable): Likewise.
 323         (print_mve_size): Likewise.
 324
 325 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 326             Michael Collison <michael.collison@arm.com>
 327
 328         * arm-dis.c (thumb32_opcodes): Add new instructions.
 329         (enum mve_instructions): Likewise.
 330         (is_mve_encoding_conflict): Handle new instructions.
 331         (is_mve_undefined): Likewise.
 332         (is_mve_unpredictable): Likewise.
 333         (print_mve_size): Likewise.
 334
 335 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 336             Michael Collison <michael.collison@arm.com>
 337
 338         * arm-dis.c (thumb32_opcodes): Add new instructions.
 339         (enum mve_instructions): Likewise.
 340         (is_mve_encoding_conflict): Handle new instructions.
 341         (is_mve_undefined): Likewise.
 342         (is_mve_unpredictable): Likewise.
 343         (print_mve_size): Likewise.
 344         (print_insn_mve): Likewise.
 345
 346 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 347             Michael Collison <michael.collison@arm.com>
 348
 349         * arm-dis.c (thumb32_opcodes): Add new instructions.
 350         (print_insn_thumb32): Handle new instructions.
 351
 352 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 353             Michael Collison <michael.collison@arm.com>
 354
 355         * arm-dis.c (enum mve_instructions): Add new instructions.
 356         (enum mve_undefined): Add new reasons.
 357         (is_mve_encoding_conflict): Handle new instructions.
 358         (is_mve_undefined): Likewise.
 359         (is_mve_unpredictable): Likewise.
 360         (print_mve_undefined): Likewise.
 361         (print_mve_size): Likewise.
 362         (print_mve_shift_n): Likewise.
 363         (print_insn_mve): Likewise.
 364
 365 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 366             Michael Collison <michael.collison@arm.com>
 367
 368         * arm-dis.c (enum mve_instructions): Add new instructions.
 369         (is_mve_encoding_conflict): Handle new instructions.
 370         (is_mve_unpredictable): Likewise.
 371         (print_mve_rotate): Likewise.
 372         (print_mve_size): Likewise.
 373         (print_insn_mve): Likewise.
 374
 375 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 376             Michael Collison <michael.collison@arm.com>
 377
 378         * arm-dis.c (enum mve_instructions): Add new instructions.
 379         (is_mve_encoding_conflict): Handle new instructions.
 380         (is_mve_unpredictable): Likewise.
 381         (print_mve_size): Likewise.
 382         (print_insn_mve): Likewise.
 383
 384 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 385             Michael Collison <michael.collison@arm.com>
 386
 387         * arm-dis.c (enum mve_instructions): Add new instructions.
 388         (enum mve_undefined): Add new reasons.
 389         (is_mve_encoding_conflict): Handle new instructions.
 390         (is_mve_undefined): Likewise.
 391         (is_mve_unpredictable): Likewise.
 392         (print_mve_undefined): Likewise.
 393         (print_mve_size): Likewise.
 394         (print_insn_mve): Likewise.
 395
 396 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 397             Michael Collison <michael.collison@arm.com>
 398
 399         * arm-dis.c (enum mve_instructions): Add new instructions.
 400         (is_mve_encoding_conflict): Handle new instructions.
 401         (is_mve_undefined): Likewise.
 402         (is_mve_unpredictable): Likewise.
 403         (print_mve_size): Likewise.
 404         (print_insn_mve): Likewise.
 405
 406 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 407             Michael Collison <michael.collison@arm.com>
 408
 409         * arm-dis.c (enum mve_instructions): Add new instructions.
 410         (enum mve_unpredictable): Add new reasons.
 411         (enum mve_undefined): Likewise.
 412         (is_mve_okay_in_it): Handle new isntructions.
 413         (is_mve_encoding_conflict): Likewise.
 414         (is_mve_undefined): Likewise.
 415         (is_mve_unpredictable): Likewise.
 416         (print_mve_vmov_index): Likewise.
 417         (print_simd_imm8): Likewise.
 418         (print_mve_undefined): Likewise.
 419         (print_mve_unpredictable): Likewise.
 420         (print_mve_size): Likewise.
 421         (print_insn_mve): Likewise.
 422
 423 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 424             Michael Collison <michael.collison@arm.com>
 425
 426         * arm-dis.c (enum mve_instructions): Add new instructions.
 427         (enum mve_unpredictable): Add new reasons.
 428         (enum mve_undefined): Likewise.
 429         (is_mve_encoding_conflict): Handle new instructions.
 430         (is_mve_undefined): Likewise.
 431         (is_mve_unpredictable): Likewise.
 432         (print_mve_undefined): Likewise.
 433         (print_mve_unpredictable): Likewise.
 434         (print_mve_rounding_mode): Likewise.
 435         (print_mve_vcvt_size): Likewise.
 436         (print_mve_size): Likewise.
 437         (print_insn_mve): Likewise.
 438
 439 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 440             Michael Collison <michael.collison@arm.com>
 441
 442         * arm-dis.c (enum mve_instructions): Add new instructions.
 443         (enum mve_unpredictable): Add new reasons.
 444         (enum mve_undefined): Likewise.
 445         (is_mve_undefined): Handle new instructions.
 446         (is_mve_unpredictable): Likewise.
 447         (print_mve_undefined): Likewise.
 448         (print_mve_unpredictable): Likewise.
 449         (print_mve_size): Likewise.
 450         (print_insn_mve): Likewise.
 451
 452 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 453             Michael Collison <michael.collison@arm.com>
 454
 455         * arm-dis.c (enum mve_instructions): Add new instructions.
 456         (enum mve_undefined): Add new reasons.
 457         (insns): Add new instructions.
 458         (is_mve_encoding_conflict):
 459         (print_mve_vld_str_addr): New print function.
 460         (is_mve_undefined): Handle new instructions.
 461         (is_mve_unpredictable): Likewise.
 462         (print_mve_undefined): Likewise.
 463         (print_mve_size): Likewise.
 464         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
 465         (print_insn_mve):  Handle new operands.
 466
 467 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 468             Michael Collison <michael.collison@arm.com>
 469
 470         * arm-dis.c (enum mve_instructions): Add new instructions.
 471         (enum mve_unpredictable): Add new reasons.
 472         (is_mve_encoding_conflict): Handle new instructions.
 473         (is_mve_unpredictable): Likewise.
 474         (mve_opcodes): Add new instructions.
 475         (print_mve_unpredictable): Handle new reasons.
 476         (print_mve_register_blocks): New print function.
 477         (print_mve_size): Handle new instructions.
 478         (print_insn_mve): Likewise.
 479
 480 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 481             Michael Collison <michael.collison@arm.com>
 482
 483         * arm-dis.c (enum mve_instructions): Add new instructions.
 484         (enum mve_unpredictable): Add new reasons.
 485         (enum mve_undefined): Likewise.
 486         (is_mve_encoding_conflict): Handle new instructions.
 487         (is_mve_undefined): Likewise.
 488         (is_mve_unpredictable): Likewise.
 489         (coprocessor_opcodes): Move NEON VDUP from here...
 490         (neon_opcodes): ... to here.
 491         (mve_opcodes): Add new instructions.
 492         (print_mve_undefined):  Handle new reasons.
 493         (print_mve_unpredictable): Likewise.
 494         (print_mve_size): Handle new instructions.
 495         (print_insn_neon): Handle vdup.
 496         (print_insn_mve): Handle new operands.
 497
 498 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 499             Michael Collison <michael.collison@arm.com>
 500
 501         * arm-dis.c (enum mve_instructions): Add new instructions.
 502         (enum mve_unpredictable): Add new values.
 503         (mve_opcodes): Add new instructions.
 504         (vec_condnames): New array with vector conditions.
 505         (mve_predicatenames): New array with predicate suffixes.
 506         (mve_vec_sizename): New array with vector sizes.
 507         (enum vpt_pred_state): New enum with vector predication states.
 508         (struct vpt_block): New struct type for vpt blocks.
 509         (vpt_block_state): Global struct to keep track of state.
 510         (mve_extract_pred_mask): New helper function.
 511         (num_instructions_vpt_block): Likewise.
 512         (mark_outside_vpt_block): Likewise.
 513         (mark_inside_vpt_block): Likewise.
 514         (invert_next_predicate_state): Likewise.
 515         (update_next_predicate_state): Likewise.
 516         (update_vpt_block_state): Likewise.
 517         (is_vpt_instruction): Likewise.
 518         (is_mve_encoding_conflict): Add entries for new instructions.
 519         (is_mve_unpredictable): Likewise.
 520         (print_mve_unpredictable): Handle new cases.
 521         (print_instruction_predicate): Likewise.
 522         (print_mve_size): New function.
 523         (print_vec_condition): New function.
 524         (print_insn_mve): Handle vpt blocks and new print operands.
 525
 526 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 527
 528         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
 529         8, 14 and 15 for Armv8.1-M Mainline.
 530
 531 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 532             Michael Collison <michael.collison@arm.com>
 533
 534         * arm-dis.c (enum mve_instructions): New enum.
 535         (enum mve_unpredictable): Likewise.
 536         (enum mve_undefined): Likewise.
 537         (struct mopcode32): New struct.
 538         (is_mve_okay_in_it): New function.
 539         (is_mve_architecture): Likewise.
 540         (arm_decode_field): Likewise.
 541         (arm_decode_field_multiple): Likewise.
 542         (is_mve_encoding_conflict): Likewise.
 543         (is_mve_undefined): Likewise.
 544         (is_mve_unpredictable): Likewise.
 545         (print_mve_undefined): Likewise.
 546         (print_mve_unpredictable): Likewise.
 547         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
 548         (print_insn_mve): New function.
 549         (print_insn_thumb32): Handle MVE architecture.
 550         (select_arm_features): Force thumb for Armv8.1-m Mainline.
 551
 552 2019-05-10  Nick Clifton  <nickc@redhat.com>
 553
 554         PR 24538
 555         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
 556         end of the table prematurely.
 557
 558 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 559
 560         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
 561         macros for R6.
 562
 563 2019-05-11  Alan Modra  <amodra@gmail.com>
 564
 565         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
 566         when -Mraw is in effect.
 567
 568 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 569
 570         * aarch64-dis-2.c: Regenerate.
 571         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
 572         (OP_SVE_BBB): New variant set.
 573         (OP_SVE_DDDD): New variant set.
 574         (OP_SVE_HHH): New variant set.
 575         (OP_SVE_HHHU): New variant set.
 576         (OP_SVE_SSS): New variant set.
 577         (OP_SVE_SSSU): New variant set.
 578         (OP_SVE_SHH): New variant set.
 579         (OP_SVE_SBBU): New variant set.
 580         (OP_SVE_DSS): New variant set.
 581         (OP_SVE_DHHU): New variant set.
 582         (OP_SVE_VMV_HSD_BHS): New variant set.
 583         (OP_SVE_VVU_HSD_BHS): New variant set.
 584         (OP_SVE_VVVU_SD_BH): New variant set.
 585         (OP_SVE_VVVU_BHSD): New variant set.
 586         (OP_SVE_VVV_QHD_DBS): New variant set.
 587         (OP_SVE_VVV_HSD_BHS): New variant set.
 588         (OP_SVE_VVV_HSD_BHS2): New variant set.
 589         (OP_SVE_VVV_BHS_HSD): New variant set.
 590         (OP_SVE_VV_BHS_HSD): New variant set.
 591         (OP_SVE_VVV_SD): New variant set.
 592         (OP_SVE_VVU_BHS_HSD): New variant set.
 593         (OP_SVE_VZVV_SD): New variant set.
 594         (OP_SVE_VZVV_BH): New variant set.
 595         (OP_SVE_VZV_SD): New variant set.
 596         (aarch64_opcode_table): Add sve2 instructions.
 597
 598 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 599
 600         * aarch64-asm-2.c: Regenerated.
 601         * aarch64-dis-2.c: Regenerated.
 602         * aarch64-opc-2.c: Regenerated.
 603         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 604         for SVE_SHLIMM_UNPRED_22.
 605         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
 606         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
 607         operand.
 608
 609 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 610
 611         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 612         sve_size_tsz_bhs iclass encode.
 613         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 614         sve_size_tsz_bhs iclass decode.
 615
 616 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 617
 618         * aarch64-asm-2.c: Regenerated.
 619         * aarch64-dis-2.c: Regenerated.
 620         * aarch64-opc-2.c: Regenerated.
 621         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 622         for SVE_Zm4_11_INDEX.
 623         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
 624         (fields): Handle SVE_i2h field.
 625         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
 626         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
 627
 628 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 629
 630         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 631         sve_shift_tsz_bhsd iclass encode.
 632         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 633         sve_shift_tsz_bhsd iclass decode.
 634
 635 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 636
 637         * aarch64-asm-2.c: Regenerated.
 638         * aarch64-dis-2.c: Regenerated.
 639         * aarch64-opc-2.c: Regenerated.
 640         * aarch64-asm.c (aarch64_ins_sve_shrimm):
 641         (aarch64_encode_variant_using_iclass): Handle
 642         sve_shift_tsz_hsd iclass encode.
 643         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 644         sve_shift_tsz_hsd iclass decode.
 645         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 646         for SVE_SHRIMM_UNPRED_22.
 647         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
 648         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
 649         operand.
 650
 651 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 652
 653         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 654         sve_size_013 iclass encode.
 655         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 656         sve_size_013 iclass decode.
 657
 658 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 659
 660         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 661         sve_size_bh iclass encode.
 662         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 663         sve_size_bh iclass decode.
 664
 665 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 666
 667         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 668         sve_size_sd2 iclass encode.
 669         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 670         sve_size_sd2 iclass decode.
 671         * aarch64-opc.c (fields): Handle SVE_sz2 field.
 672         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
 673
 674 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 675
 676         * aarch64-asm-2.c: Regenerated.
 677         * aarch64-dis-2.c: Regenerated.
 678         * aarch64-opc-2.c: Regenerated.
 679         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 680         for SVE_ADDR_ZX.
 681         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
 682         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
 683
 684 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 685
 686         * aarch64-asm-2.c: Regenerated.
 687         * aarch64-dis-2.c: Regenerated.
 688         * aarch64-opc-2.c: Regenerated.
 689         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 690         for SVE_Zm3_11_INDEX.
 691         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
 692         (fields): Handle SVE_i3l and SVE_i3h2 fields.
 693         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
 694         fields.
 695         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
 696
 697 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 698
 699         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
 700         sve_size_hsd2 iclass encode.
 701         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
 702         sve_size_hsd2 iclass decode.
 703         * aarch64-opc.c (fields): Handle SVE_size field.
 704         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
 705
 706 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 707
 708         * aarch64-asm-2.c: Regenerated.
 709         * aarch64-dis-2.c: Regenerated.
 710         * aarch64-opc-2.c: Regenerated.
 711         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
 712         for SVE_IMM_ROT3.
 713         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
 714         (fields): Handle SVE_rot3 field.
 715         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
 716         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
 717
 718 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 719
 720         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
 721         instructions.
 722
 723 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 724
 725         * aarch64-tbl.h
 726         (aarch64_feature_sve2, aarch64_feature_sve2aes,
 727         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
 728         aarch64_feature_sve2bitperm): New feature sets.
 729         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
 730         for feature set addresses.
 731         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
 732         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
 733
 734 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
 735             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 736
 737         * mips-dis.c (mips_calculate_combination_ases): Add ISA
 738         argument and set ASE_EVA_R6 appropriately.
 739         (set_default_mips_dis_options): Pass ISA to above.
 740         (parse_mips_dis_option): Likewise.
 741         * mips-opc.c (EVAR6): New macro.
 742         (mips_builtin_opcodes): Add llwpe, scwpe.
 743
 744 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
 745
 746         * aarch64-asm-2.c: Regenerated.
 747         * aarch64-dis-2.c: Regenerated.
 748         * aarch64-opc-2.c: Regenerated.
 749         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
 750         AARCH64_OPND_TME_UIMM16.
 751         (aarch64_print_operand): Likewise.
 752         * aarch64-tbl.h (QL_IMM_NIL): New.
 753         (TME): New.
 754         (_TME_INSN): New.
 755         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
 756
 757 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
 758
 759         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
 760
 761 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
 762             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 763
 764         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
 765
 766 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 767
 768         * s12z-opc.h: Add extern "C" bracketing to help
 769         users who wish to use this interface in c++ code.
 770
 771 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 772
 773         * s12z-opc.c (bm_decode): Handle bit map operations with the
 774         "reserved0" mode.
 775
 776 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 777
 778         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
 779         specifier.  Add entries for VLDR and VSTR of system registers.
 780         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
 781         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
 782         of %J and %K format specifier.
 783
 784 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 785
 786         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
 787         Add new entries for VSCCLRM instruction.
 788         (print_insn_coprocessor): Handle new %C format control code.
 789
 790 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 791
 792         * arm-dis.c (enum isa): New enum.
 793         (struct sopcode32): New structure.
 794         (coprocessor_opcodes): change type of entries to struct sopcode32 and
 795         set isa field of all current entries to ANY.
 796         (print_insn_coprocessor): Change type of insn to struct sopcode32.
 797         Only match an entry if its isa field allows the current mode.
 798
 799 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 800
 801         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
 802         CLRM.
 803         (print_insn_thumb32): Add logic to print %n CLRM register list.
 804
 805 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 806
 807         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
 808         and %Q patterns.
 809
 810 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 811
 812         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
 813         (print_insn_thumb32): Edit the switch case for %Z.
 814
 815 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 816
 817         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
 818
 819 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 820
 821         * arm-dis.c (thumb32_opcodes): New instruction bfl.
 822
 823 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 824
 825         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
 826
 827 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 828
 829         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
 830         Arm register with r13 and r15 unpredictable.
 831         (thumb32_opcodes): New instructions for bfx and bflx.
 832
 833 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 834
 835         * arm-dis.c (thumb32_opcodes): New instructions for bf.
 836
 837 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 838
 839         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
 840
 841 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 842
 843         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
 844
 845 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 846
 847         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
 848
 849 2019-04-12  John Darrington <john@darrington.wattle.id.au>
 850
 851         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
 852         "optr". ("operator" is a reserved word in c++).
 853
 854 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 855
 856         * aarch64-opc.c (aarch64_print_operand): Add case for
 857         AARCH64_OPND_Rt_SP.
 858         (verify_constraints): Likewise.
 859         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
 860         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
 861         to accept Rt|SP as first operand.
 862         (AARCH64_OPERANDS): Add new Rt_SP.
 863         * aarch64-asm-2.c: Regenerated.
 864         * aarch64-dis-2.c: Regenerated.
 865         * aarch64-opc-2.c: Regenerated.
 866
 867 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 868
 869         * aarch64-asm-2.c: Regenerated.
 870         * aarch64-dis-2.c: Likewise.
 871         * aarch64-opc-2.c: Likewise.
 872         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
 873
 874 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
 875
 876         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
 877
 878 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
 879
 880         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
 881         * i386-init.h: Regenerated.
 882
 883 2019-04-07  Alan Modra  <amodra@gmail.com>
 884
 885         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
 886         op_separator to control printing of spaces, comma and parens
 887         rather than need_comma, need_paren and spaces vars.
 888
 889 2019-04-07  Alan Modra  <amodra@gmail.com>
 890
 891         PR 24421
 892         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
 893         (print_insn_neon, print_insn_arm): Likewise.
 894
 895 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
 896
 897         * i386-dis-evex.h (evex_table): Updated to support BF16
 898         instructions.
 899         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
 900         and EVEX_W_0F3872_P_3.
 901         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
 902         (cpu_flags): Add bitfield for CpuAVX512_BF16.
 903         * i386-opc.h (enum): Add CpuAVX512_BF16.
 904         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
 905         * i386-opc.tbl: Add AVX512 BF16 instructions.
 906         * i386-init.h: Regenerated.
 907         * i386-tbl.h: Likewise.
 908
 909 2019-04-05  Alan Modra  <amodra@gmail.com>
 910
 911         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
 912         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
 913         to favour printing of "-" branch hint when using the "y" bit.
 914         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
 915
 916 2019-04-05  Alan Modra  <amodra@gmail.com>
 917
 918         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
 919         opcode until first operand is output.
 920
 921 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
 922
 923         PR gas/24349
 924         * ppc-opc.c (valid_bo_pre_v2): Add comments.
 925         (valid_bo_post_v2): Add support for 'at' branch hints.
 926         (insert_bo): Only error on branch on ctr.
 927         (get_bo_hint_mask): New function.
 928         (insert_boe): Add new 'branch_taken' formal argument.  Add support
 929         for inserting 'at' branch hints.
 930         (extract_boe): Add new 'branch_taken' formal argument.  Add support
 931         for extracting 'at' branch hints.
 932         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
 933         (BOE): Delete operand.
 934         (BOM, BOP): New operands.
 935         (RM): Update value.
 936         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
 937         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
 938         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
 939         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
 940         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
 941         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
 942         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
 943         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
 944         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
 945         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
 946         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
 947         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
 948         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
 949         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
 950         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
 951         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
 952         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
 953         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
 954         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
 955         bttarl+>: New extended mnemonics.
 956
 957 2019-03-28  Alan Modra  <amodra@gmail.com>
 958
 959         PR 24390
 960         * ppc-opc.c (BTF): Define.
 961         (powerpc_opcodes): Use for mtfsb*.
 962         * ppc-dis.c (print_insn_powerpc): Print fields with both
 963         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
 964
 965 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 966
 967         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
 968         (mapping_symbol_for_insn): Implement new algorithm.
 969         (print_insn): Remove duplicate code.
 970
 971 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 972
 973         * aarch64-dis.c (print_insn_aarch64):
 974         Implement override.
 975
 976 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 977
 978         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
 979         order.
 980
 981 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 982
 983         * aarch64-dis.c (last_stop_offset): New.
 984         (print_insn_aarch64): Use stop_offset.
 985
 986 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
 987
 988         PR gas/24359
 989         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
 990         CPU_ANY_AVX2_FLAGS.
 991         * i386-init.h: Regenerated.
 992
 993 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
 994
 995         PR gas/24348
 996         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
 997         vmovdqu16, vmovdqu32 and vmovdqu64.
 998         * i386-tbl.h: Regenerated.
 999
1000 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1001
1002         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1003         from vstrszb, vstrszh, and vstrszf.
1004
1005 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1006
1007         * s390-opc.txt: Add instruction descriptions.
1008
1009 2019-02-08  Jim Wilson  <jimw@sifive.com>
1010
1011         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1012         <bne>: Likewise.
1013
1014 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1015
1016         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1017
1018 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1019
1020         PR binutils/23212
1021         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1022         * aarch64-opc.c (verify_elem_sd): New.
1023         (fields): Add FLD_sz entr.
1024         * aarch64-tbl.h (_SIMD_INSN): New.
1025         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1026         fmulx scalar and vector by element isns.
1027
1028 2019-02-07  Nick Clifton  <nickc@redhat.com>
1029
1030         * po/sv.po: Updated Swedish translation.
1031
1032 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1033
1034         * s390-mkopc.c (main): Accept arch13 as cpu string.
1035         * s390-opc.c: Add new instruction formats and instruction opcode
1036         masks.
1037         * s390-opc.txt: Add new arch13 instructions.
1038
1039 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1040
1041         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1042         (aarch64_opcode): Change encoding for stg, stzg
1043         st2g and st2zg.
1044         * aarch64-asm-2.c: Regenerated.
1045         * aarch64-dis-2.c: Regenerated.
1046         * aarch64-opc-2.c: Regenerated.
1047
1048 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1049
1050         * aarch64-asm-2.c: Regenerated.
1051         * aarch64-dis-2.c: Likewise.
1052         * aarch64-opc-2.c: Likewise.
1053         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1054
1055 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1056             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1057
1058         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1059         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1060         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1061         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1062         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1063         case for ldstgv_indexed.
1064         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1065         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1066         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1067         * aarch64-asm-2.c: Regenerated.
1068         * aarch64-dis-2.c: Regenerated.
1069         * aarch64-opc-2.c: Regenerated.
1070
1071 2019-01-23  Nick Clifton  <nickc@redhat.com>
1072
1073         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1074
1075 2019-01-21  Nick Clifton  <nickc@redhat.com>
1076
1077         * po/de.po: Updated German translation.
1078         * po/uk.po: Updated Ukranian translation.
1079
1080 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1081         * mips-dis.c (mips_arch_choices): Fix typo in
1082         gs464, gs464e and gs264e descriptors.
1083
1084 2019-01-19  Nick Clifton  <nickc@redhat.com>
1085
1086         * configure: Regenerate.
1087         * po/opcodes.pot: Regenerate.
1088
1089 2018-06-24  Nick Clifton  <nickc@redhat.com>
1090
1091         2.32 branch created.
1092
1093 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1094
1095         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1096         if it is null.
1097         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1098         zero.
1099
1100 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1101
1102         * configure: Regenerate.
1103
1104 2019-01-07  Alan Modra  <amodra@gmail.com>
1105
1106         * configure: Regenerate.
1107         * po/POTFILES.in: Regenerate.
1108
1109 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1110
1111         * s12z-opc.c: New file.
1112         * s12z-opc.h: New file.
1113         * s12z-dis.c: Removed all code not directly related to display
1114         of instructions.  Used the interface provided by the new files
1115         instead.
1116         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1117         * Makefile.in: Regenerate.
1118         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1119         * configure: Regenerate.
1120
1121 2019-01-01  Alan Modra  <amodra@gmail.com>
1122
1123         Update year range in copyright notice of all files.
1124
1125 For older changes see ChangeLog-2018
1126 \f
1127 Copyright (C) 2019 Free Software Foundation, Inc.
1128
1129 Copying and distribution of this file, with or without modification,
1130 are permitted in any medium without royalty provided the copyright
1131 notice and this notice are preserved.
1132
1133 Local Variables:
1134 mode: change-log
1135 left-margin: 8
1136 fill-column: 74
1137 version-control: never
1138 End: