opcodes/ChangeLog

   1 2014-12-06  Eric Botcazou  <ebotcazou@adacore.com>
   2
   3         * configure.ac: Add Visium support.
   4         * configure: Regenerate.
   5         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add visium-dis.c and
   6         visium-opc.c.
   7         * Makefile.in: Regenerate.
   8         * disassemble.c (ARCH_visium): Define if ARCH_all.
   9         (disassembler): Deal with bfd_arch_visium if ARCH_visium.
  10         * visium-dis.c: New file.
  11         * visium-opc.c: Likewise.
  12         * po/POTFILES.in: Regenerate.
  13
  14 2014-11-30  Alan Modra  <amodra@gmail.com>
  15
  16         * ppc-opc.c (powerpc_opcodes): Make mftb* generate mfspr for
  17         power4 and later.
  18
  19 2014-11-28  Sandra Loosemore  <sandra@codesourcery.com>
  20
  21         * nios2-opc.c (nios2_r1_opcodes): Remove deleted attributes
  22         from descriptors.
  23
  24 2014-11-28  Alan Modra  <amodra@gmail.com>
  25
  26         * ppc-opc.c (powerpc_opcodes <mftb>): Don't deprecate for power7.
  27         (TB): Delete.
  28         (insert_tbr, extract_tbr): Validate tbr number.
  29
  30 2014-11-24  H.J. Lu  <hongjiu.lu@intel.com>
  31
  32         * configure: Regenerated.
  33
  34 2014-11-17  Ilya Tocar  <ilya.tocar@intel.com>
  35
  36         * i386-dis-evex.c (evex_table): Add vpermi2b, vpermt2b, vpermb,
  37         vpmultishiftqb.
  38         * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F3883, EVEX_W_0F3883_P_2.
  39         * i386-gen.c (cpu_flag_init): Add CPU_AVX512VBMI_FLAGS.
  40         (cpu_flags): Add CpuAVX512VBMI.
  41         * i386-opc.h (enum): Add CpuAVX512VBMI.
  42         (i386_cpu_flags): Add cpuavx512vbmi.
  43         * i386-opc.tbl: Add vpmadd52luq, vpmultishiftqb, vpermb, vpermi2b,
  44         vpermt2b.
  45         * i386-init.h: Regenerated.
  46         * i386-tbl.h: Likewise.
  47
  48 2014-11-17  Ilya Tocar  <ilya.tocar@intel.com>
  49
  50         * i386-dis-evex.c (evex_table): Add vpmadd52luq, vpmadd52huq.
  51         * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F38B4,
  52         PREFIX_EVEX_0F38B5.
  53         * i386-gen.c (cpu_flag_init): Add CPU_AVX512IFMA_FLAGS.
  54         (cpu_flags): Add CpuAVX512IFMA.
  55         * i386-opc.h (enum): Add CpuAVX512IFMA.
  56         (i386_cpu_flags): Add cpuavx512ifma.
  57         * i386-opc.tbl: Add vpmadd52huq, vpmadd52luq.
  58         * i386-init.h: Regenerated.
  59         * i386-tbl.h: Likewise.
  60
  61 2014-11-17  Ilya Tocar  <ilya.tocar@intel.com>
  62
  63         * i386-dis.c (PREFIX enum): Add PREFIX_RM_0_0FAE_REG_7.
  64         (prefix_table): Add pcommit.
  65         * i386-gen.c (cpu_flag_init): Add CPU_PCOMMIT_FLAGS.
  66         (cpu_flags): Add CpuPCOMMIT.
  67         * i386-opc.h (enum): Add CpuPCOMMIT.
  68         (i386_cpu_flags): Add cpupcommit.
  69         * i386-opc.tbl: Add pcommit.
  70         * i386-init.h: Regenerated.
  71         * i386-tbl.h: Likewise.
  72
  73 2014-11-17  Ilya Tocar  <ilya.tocar@intel.com>
  74
  75         * i386-dis.c (PREFIX enum): Add PREFIX_0FAE_REG_6.
  76         (prefix_table): Add clwb.
  77         * i386-gen.c (cpu_flag_init): Add CPU_CLWB_FLAGS.
  78         (cpu_flags): Add CpuCLWB.
  79         * i386-opc.h (enum): Add CpuCLWB.
  80         (i386_cpu_flags): Add cpuclwb.
  81         * i386-opc.tbl: Add clwb.
  82         * i386-init.h: Regenerated.
  83         * i386-tbl.h: Likewise.
  84
  85 2014-11-06  Sandra Loosemore  <sandra@codesourcery.com>
  86
  87         * nios2-dis.c (nios2_find_opcode_hash): Add mach parameter.
  88         (nios2_disassemble): Adjust call to nios2_find_opcode_hash.
  89
  90 2014-11-03  Nick Clifton  <nickc@redhat.com>
  91
  92         * po/fi.po: Updated Finnish translation.
  93
  94 2014-10-31  Andrew Pinski  <apinski@cavium.com>
  95             Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>
  96
  97         * mips-dis.c (mips_arch_choices): Add octeon3.
  98         * mips-opc.c (IOCT): Include INSN_OCTEON3.
  99         (IOCT2): Likewise.
 100         (IOCT3): New define.
 101         (IVIRT): New define.
 102         (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 103         tlbinv, tlbinvf, tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp, tlti
 104         IVIRT instructions.
 105         Extend mtm0, mtm1, mtm2, mtp0, mtp1, mtp2 instructions to take another
 106         operand for IOCT3.
 107
 108 2014-10-29  Nick Clifton  <nickc@redhat.com>
 109
 110         * po/de.po: Updated German translation.
 111
 112 2014-10-23  Sandra Loosemore  <sandra@codesourcery.com>
 113
 114         * nios2-opc.c (nios2_builtin_regs): Add regtype field initializers.
 115         (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.  Use new
 116         MATCH_R1_<insn> and MASK_R1_<insn> macros in initializers.  Add
 117         size and format initializers.  Merge 'b' arguments into 'j'.
 118         (NIOS2_NUM_OPCODES): Adjust definition.
 119         (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
 120         (nios2_opcodes): Adjust.
 121         (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
 122         * nios2-dis.c (INSNLEN): Update comment.
 123         (nios2_hash_init, nios2_hash): Delete.
 124         (OPCODE_HASH_SIZE): New.
 125         (nios2_r1_extract_opcode): New.
 126         (nios2_disassembler_state): New.
 127         (nios2_r1_disassembler_state): New.
 128         (nios2_init_opcode_hash): Add state parameter.  Adjust to use it.
 129         (nios2_find_opcode_hash): Use state object.
 130         (bad_opcode): New.
 131         (nios2_print_insn_arg): Add op parameter.  Use it to access
 132         format.  Remove 'b' case.
 133         (nios2_disassemble): Remove special case for nop.  Remove
 134         hard-coded instruction size.
 135
 136 2014-10-21  Jan Beulich  <jbeulich@suse.com>
 137
 138         * ppc-opc.c (powerpc_opcodes): Enable msgclr and msgsnd on Power8.
 139
 140 2014-10-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 141
 142         * sparc-opc.c (sparc-opcodes): Fix several misplaced hwcap
 143         entries.
 144         Annotate several instructions with the HWCAP2_VIS3B hwcap.
 145
 146 2014-10-15  Tristan Gingold  <gingold@adacore.com>
 147
 148         * configure: Regenerate.
 149
 150 2014-10-09  Jose E. Marchesi  &lt;jose.marchesi@oracle.com&gt;
 151
 152         * sparc-opc.c (sparc-opcodes): Remove instructions `chkpt',
 153         `commit', `random', `wr r,r,%cps', `wr r,i,%cps' and `rd %cps,r'.
 154         Annotate table with HWCAP2 bits.
 155         Add instructions xmontmul, xmontsqr, xmpmul.
 156         (sparc-opcodes): Add the `mwait',  `wr r,r,%mwait', `wr
 157         r,i,%mwait' and `rd %mwait,r' instructions.
 158         Add rd/wr instructions for accessing the %mcdper ancillary state
 159         register.
 160         (sparc-opcodes): Add sparc5/vis4.0 instructions:
 161         subxc, subxccc, fpadd8, fpadds8, fpaddus8, fpaddus16, fpcmple8,
 162         fpcmpgt8, fpcmpule16, fpcmpugt16, fpcmpule32, fpcmpugt32, fpmax8,
 163         fpmax16, fpmax32, fpmaxu8, fpmaxu16, fpmaxu32, fpmin8, fpmin16,
 164         fpmin32, fpminu8, fpminu16, fpminu32, fpsub8, fpsubs8, fpsubus8,
 165         fpsubus16, and faligndatai.
 166         * sparc-dis.c (v9a_asr_reg_names): Add the %mwait (%asr28)
 167         ancillary state register to the table.
 168         (print_insn_sparc): Handle the %mcdper ancillary state register.
 169         (print_insn_sparc): Handle new operand type '}'.
 170
 171 2014-09-22  H.J. Lu  <hongjiu.lu@intel.com>
 172
 173         * i386-dis.c (MOD_0F20): Removed.
 174         (MOD_0F21): Likewise.
 175         (MOD_0F22): Likewise.
 176         (MOD_0F23): Likewise.
 177         (dis386_twobyte): Replace MOD_0F20, MOD_0F21, MOD_0F22 and
 178         MOD_0F23 with "movZ".
 179         (mod_table): Remove MOD_0F20, MOD_0F21, MOD_0F22 and MOD_0F23.
 180         (OP_R): Check mod/rm byte and call OP_E_register.
 181
 182 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
 183
 184         * nds32-asm.c (nds32_opcodes, operand_fields, keyword_im5_i,
 185         keyword_im5_m, keyword_accumulator, keyword_aridx, keyword_aridx2,
 186         keyword_aridxi): Add audio ISA extension.
 187         (keyword_gpr, keyword_usr, keyword_sr, keyword_cp, keyword_cpr,
 188         keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm, keyword_dpref_st,
 189         keyword_cctl_lv, keyword_standby_st, keyword_msync_st): Adjust scrope
 190         for nds32-dis.c using.
 191         (build_opcode_syntax): Remove dead code.
 192         (parse_re, parse_a30b20, parse_rt21, parse_rte_start, parse_rte_end,
 193         parse_rte69_start, parse_rte69_end, parse_im5_ip, parse_im5_mr,
 194         parse_im6_ip, parse_im6_iq, parse_im6_mr, parse_im6_ms): Add audio ISA
 195         operand parser.
 196         * nds32-asm.h: Declare.
 197         * nds32-dis.c: Use array nds32_opcodes to disassemble instead of
 198         decoding by switch.
 199
 200 2014-09-15  Andrew Bennett  <andrew.bennett@imgtec.com>
 201             Matthew Fortune  <matthew.fortune@imgtec.com>
 202
 203         * mips-dis.c (mips_arch_choices): Add entries for mips32r6 and
 204         mips64r6.
 205         (parse_mips_dis_option): Allow MSA and virtualization support for
 206         mips64r6.
 207         (mips_print_arg_state): Add fields dest_regno and seen_dest.
 208         (mips_seen_register): New function.
 209         (print_insn_arg): Refactored code to use mips_seen_register
 210         function.  Add support for OP_SAME_RS_RT, OP_CHECK_PREV and
 211         OP_NON_ZERO_REG.  Changed OP_REPEAT_DEST_REG case to print out
 212         the register rather than aborting.
 213         (print_insn_args): Add length argument.  Add code to correctly
 214         calculate the instruction address for pc relative instructions.
 215         (validate_insn_args): New static function.
 216         (print_insn_mips): Prevent jalx disassembling for r6.  Use
 217         validate_insn_args.
 218         (print_insn_micromips): Use validate_insn_args.
 219         all the arguments are valid.
 220         * mips-formats.h (PREV_CHECK): New define.
 221         * mips-opc.c (decode_mips_operand): Add support for -a, -b, -d, -s,
 222         -t, -u, -v, -w, -x, -y, -A, -B, +I, +O, +R, +:, +\, +", +;
 223         (RD_pc): New define.
 224         (FS): New define.
 225         (I37): New define.
 226         (I69): New define.
 227         (mips_builtin_opcodes): Add MIPS R6 instructions.  Exclude recoded
 228         MIPS R6 instructions from MIPS R2 instructions.
 229
 230 2014-09-10  H.J. Lu  <hongjiu.lu@intel.com>
 231
 232         * i386-dis.c (dis386): Replace "P" with "%LP" for iret and sysret.
 233         (putop): Handle "%LP".
 234
 235 2014-09-03  Jiong Wang  <jiong.wang@arm.com>
 236
 237         * aarch64-tbl.h (aarch64_opcode_table): Update encoding for mrs/msr.
 238         * aarch64-dis-2.c: Update auto-generated file.
 239
 240 2014-09-03  Jiong Wang  <jiong.wang@arm.com>
 241
 242         * aarch64-tbl.h (QL_R4NIL): New qualifiers.
 243         (aarch64_feature_lse): New feature added.
 244         (LSE): New Added.
 245         (aarch64_opcode_table): New LSE instructions added.  Improve
 246         descriptions for ldarb/ldarh/ldar.
 247         (aarch64_opcode_table): Describe PAIRREG.
 248         * aarch64-opc.h (aarch64_field_kind): Add FLD_lse_sz.
 249         * aarch64-opc.c (fields): Add entry for F_LSE_SZ.
 250         (aarch64_print_operand): Recognize PAIRREG.
 251         (operand_general_constraint_met_p): Check reg pair constraints for CASP
 252         instructions.
 253         * aarch64-dis.c (aarch64_ext_regno_pair): New extractor for paired reg.
 254         (do_special_decoding): Recognize F_LSE_SZ.
 255         * aarch64-asm.c (do_special_encoding): Recognize F_LSE_SZ.
 256
 257 2014-08-26  Maciej W. Rozycki  <macro@codesourcery.com>
 258
 259         * micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'.
 260         (micromips_opcodes): Use "+J" in place of "B" for "hypcall",
 261         "sdbbp", "syscall" and "wait".
 262
 263 2014-08-21  Nathan Sidwell  <nathan@codesourcery.com>
 264             Maciej W. Rozycki  <macro@codesourcery.com>
 265
 266         * arm-dis.c (print_arm_address): Negate the GPR-relative offset
 267         returned if the U bit is set.
 268
 269 2014-08-21  Maciej W. Rozycki  <macro@codesourcery.com>
 270
 271         * micromips-opc.c (micromips_opcodes): Remove #ifdef-ed out
 272         48-bit "li" encoding.
 273
 274 2014-08-19  Andreas Arnez  <arnez@linux.vnet.ibm.com>
 275
 276         * s390-dis.c (s390_insn_length, s390_insn_matches_opcode)
 277         (s390_print_insn_with_opcode, opcode_mask_more_specific): New
 278         static functions, code was moved from...
 279         (print_insn_s390): ...here.
 280         (s390_extract_operand): Adjust comment.  Change type of first
 281         parameter from 'unsigned char *' to 'const bfd_byte *'.
 282         (union operand_value): New.
 283         (s390_extract_operand): Change return type to union operand_value.
 284         Also avoid integer overflow in sign-extension.
 285         (s390_print_insn_with_opcode): Adjust to changed return value from
 286         s390_extract_operand().  Change "%i" printf format to "%u" for
 287         unsigned values.
 288         (init_disasm): Simplify initialization of opc_index[].  This also
 289         fixes an access after the last element of s390_opcodes[].
 290         (print_insn_s390): Simplify the opcode search loop.
 291         Check architecture mask against all searched opcodes, not just the
 292         first matching one.
 293         (s390_print_insn_with_opcode): Drop function pointer dereferences
 294         without effect.
 295         (print_insn_s390): Likewise.
 296         (s390_insn_length): Simplify formula for return value.
 297         (s390_print_insn_with_opcode): Avoid special handling for the
 298         separator before the first operand.  Use new local variable
 299         'flags' in place of 'operand->flags'.
 300
 301 2014-08-14  Mike Frysinger  <vapier@gentoo.org>
 302
 303         * bfin-dis.c (struct private): Change int's to bfd_boolean's.
 304         (decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
 305         decode_dagMODik_0, decode_LDIMMhalf_0, decode_linkage_0):
 306         Change assignment of 1 to priv->comment to TRUE.
 307         (print_insn_bfin): Change legal to a bfd_boolean.  Change
 308         assignment of 0/1 with priv comment and parallel and legal
 309         to FALSE/TRUE.
 310
 311 2014-08-14  Mike Frysinger  <vapier@gentoo.org>
 312
 313         * bfin-dis.c (OUT): Define.
 314         (decode_CC2stat_0): Declare new op_names array.
 315         Replace multiple if statements with a single one.
 316
 317 2014-08-14  Mike Frysinger  <vapier@gentoo.org>
 318
 319         * bfin-dis.c (struct private): Add iw0.
 320         (_print_insn_bfin): Assign iw0 to priv.iw0.
 321         (print_insn_bfin): Drop ifetch and use priv.iw0.
 322
 323 2014-08-13  Mike Frysinger  <vapier@gentoo.org>
 324
 325         * bfin-dis.c (comment, parallel): Move from global scope ...
 326         (struct private): ... to this new struct.
 327         (decode_ProgCtrl_0, decode_CaCTRL_0, decode_PushPopReg_0,
 328         decode_PushPopMultiple_0, decode_ccMV_0, decode_CCflag_0,
 329         decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
 330         decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
 331         decode_dagMODik_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
 332         decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
 333         decode_pseudoOChar_0, decode_pseudodbg_assert_0, _print_insn_bfin,
 334         print_insn_bfin): Declare private struct.  Use priv's comment and
 335         parallel members.
 336
 337 2014-08-13  Mike Frysinger  <vapier@gentoo.org>
 338
 339         * bfin-dis.c (ifetch): Do not align pc to 2 bytes.
 340         (_print_insn_bfin): Add check for unaligned pc.
 341
 342 2014-08-13  Mike Frysinger  <vapier@gentoo.org>
 343
 344         * bfin-dis.c (ifetch): New function.
 345         (_print_insn_bfin, print_insn_bfin): Call new ifetch and return
 346         -1 when it errors.
 347
 348 2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
 349
 350         * micromips-opc.c (COD): Rename throughout to...
 351         (CM): New define, update to use INSN_COPROC_MOVE.
 352         (LCD): Rename throughout to...
 353         (LC): New define, update to use INSN_LOAD_COPROC.
 354         * mips-opc.c: Likewise.
 355
 356 2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
 357
 358         * micromips-opc.c (COD, LCD) New macros.
 359         (cfc1, ctc1): Remove FP_S attribute.
 360         (dmfc1, mfc1, mfhc1): Add LCD attribute.
 361         (dmtc1, mtc1, mthc1): Add COD attribute.
 362         * mips-opc.c (cfc1, cftc1, ctc, cttc1): Remove FP_S attribute.
 363
 364 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 365             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 366             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 367             Sergey Lega  <sergey.s.lega@intel.com>
 368             Anna Tikhonova  <anna.tikhonova@intel.com>
 369             Ilya Tocar  <ilya.tocar@intel.com>
 370             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 371             Ilya Verbin  <ilya.verbin@intel.com>
 372             Kirill Yukhin  <kirill.yukhin@intel.com>
 373             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 374
 375         * i386-dis-evex.h: Updated.
 376         * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
 377         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0F3A16,
 378         PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A50, PREFIX_EVEX_0F3A51,
 379         PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
 380         PREFIX_EVEX_0F3A67.
 381         (VEX_LEN enum): Add VEX_LEN_0F92_P_2, VEX_LEN_0F93_P_2,
 382         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_2_LEN_0.
 383         (VEX_W enum): Add EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
 384         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2, EVEX_W_0F57_P_0,
 385         EVEX_W_0F57_P_2, EVEX_W_0F78_P_2, EVEX_W_0F79_P_2, EVEX_W_0F7A_P_2,
 386         EVEX_W_0F7B_P_2, EVEX_W_0F3838_P_1, EVEX_W_0F3839_P_1,
 387         EVEX_W_0F3A16_P_2, EVEX_W_0F3A22_P_2, EVEX_W_0F3A50_P_2,
 388         EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2, EVEX_W_0F3A57_P_2,
 389         EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2.
 390         (prefix_table): Add entries for new instructions.
 391         (vex_len_table): Ditto.
 392         (vex_w_table): Ditto.
 393         (OP_E_memory): Update xmmq_mode handling.
 394         * i386-gen.c (cpu_flag_init): Add CPU_AVX512DQ_FLAGS.
 395         (cpu_flags): Add CpuAVX512DQ.
 396         * i386-init.h: Regenerared.
 397         * i386-opc.h (CpuAVX512DQ): New.
 398         (i386_cpu_flags): Add cpuavx512dq.
 399         * i386-opc.tbl: Add AVX512DQ instructions.
 400         * i386-tbl.h: Regenerate.
 401
 402 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 403             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 404             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 405             Sergey Lega  <sergey.s.lega@intel.com>
 406             Anna Tikhonova  <anna.tikhonova@intel.com>
 407             Ilya Tocar  <ilya.tocar@intel.com>
 408             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 409             Ilya Verbin  <ilya.verbin@intel.com>
 410             Kirill Yukhin  <kirill.yukhin@intel.com>
 411             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 412
 413         * i386-dis-evex.h: Add new instructions (prefixes bellow).
 414         * i386-dis.c (fetch_data): Add EdqwS, Edb, Edw, MaskBDE.
 415         (enum): Add dqw_swap_mode, db_mode, dw_mode, mask_bd_mode, REG_EVEX_0F71.
 416         (PREFIX enum): Add PREFIX_VEX_0F4A, PREFIX_VEX_0F99, PREFIX_VEX_0F3A31,
 417         PREFIX_VEX_0F3A33, PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, PREFIX_EVEX_0F63,
 418         PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
 419         PREFIX_EVEX_0F69, PREFIX_EVEX_0F6B, PREFIX_EVEX_0F71_REG_2, PREFIX_EVEX_0F71_REG_4,
 420         PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_7,
 421         PREFIX_EVEX_0F74, PREFIX_EVEX_0F75, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
 422         PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9,
 423         PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
 424         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, PREFIX_EVEX_0FE4,
 425         PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA,
 426         PREFIX_EVEX_0FEC, PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
 427         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, PREFIX_EVEX_0FF9,
 428         PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804,
 429         PREFIX_EVEX_0F380B, PREFIX_EVEX_0F3810, PREFIX_EVEX_0F381C, PREFIX_EVEX_0F381D,
 430         PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3826, PREFIX_EVEX_0F382B, PREFIX_EVEX_0F3830,
 431         PREFIX_EVEX_0F3838, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, PREFIX_EVEX_0F3866,
 432         PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, PREFIX_EVEX_0F387A,
 433         PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387D, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3A0F,
 434         PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15, PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A3E,
 435         PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42.
 436         (VEX_LEN enum): Add VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_2,
 437         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 438         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_2,
 439         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_2, VEX_LEN_0F99_P_0,
 440         VEX_LEN_0F99_P_2, VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A33_P_2, VEX_W_0F41_P_2_LEN_1,
 441         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_2_LEN_1,
 442         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 443         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F90_P_2_LEN_0,
 444         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_3_LEN_0,
 445         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0,
 446         VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0.
 447         (VEX_W enum): Add EVEX_W_0F6B_P_2, EVEX_W_0F6F_P_3, EVEX_W_0F7F_P_3,
 448         EVEX_W_0F3810_P_1, EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_2,
 449         EVEX_W_0F3820_P_1, EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2, EVEX_W_0F3828_P_1,
 450         EVEX_W_0F3829_P_1, EVEX_W_0F382B_P_2, EVEX_W_0F3830_P_1, EVEX_W_0F3866_P_2,
 451         EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F387A_P_2,
 452         EVEX_W_0F387B_P_2, EVEX_W_0F387D_P_2, EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2,
 453         EVEX_W_0F3A3F_P_2, EVEX_W_0F3A42_P_2.
 454         (prefix_table): Add entries for new instructions.
 455         (vex_table) : Ditto.
 456         (vex_len_table): Ditto.
 457         (vex_w_table): Ditto.
 458         (intel_operand_size): Add db_mode, dw_mode, dqw_swap_mode,
 459         mask_bd_mode handling.
 460         (OP_E_register): Add dqw_swap_mode, dw_mode, db_mode, mask_bd_mode
 461         handling.
 462         (OP_E_memory): Add dqw_mode, dw_mode, dqw_swap_mode, dqb_mode, db_mode
 463         handling.
 464         (OP_G): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling.
 465         (OP_EX): Add dqw_swap_mode handling.
 466         (OP_VEX): Add mask_bd_mode handling.
 467         (OP_Mask): Add mask_bd_mode handling.
 468         * i386-gen.c (cpu_flag_init): Add CPU_AVX512BW_FLAGS.
 469         (cpu_flags): Add CpuAVX512BW.
 470         * i386-init.h: Regenerated.
 471         * i386-opc.h (CpuAVX512BW): New.
 472         (i386_cpu_flags): Add cpuavx512bw.
 473         * i386-opc.tbl: Add AVX512BW instructions.
 474         * i386-tbl.h: Regenerate.
 475
 476 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 477             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 478             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 479             Sergey Lega  <sergey.s.lega@intel.com>
 480             Anna Tikhonova  <anna.tikhonova@intel.com>
 481             Ilya Tocar  <ilya.tocar@intel.com>
 482             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 483             Ilya Verbin  <ilya.verbin@intel.com>
 484             Kirill Yukhin  <kirill.yukhin@intel.com>
 485             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 486
 487         * i386-opc.tbl: Add AVX512VL and AVX512CD instructions.
 488         * i386-tbl.h: Regenerate.
 489
 490 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 491             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 492             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 493             Sergey Lega  <sergey.s.lega@intel.com>
 494             Anna Tikhonova  <anna.tikhonova@intel.com>
 495             Ilya Tocar  <ilya.tocar@intel.com>
 496             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 497             Ilya Verbin  <ilya.verbin@intel.com>
 498             Kirill Yukhin  <kirill.yukhin@intel.com>
 499             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 500
 501         * i386-dis.c (intel_operand_size): Support 128/256 length in
 502         vex_vsib_q_w_dq_mode.
 503         (OP_E_memory): Add ymmq_mode handling, handle new broadcast.
 504         * i386-gen.c (cpu_flag_init): Add CPU_AVX512VL_FLAGS.
 505         (cpu_flags): Add CpuAVX512VL.
 506         * i386-init.h: Regenerated.
 507         * i386-opc.h (CpuAVX512VL): New.
 508         (i386_cpu_flags): Add cpuavx512vl.
 509         (BROADCAST_1TO4, BROADCAST_1TO2): Define.
 510         * i386-opc.tbl: Add AVX512VL instructions.
 511         * i386-tbl.h: Regenerate.
 512
 513 2014-07-20  Stefan Kristiansson  <stefan.kristiansson@saunalahti.fi>
 514
 515         * or1k-desc.c, * or1k-desc.h, * or1k-opc.c, * or1k-opc.h,
 516         * or1k-opinst.c: Regenerate.
 517
 518 2014-07-08  Ilya Tocar  <ilya.tocar@intel.com>
 519
 520         * i386-dis-evex.h (EVEX_W_0F10_P_1_M_1): Fix vmovss.
 521         (EVEX_W_0F10_P_3_M_1): Fix vmovsd.
 522
 523 2014-07-04  Alan Modra  <amodra@gmail.com>
 524
 525         * configure.ac: Rename from configure.in.
 526         * Makefile.in: Regenerate.
 527         * config.in: Regenerate.
 528
 529 2014-07-04  Alan Modra  <amodra@gmail.com>
 530
 531         * configure.in: Include bfd/version.m4.
 532         (AC_INIT, AM_INIT_AUTOMAKE): Use modern form.
 533         (BFD_VERSION): Delete.
 534         * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Remove bfd/configure.in.
 535         * configure: Regenerate.
 536         * Makefile.in: Regenerate.
 537
 538 2014-07-01  Barney Stratford   <barney_stratford@fastmail.fm>
 539             Senthil Kumar Selvaraj  <senthil_kumar.selvaraj@atmel.com>
 540             Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 541             Soundararajan  <Sounderarajan.D@atmel.com>
 542
 543         * avr-dis.c (avr_operand): Handle constraint j for 16 bit lds/sts.
 544         (print_insn_avr): Do not select opcode if insn ISA is avrtiny and
 545         machine is not avrtiny.
 546
 547 2014-06-26  Philippe De Muyter <phdm@macqel.be>
 548
 549         * or1k-desc.h (spr_field_masks): Add U suffix to the end of long
 550         constants.
 551
 552 2014-06-12  Alan Modra  <amodra@gmail.com>
 553
 554         * or1k-asm.c, * or1k-desc.c, * or1k-desc.h, * or1k-dis.c,
 555         * or1k-ibld.c, * or1k-opc.c, * or1k-opc.h, * or1k-opinst.c: Regenerate.
 556
 557 2014-06-10  H.J. Lu  <hongjiu.lu@intel.com>
 558
 559         * i386-dis.c (fwait_prefix): New.
 560         (ckprefix): Set fwait_prefix.
 561         (print_insn): Properly print prefixes before fwait.
 562
 563 2014-06-07  Alan Modra  <amodra@gmail.com>
 564
 565         * ppc-opc.c (UISIGNOPT): Define and use with cmpli.
 566
 567 2014-06-05  Joel Brobecker  <brobecker@adacore.com>
 568
 569         * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
 570         bfd's development.sh.
 571         * Makefile.in, configure: Regenerate.
 572
 573 2014-06-03  Nick Clifton  <nickc@redhat.com>
 574
 575         * msp430-dis.c (msp430_doubleoperand): Use extension_word to
 576         decide when extended addressing is being used.
 577
 578 2014-06-02  Eric Botcazou  <ebotcazou@adacore.com>
 579
 580         * sparc-opc.c (cas): Disable for LEON.
 581         (casl): Likewise.
 582
 583 2014-05-20  Alan Modra  <amodra@gmail.com>
 584
 585         * m68k-dis.c: Don't include setjmp.h.
 586
 587 2014-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 588
 589         * i386-dis.c (ADDR16_PREFIX): Removed.
 590         (ADDR32_PREFIX): Likewise.
 591         (DATA16_PREFIX): Likewise.
 592         (DATA32_PREFIX): Likewise.
 593         (prefix_name): Updated.
 594         (print_insn): Simplify data and address size prefixes processing.
 595
 596 2014-05-08  Stefan Kristiansson  <stefan.kristiansson@saunalahti.fi>
 597
 598         * or1k-desc.c: Regenerated.
 599         * or1k-desc.h: Likewise.
 600         * or1k-opc.c: Likewise.
 601         * or1k-opc.h: Likewise.
 602         * or1k-opinst.c: Likewise.
 603
 604 2014-05-07  Andrew Bennett  <andrew.bennett@imgtec.com>
 605
 606         * mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
 607         (I34): New define.
 608         (I36): New define.
 609         (I66): New define.
 610         (I68): New define.
 611         * mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and
 612         mips64r5.
 613         (parse_mips_dis_option): Update MSA and virtualization support to
 614         allow mips64r3 and mips64r5.
 615
 616 2014-05-07  Andrew Bennett  <andrew.bennett@imgtec.com>
 617
 618         * mips-opc.c (G3): Remove I4.
 619
 620 2014-05-05  H.J. Lu  <hongjiu.lu@intel.com>
 621
 622         PR binutils/16893
 623         * i386-dis.c (twobyte_has_mandatory_prefix): New variable.
 624         (end_codep): Likewise.
 625         (mandatory_prefix): Likewise.
 626         (active_seg_prefix): Likewise.
 627         (ckprefix): Set active_seg_prefix to the active segment register
 628         prefix.
 629         (seg_prefix): Removed.
 630         (get_valid_dis386): Use the last of PREFIX_REPNZ and PREFIX_REPZ
 631         for prefix index.  Ignore the index if it is invalid and the
 632         mandatory prefix isn't required.
 633         (print_insn): Set mandatory_prefix if the PREFIX_XXX prefix is
 634         mandatory.  Don't set PREFIX_REPZ/PREFIX_REPNZ/PREFIX_LOCK bits
 635         in used_prefixes here.  Don't print unused prefixes.  Check
 636         active_seg_prefix for the active segment register prefix.
 637         Restore the DFLAG bit in sizeflag if the data size prefix is
 638         unused.  Check the unused mandatory PREFIX_XXX prefixes
 639         (append_seg): Only print the segment register which gets used.
 640         (OP_E_memory): Check active_seg_prefix for the segment register
 641         prefix.
 642         (OP_OFF): Likewise.
 643         (OP_OFF64): Likewise.
 644         (OP_DSreg): Set active_seg_prefix to PREFIX_DS if it is unset.
 645
 646 2014-05-02  H.J. Lu  <hongjiu.lu@intel.com>
 647
 648         PR binutils/16886
 649         * config.in: Regenerated.
 650         * configure: Likewise.
 651         * configure.in: Check if sigsetjmp is available.
 652         * h8500-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 653         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 654         (print_insn_h8500): Replace setjmp with OPCODES_SIGSETJMP.
 655         * i386-dis.c (dis_private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 656         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 657         (print_insn): Replace setjmp with OPCODES_SIGSETJMP.
 658         * ns32k-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 659         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 660         (print_insn_ns32k): Replace setjmp with OPCODES_SIGSETJMP.
 661         * sysdep.h (OPCODES_SIGJMP_BUF): New macro.
 662         (OPCODES_SIGSETJMP): Likewise.
 663         (OPCODES_SIGLONGJMP): Likewise.
 664         * vax-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 665         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 666         (print_insn_vax): Replace setjmp with OPCODES_SIGSETJMP.
 667         * xtensa-dis.c (dis_private): Replace jmp_buf with
 668         OPCODES_SIGJMP_BUF.
 669         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 670         (print_insn_xtensa): Replace setjmp with OPCODES_SIGSETJMP.
 671         * z8k-dis.c(instr_data_s): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 672         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 673         (print_insn_z8k): Replace setjmp with OPCODES_SIGSETJMP.
 674
 675 2014-05-01  H.J. Lu  <hongjiu.lu@intel.com>
 676
 677         PR binutils/16891
 678         * i386-dis.c (print_insn): Handle prefixes before fwait.
 679
 680 2014-04-26  Alan Modra  <amodra@gmail.com>
 681
 682         * po/POTFILES.in: Regenerate.
 683
 684 2014-04-23  Andrew Bennett  <andrew.bennett@imgtec.com>
 685
 686         * mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
 687         to allow the MIPS XPA ASE.
 688         (parse_mips_dis_option): Process the -Mxpa option.
 689         * mips-opc.c (XPA): New define.
 690         (mips_builtin_opcodes): Add MIPS XPA instructions and move the
 691         locations of the ctc0 and cfc0 instructions.
 692
 693 2014-04-22  Christian Svensson  <blue@cmd.nu>
 694
 695         * Makefile.am: Remove openrisc and or32 support.  Add support for or1k.
 696         * configure.in: Likewise.
 697         * disassemble.c: Likewise.
 698         * or1k-asm.c: New file.
 699         * or1k-desc.c: New file.
 700         * or1k-desc.h: New file.
 701         * or1k-dis.c: New file.
 702         * or1k-ibld.c: New file.
 703         * or1k-opc.c: New file.
 704         * or1k-opc.h: New file.
 705         * or1k-opinst.c: New file.
 706         * Makefile.in: Regenerate.
 707         * configure: Regenerate.
 708         * openrisc-asm.c: Delete.
 709         * openrisc-desc.c: Delete.
 710         * openrisc-desc.h: Delete.
 711         * openrisc-dis.c: Delete.
 712         * openrisc-ibld.c: Delete.
 713         * openrisc-opc.c: Delete.
 714         * openrisc-opc.h: Delete.
 715         * or32-dis.c: Delete.
 716         * or32-opc.c: Delete.
 717
 718 2014-04-04  Ilya Tocar  <ilya.tocar@intel.com>
 719
 720         * i386-dis.c (rm_table): Add encls, enclu.
 721         * i386-gen.c (cpu_flag_init): Add CPU_SE1_FLAGS,
 722         (cpu_flags): Add CpuSE1.
 723         * i386-opc.h (enum): Add CpuSE1.
 724         (i386_cpu_flags): Add cpuse1.
 725         * i386-opc.tbl: Add encls, enclu.
 726         * i386-init.h: Regenerated.
 727         * i386-tbl.h: Likewise.
 728
 729 2014-04-02  Anthony Green  <green@moxielogic.com>
 730
 731         * moxie-opc.c (moxie_form1_opc_info): Add sign-extension
 732         instructions, sex.b and sex.s.
 733
 734 2014-03-26  Jiong Wang  <jiong.wang@arm.com>
 735
 736         * aarch64-dis.c (aarch64_ext_ldst_elemlist): Check H/S undefined
 737         instructions.
 738
 739 2014-03-20  Ilya Tocar  <ilya.tocar@intel.com>
 740
 741         * i386-opc.tbl: Change memory size for vgatherpf0qps, vgatherpf1qps,
 742         vscatterpf0qps, vscatterpf1qps, vgatherqps, vpgatherqd, vpscatterqd,
 743         vscatterqps.
 744         * i386-tbl.h: Regenerate.
 745
 746 2014-03-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 747
 748         * sparc-dis.c (v9_hpriv_reg_names): Names for %hstick_offset and
 749         %hstick_enable added.
 750
 751 2014-03-19  Nick Clifton  <nickc@redhat.com>
 752
 753         * rx-decode.opc (bwl): Allow for bogus instructions with a size
 754         field of 3.
 755         (sbwl, ubwl, SCALE): Likewise.
 756         * rx-decode.c: Regenerate.
 757
 758 2014-03-12  Alan Modra  <amodra@gmail.com>
 759
 760         * Makefile.in: Regenerate.
 761
 762 2014-03-05  Alan Modra  <amodra@gmail.com>
 763
 764         Update copyright years.
 765
 766 2014-03-04  Heiher  <r@hev.cc>
 767
 768         * mips-dis.c (mips_arch_choices): Usee ISA_MIPS64R2 for Loongson-3A.
 769
 770 2014-03-04  Richard Sandiford  <rdsandiford@googlemail.com>
 771
 772         * mips-opc.c (mips_builtin_opcodes): Move the udi* instructions
 773         so that they come after the Loongson extensions.
 774
 775 2014-03-03  Alan Modra  <amodra@gmail.com>
 776
 777         * i386-gen.c (process_copyright): Emit copyright notice on one line.
 778
 779 2014-02-28  Alan Modra  <amodra@gmail.com>
 780
 781         * msp430-decode.c: Regenerate.
 782
 783 2014-02-27  Jiong Wang  <jiong.wang@arm.com>
 784
 785         * aarch64-tbl.h (aarch64_opcode_table): Replace IMM0 with
 786         FPIMM0 for fcmeq, fcmgt, fcmge, fcmlt and fcmle.
 787
 788 2014-02-27  Yufeng Zhang  <yufeng.zhang@arm.com>
 789
 790         * aarch64-opc.c (print_register_offset_address): Call
 791         get_int_reg_name to prepare the register name.
 792
 793 2014-02-25  Ilya Tocar  <ilya.tocar@intel.com>
 794
 795         * i386-opc.tbl: Remove wrong variant of vcvtps2ph
 796         * i386-tbl.h: Regenerate.
 797
 798 2014-02-20  Ilya Tocar  <ilya.tocar@intel.com>
 799
 800         * i386-gen.c (cpu_flag_init): Add CPU_PREFETCHWT1_FLAGS/
 801         (cpu_flags): Add CpuPREFETCHWT1.
 802         * i386-init.h: Regenerate.
 803         * i386-opc.h (CpuPREFETCHWT1): New.
 804         (i386_cpu_flags): Add cpuprefetchwt1.
 805         * i386-opc.tbl: Cahnge CPU of prefetchwt1 from CpuAVX512PF to CpuPREFETCHWT1.
 806         * i386-tbl.h: Regenerate.
 807
 808 2014-02-20  Ilya Tocar  <ilya.tocar@intel.com>
 809
 810         * i386-opc.tbl: Change CPU of vptestnmq, vptestnmd from CpuAVX512CD,
 811         to CpuAVX512F.
 812         * i386-tbl.h: Regenerate.
 813
 814 2014-02-19  H.J. Lu  <hongjiu.lu@intel.com>
 815
 816         * i386-gen.c (output_cpu_flags): Don't output trailing space.
 817         (output_opcode_modifier): Likewise.
 818         (output_operand_type): Likewise.
 819         * i386-init.h: Regenerated.
 820         * i386-tbl.h: Likewise.
 821
 822 2014-02-12  Ilya Tocar  <ilya.tocar@intel.com>
 823
 824         * i386-dis.c (MOD enum): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4,
 825         MOD_0FC7_REG_5.
 826         (PREFIX enum): Add PREFIX_0FAE_REG_7.
 827         (reg_table): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4 MOD_0FC7_REG_5.
 828         (prefix_table): Add clflusopt.
 829         (mod_table): Add xrstors, xsavec, xsaves.
 830         * i386-gen.c (cpu_flag_init): Add CPU_CLFLUSHOPT_FLAGS,
 831         CPU_XSAVES_FLAGS, CPU_XSAVEC_FLAGS.
 832         (cpu_flags): Add CpuClflushOpt, CpuXSAVES, CpuXSAVEC.
 833         * i386-init.h: Regenerate.
 834         * i386-opc.tbl: Add clflushopt, xrstors, xrstors64, xsaves,
 835         xsaves64, xsavec, xsavec64.
 836         * i386-tbl.h: Regenerate.
 837
 838 2014-02-10  Alan Modra  <amodra@gmail.com>
 839
 840         * po/POTFILES.in: Regenerate.
 841         * po/opcodes.pot: Regenerate.
 842
 843 2014-01-30  Michael Zolotukhin  <michael.v.zolotukhin@gmail.com>
 844             Jan Beulich  <jbeulich@suse.com>
 845
 846         PR binutils/16490
 847         * i386-dis.c (OP_E_memory): Fix shift computation for
 848         vex_vsib_q_w_dq_mode.
 849
 850 2014-01-09  Bradley Nelson  <bradnelson@google.com>
 851             Roland McGrath  <mcgrathr@google.com>
 852
 853         * i386-dis.c (print_insn): Do not touch all_prefixes[-1] when
 854         last_rex_prefix is -1.
 855
 856 2014-01-08  H.J. Lu  <hongjiu.lu@intel.com>
 857
 858         * i386-gen.c (process_copyright): Update copyright year to 2014.
 859
 860 2014-01-03  Maciej W. Rozycki  <macro@codesourcery.com>
 861
 862         * nds32-asm.c (parse_operand): Fix out-of-range integer constant.
 863
 864 For older changes see ChangeLog-2013
 865 \f
 866 Copyright (C) 2014 Free Software Foundation, Inc.
 867
 868 Copying and distribution of this file, with or without modification,
 869 are permitted in any medium without royalty provided the copyright
 870 notice and this notice are preserved.
 871
 872 Local Variables:
 873 mode: change-log
 874 left-margin: 8
 875 fill-column: 74
 876 version-control: never
 877 End: